CY2XF33 PRELIMINARY High Performance LVDS Oscillator with Frequency Margining - Pin Control Features Functional Description ■ Low Jitter Crystal Oscillator (XO) The CY2XF33 is a high performance and high frequency Crystal Oscillator (XO). It uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed through two select pins, allowing easy frequency margin testing in applications. ■ Less than 1 ps Typical RMS Phase Jitter ■ Differential LVDS Output ■ Output Frequency from 50 MHz to 690 MHz ■ Two Frequency Margining Control Pins (FS0, FS1) ■ Factory Configured or Field Programmable ■ Integrated Phase-Locked Loop (PLL) ■ Supply Voltage: 3.3V or 2.5V ■ Pb-Free Package: 5.0 x 3.2 mm LCC ■ Commercial and Industrial Temperature Ranges The CY2XF33 is available as a factory configured device or as a field programmable device. Logic Block Diagram C RYSTAL OSCILLATOR FS0 LOW -NOISE PLL 4 CLK 5 CLK# OUTPUT DIVIDER 1 FREQUENCY SELECT DECODE FS1 2 Pinouts Figure 1. Pin Diagram - 6 Pin Ceramic LCC FS0 1 6 VDD FS1 2 5 CLK# VSS 3 4 CLK Table 1. Pin Definitions - 6 Pin Ceramic LCC Pin Name I/O Type Description 1, 2 FS0, FS1 CMOS Input Frequency Select 4, 5 CLK, CLK# LVDS Output Differential Output Clock 6 VDD Power Supply Voltage: 2.5V or 3.3V 3 VSS Power Ground Cypress Semiconductor Corporation Document Number: 001-53148 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 18, 2009 [+] Feedback CY2XF33 PRELIMINARY Functional Description Programming Variables The FS0 and FS1 pins select between four different output frequencies, as shown in Table 2. Frequency margining is a common application for this feature. One frequency is used for the standard operating mode of the device, while the other frequencies are available for margin testing, either during product development or in system manufacturing test. Output Frequencies Table 2. Frequency Select FS1 FS0 Output Frequency 0 0 Frequency 0 0 1 Frequency 1 1 0 Frequency 2 1 1 Frequency 3 When changing the output frequency, the frequency transition is not guaranteed to be smooth. There can be frequency excursions beyond the start frequency and the new frequency. Glitches and runt pulses are possible, and time must be allowed for the PLL to relock. Programming Description The CY2XF33 is a programmable device. Before being used in an application, it must be programmed with the output frequencies and other variables described in a later section. Two different device types are available, each with its own programming flow. They are described in the following sections. The CY2XF33 is programmed with up to four independent output frequencies, which are then selected using the FS0 and FS1 pins. The device can synthesize frequencies to a resolution of 1 part per million (ppm), but the actual accuracy of the output frequency is limited by the accuracy of the integrated reference crystal. The CY2XF33 has an output frequency range of 50 MHz to 690 MHz, but the range is not continuous. The CY2XF33 cannot generate frequencies in the ranges of 521 MHz to 529 MHz and 596 MHz to 617 MHz. Industrial Versus Commercial Device Performance Industrial and Commercial devices have different internal crystals. This has a potentially significant impact on performance levels for applications requiring the lowest possible phase noise. CyberClocks Online Software displays expected performance for both options. Phase Noise Versus Jitter Performance In most cases, the device configuration for optimal phase noise performance is different from the device configuration for optimal cycle to cycle or period jitter. CyberClocks Online Software includes algorithms to optimize performance for either parameter. Table 3. Device Programming Variables Variable Field Programmable CY2XF33F Output Frequency 0 (Power on default) Field programmable devices are shipped unprogrammed and must be programmed before being installed on a printed circuit board (PCB). Customers use CyberClocks™ Online Software to specify the device configuration and generate a JEDEC (extension .jed) programming file. Programming of samples and prototype quantities is available using a Cypress programmer. Third party vendors manufacture programmers for small to large volume applications. Cypress’s value added distribution partners also provide programming services. Field programmable devices are designated with an “F” in the part number. They are intended for quick prototyping and inventory reduction. The CY2XF33 is one time programmable (OTP). Output Frequency 1 Output Frequency 2 Output Frequency 3 Optimization (phase noise or jitter) Temperature range (Commercial or Industrial) The software is located at www.cyberclocksonline.com. Factory Configured CY2XF33 For customers wanting ready-to-use devices, the CY2XF33 is available with no field programming required. All requests are submitted to the local Cypress Field Application Engineer (FAE) or sales representative. After the request is processed, the user receives a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample requests and production orders. Document Number: 001-53148 Rev. *B Page 2 of 7 [+] Feedback CY2XF33 PRELIMINARY Absolute Maximum Conditions Parameter Description Condition Min Max Unit VDD Supply Voltage –0.5 4.4 V VIN[1] Input Voltage, DC Relative to VSS –0.5 VDD+0.5 V TS Temperature, Storage Non operating –55 135 °C TJ Temperature, Junction –40 135 °C ESDHBM ESD Protection (Human Body Model) JEDEC STD 22-A114-B ΘJA[2] Thermal Resistance, Junction to Ambient 0 m/s airflow 2000 – V °C/W 64 Operating Conditions Parameter VDD Min Typ Max Unit 3.3V Supply Voltage Range Description 3.135 3.3 3.465 V 2.5V Supply Voltage Range 2.375 2.5 2.625 V TPU Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp is Monotonic) 0.05 – 500 ms TA Ambient Temperature (Commercial) 0 – 70 °C –40 – 85 °C Condition Min Typ Max Unit VDD = 3.465V, CLK = 150 MHz, output terminated – – 120 mA VDD = 2.625V, CLK = 150 MHz, output terminated – – 115 mA Ambient Temperature (Industrial) DC Electrical Characteristics Parameter IDD[3] Description Operating Supply Current VOD LVDS Differential Output Voltage VDD = 3.3V or 2.5V, defined in Figure 3 as terminated in Figure 2 247 – 454 mV ΔVOD Change in VOD between Complementary Output States VDD = 3.3V or 2.5V, defined in Figure 3 as terminated in Figure 2 – – 50 mV VOS LVDS Offset Output Voltage VDD = 3.3V or 2.5V, defined in Figure 4 as terminated in Figure 2 1.125 – 1.375 V ΔVOS Change in VOS between Complementary Output States VDD = 3.3V or 2.5V, RTERM = 100Ω between CLK and CLK# – – 50 mV VIH Input High Voltage 0.7*VDD – – V VIL Input Low Voltage – – 0.3*VDD V IIH0 Input High Current, FS0 pin Input = VDD – – 115 μA IIH1 Input High Current, FS1 pin Input = VDD – – 10 μA IIL0 Input Low Current, FS0 pin Input = VSS –50 – – μA IIL1 Input Low Current, FS1 pin Input = VSS –20 – – μA CIN0[4] CIN1[4] Input Capacitance, FS0 pin – 15 – pF Input Capacitance, FS1 pin – 4 – pF Notes 1. The voltage on any input or IO pin cannot exceed the power pin during power up. 2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors. 4. Not 100% tested, guaranteed by design and characterization. Document Number: 001-53148 Rev. *B Page 3 of 7 [+] Feedback CY2XF33 PRELIMINARY AC Electrical Characteristics[4] Parameter Description FOUT Output Frequency[6] FSC Frequency Stability, commercial devices[5] FSI Frequency Stability, industrial devices[5] Condition Min Typ Max Unit 50 – 690 MHz TA = 0°C to 70°C – – ±35 ppm TA = –40° to 85°C – – ±55 ppm – – ±15 ppm F <= 450 MHz, measured at zero crossing 45 50 55 % AG Aging, 10 years TDC Output Duty Cycle F > 450 MHz, measured at zero crossing 40 50 60 % TR, TF Output Rise and Fall Time 20% and 80% of full output swing – 0.35 1.0 ns TLOCK Startup Time Time for CLK to reach valid frequency measured from the time VDD = VDD(min) – – 5 ms TLFS Re-lock Time Time for CLK to reach valid frequency from FS0 or FS1 pin change – – 1 ms TJitter(φ) RMS Phase Jitter (Random) fOUT = 106.25 MHz (12 kHz–20 MHz) – 1 – ps Termination Circuits Figure 2. LVDS Termination CLK 100Ω CLK# Notes 5. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage. 6. This parameter is specified in CyberClocks Online software. Document Number: 001-53148 Rev. *B Page 4 of 7 [+] Feedback CY2XF33 PRELIMINARY Switching Waveforms Figure 3. Output Voltage Swing CLK# VOD1 VOD2 CLK ΔVOD = VOD1 - VOD2 Figure 4. Output Offset Voltage CLK 50Ω V OS 50Ω CLK# Figure 5. Output Duty Cycle Timing CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Figure 6. Output Rise and Fall Time CLK# CLK 80% 80% 20% 20% TR TF Figure 7. RMS Phase Jitter Phase noise Noise Power Phase noise mark Offset Frequency f1 RMS Jitter = Document Number: 001-53148 Rev. *B f2 Area Under the Masked Phase Noise Plot Page 5 of 7 [+] Feedback CY2XF33 PRELIMINARY Ordering Information Part Number[7] Configuration Package Description Product Flow Pb-Free CY2XF33FLXCT Field Programmable 6-Pin Ceramic LCC SMD - Tape and Reel Commercial, 0° to 70°C CY2XF33FLXIT Field Programmable 6-Pin Ceramic LCC SMD - Tape and Reel Industrial, –40° to 85°C CY2XF33LXCxxxT Factory Configured 6-Pin Ceramic LCC SMD - Tape and Reel Commercial, 0° to 70°C CY2XF33LXIxxxT Factory Configured 6-Pin Ceramic LCC SMD - Tape and Reel Industrial, –40° to 85°C Package Drawings and Dimensions Figure 8. 6-Pin 3.2x5.0 mm Ceramic LCC LZ06A 0.50 1.30 Max 2.54 TYP. SIDE VIEW 0.64 TYP. TYP. 0.20 R REF. 5 4 0.32 R INDEX 6 10 7 9 8 TYP. 1.2 TYP. 3 2 0.45 REF. TOP VIEW 1 0.10 REF. 3.2 TYP. 1.27 5.0 0.10 R REF. BOTTOM VIEW Dimensions in mm General Tolerance: ± 0.15MM Kyocera dwg ref KD-VA6432-A 001-10044-** Package Weight ~ 0.12 grams . Note 7. “xxx” is a factory assigned code that identifies the programming option. Document Number: 001-53148 Rev. *B Page 6 of 7 [+] Feedback PRELIMINARY CY2XF33 Document History Page Document Title: CY2XF33 High Performance LVDS Oscillator with Frequency Margining - Pin Control Document Number: 001-53148 REV. ECN NO. Orig. of Change Submission Date Description of Change ** 2704379 *A 2734005 KVM/PYRS 05/11/2009 New data sheet WWZ 07/09/2009 Post to external web *B 2764787 KVM 09/18/2009 Change VOD limits from 250/450 mV to 247/454 mV Add max limit for TR, TF: 1.0 ns Change TLOCK max from 10 ms to 5 ms Change TLFS max from 10 ms to 1 ms Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53148 Rev. *B Revised September 18, 2009 Page 7 of 7 CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback