PRELIMINARY CY2XP22 Crystal to LVPECL Clock Generator Features ■ One LVPECL Output Pair ■ Pb-free 8-Pin TSSOP Package ■ Selectable Frequency Multiplication: x2.5 or x5 ■ Supply Voltage: 3.3V or 2.5V ■ External Crystal Frequency: 25.0 MHz ■ Commercial and Industrial Temperature Ranges ■ Output Frequency: 62.5 MHz or 125 MHz Functional Description ■ Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal (1.875 MHz to 20 MHz): 0.4 ps (Typical) ■ Phase Noise at 125 MHz: Offset Noise Power 1 kHz –117 dBc/Hz 10 kHz –126 dBc/Hz 100 kHz –131 dBc/Hz 1 MHz –131 dBc/Hz The CY2XP22 is a PLL (Phase Locked Loop) based high performance clock generator that uses an external reference crystal. It is specifically targeted at FibreChannel and Gigabit Ethernet applications. It produces a selectable output frequency that is 2.5 or 5 times the crystal frequency. With a 25 MHz crystal, the user can select either a 62.5 MHz or 125 MHz output. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter. The CY2XP22 has a crystal oscillator interface input and one LVPECL output pair. Logic Block Diagram XIN External Crystal CRYSTAL OSCILLATOR LOW -N OISE PLL OUTPUT DIVIDER CLK CLK# XOUT F _SEL Pinouts Figure 1. Pin Diagram - 8-Pin TSSOP VDD VSS XOUT XIN 1 2 3 4 8 7 6 5 VDD CLK CLK# F_SEL Table 1. Pin Definition - 8-Pin TSSOP Pin Number Pin Name I/O Type Description 1, 8 VDD Power 2 VSS Power Ground 3, 4 XOUT, XIN XTAL output and input Parallel resonant crystal interface 5 F_SEL CMOS input Frequency Select: see Frequency Table 6,7 CLK#, CLK LVPECL output Differential Clock Output Cypress Semiconductor Corporation Document #: 001-10229 Rev. *C 3.3V or 2.5V power supply • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 15, 2009 [+] Feedback PRELIMINARY CY2XP22 Frequency Table Inputs PLL Multiplier Value Output Frequency (MHz) 0 5 125 1 2.5 62.5 Crystal Frequency (MHz) F_SEL 25 Absolute Maximum Conditions Parameter Description Conditions Min Max Unit VDD Supply Voltage –0.5 4.4 V VIN[1] Input Voltage, DC Relative to VSS –0.5 VDD + 0.5 V TS Temperature, Storage Non operating –65 150 °C TJ Temperature, Junction 135 °C ESDHBM ESD Protection, Human Body Model JEDEC STD 22-A114-B UL–94 Flammability Rating At 1/8 in. V–0 ΘJA[2] Thermal Resistance, Junction to Ambient 2000 V 0 m/s airflow 100 1 m/s airflow 91 2.5 m/s airflow 87 °C/W Operating Conditions Parameter VDD TA TPU Min Max Unit 3.3V Supply Voltage Description 3.135 3.465 V 2.5V Supply Voltage 2.375 2.625 V 0 70 °C Ambient Temperature, Commercial Ambient Temperature, Industrial –40 85 °C Power up time for all VDD to reach minimum specified voltage (ensure power ramps is monotonic) 0.05 500 ms DC Electrical Characteristics Parameter IDD[3] Description Operating Supply Current with output terminated Min Typ Max Unit VDD = 3.465V, FOUT = 125 MHz, output terminated Test Conditions – – 150 mA VDD = 2.625V, FOUT = 125 MHz, output terminated – – 145 mA VOH LVPECL Output High Voltage VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD –1.15 VDD – 2.0V – VDD –0.75 V VOL LVPECL Output Low Voltage VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD – 2.0V VDD –2.0 – VDD –1.625 V VOD1 LVPECL Peak-to-Peak Output Voltage Swing VDD = 3.3V or 2.5V, RTERM = 50Ω to VDD – 2.0V 600 – 1000 mV VOD2 LVPECL Output Voltage Swing (VOH - VOL) VDD = 2.5V, RTERM = 50Ω to VDD – 1.5V 500 – 1000 mV Notes 1. The voltage on any input or IO pin cannot exceed the power pin during power up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. IDD includes approximately 24 mA of current that is dissipated externally in the output termination resistors. Document #: 001-10229 Rev. *C Page 2 of 8 [+] Feedback PRELIMINARY CY2XP22 DC Electrical Characteristics (continued) Parameter Description Test Conditions Min Typ Max Unit 1.2 – – V VOCM LVPECL Output Common Mode VDD = 2.5V, RTERM = 50Ω to VDD – Voltage (VOH + VOL)/2 1.5V VIH Input High Voltage, F_SEL 0.7*VDD – VDD + 0.3 V VIL Input Low Voltage, F_SEL –0.3 – 0.3*VDD V IIH Input High Current, F_SEL F_SEL = VDD – – 115 µA IIL Input Low Current, F_SEL F_SEL = VSS –50 – – µA CIN Input Capacitance, F_SEL 15 pF CINX Pin Capacitance, XIN & XOUT 4.5 pF AC Electrical Characteristics[4] Parameter Description FOUT Output Frequency TR, TF Output Rise or Fall Time TJitter(φ) RMS Phase Jitter (Random) TDC Output Duty Cycle TLOCK Startup Time Conditions Min Typ Max Unit 62.5 – 125 MHz 20% to 80% of full output swing – 500 – ps 125 MHz, (1.875–20 MHz) – 0.4 – ps Measured at zero crossing point 48 50 52 % Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) or from F_SEL changing – – 10 ms Min Max Unit Recommended Crystal Specifications[5] Parameter Description Mode Mode of Oscillation F Frequency Fundamental 25 25 MHz ESR Equivalent Series Resistance – 50 Ω C0 Shunt Capacitance – 7 pF Notes 4. Not 100% tested, guaranteed by design and characterization. 5. Characterized using an 18 pF parallel resonant crystal. Document #: 001-10229 Rev. *C Page 3 of 8 [+] Feedback PRELIMINARY CY2XP22 Parameter Measurements Figure 2. 3.3V Output Load AC Test Circuit 2V VDD SCOPE Z = 50Ω CLK Z = 50Ω CLK# 50Ω LVPECL VSS 50Ω -1.3V +/- 0.165V Figure 3. 2.5V Output Load AC Test Circuit 2V VDD SCOPE Z = 50Ω CLK Z = 50Ω CLK# 50Ω LVPECL VSS 50Ω -0.5V +/- 0.125V Figure 4. Output DC Parameters VA CLK VOD VOCM = (V A + VB)/2 CLK# VB Figure 5. Output Rise and Fall Time CLK# CLK 80% 20% 20% TR Document #: 001-10229 Rev. *C 80% TF Page 4 of 8 [+] Feedback PRELIMINARY CY2XP22 Figure 6. RMS Phase Jitter Phase noise Noise Power Phase noise mask Offset Frequency f2 f1 RMS Jitter = Area Under the Masked Phase Noise Plot Figure 7. Output Duty Cycle CLK TDC = TPW TPERIOD CLK# TPW TPERIOD Document #: 001-10229 Rev. *C Page 5 of 8 [+] Feedback PRELIMINARY CY2XP22 Application Information Power Supply Filtering Techniques As in any high speed analog circuitry, noise at the power supply pins can degrade performance. To achieve optimum jitter performance, use good power supply isolation practices. Figure 8 illustrates a typical filtering scheme. Since all the current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip capacitor is also located close to this pin to provide a short and low impedance AC path to ground. A 1 to 10 µF ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. Figure 9. LVPECL Output Termination 3.3V 125Ω 125Ω Z0 = 50Ω CLK CLK# IN Z0 = 50Ω 84Ω 84Ω Figure 8. Power Supply Filtering Crystal Interface V DD (Pin 8) VDD (Pin 1) 3.3V 0.1μF 0.01 µF 10µF The CY2XP22 is characterized with 18 pF parallel resonant crystals. The capacitor values shown in Figure 10 are determined using a 25 MHz 18 pF parallel resonant crystal and are chosen to minimize the ppm error. Note that the optimal values for C1 and C2 depend on the parasitic trace capacitance and are thus layout dependent. Figure 10. Crystal Input Interface XIN Termination for LVPECL Output The CY2XP22 implements its LVPECL driver with a current steering design. For proper operation, it requires a 50 ohm dc termination on each of the two output signals. For 3.3V operation, this data sheet specifies output levels for termination to VDD–2.0V. This same termination voltage can also be used for VDD = 2.5V operation, or it can be terminated to VDD-1.5V. Note that it is also possible to terminate with 50 ohms to ground (VSS), but the high and low signal levels differ from the data sheet values. Termination resistors are best located close to the destination device. To avoid reflections, trace characteristic impedance (Z0) should match the termination impedance. Figure 9 shows a standard termination scheme. Document #: 001-10229 Rev. *C X1 18 pF Parallel Crystal C1 30 pF Device XOUT C2 27 pF Page 6 of 8 [+] Feedback PRELIMINARY CY2XP22 Ordering Information Part Number Package Type Product Flow CY2XP22ZXC 8-pin TSSOP Commercial, 0°C to 70°C CY2XP22ZXCT 8-pin TSSOP - Tape and Reel Commercial, 0°C to 70°C CY2XP22ZXI 8-pin TSSOP Industrial, -40°C to 85°C CY2XP22ZXIT 8-pin TSSOP - Tape and Reel Industrial, -40°C to 85°C Package Drawing and Dimensions Figure 11. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 8 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] 2.90[0.114] 3.10[0.122] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85093-*A Document #: 001-10229 Rev. *C Page 7 of 8 [+] Feedback PRELIMINARY CY2XP22 Document History Page Document Title: CY2XP22 Crystal to LVPECL Clock Generator Document Number: 001-10229 REV. ECN NO. Submission Date Orig. of Change Description of Change ** 506262 See ECN RGL New Data Sheet *A 838060 See ECN RGL Changed status from Advance to Preliminary *B 2700242 04/30/2009 *C 2718898 06/15/09 KVM/PYRS Reformatted Revised phase noise values Replaced VCC with VDD; VEE with VSS; updated pin names Removed pull-up resistor on F_SEL Corrected temperature range, added industrial temperature range Increased IDD from 120 / 100 mA to 150 / 140 mA Added CINX parameter, revised CIN parameter Revised LVPECL output specs Added thermal resistance information Changed VIL, VIH, IIL & IIH specs Revised suggested crystal load capacitor values WWZ Minor ECN to post data sheet to external web Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. 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Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-10229 Rev. *C Revised June 15, 2009 Page 8 of 8 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback