CY2XL11 100 MHz LVDS Clock Generator 100 MHz LVDS Clock Generator Features Functional Description ■ One low-voltage differential signaling (LVDS) output pair ■ Output frequency: 100 MHz ■ External crystal frequency: 25 MHz ■ Low RMS phase jitter at 100 MHz, using 25 MHz crystal (637 kHz to 10 MHz): 0.53 ps (typical) ■ Pb-free 8-Pin TSSOP package ■ Supply voltage: 3.3 V or 2.5 V ■ Commercial temperature range The CY2XL11 is a PLL based high performance clock generator with a crystal oscillator interface and one LVDS output pair. It is optimized to generate PCI Express, FC, and other highperformance clock frequencies. It also produces an output frequency that is four times the crystal frequency. It uses Cypress’s low-noise VCO technology to achieve less than 1 ps typical RMS phase jitter, that meets high-performance systems’ jitter requirements. For a complete list of related documentation, click here. Logic Block Diagram XIN External Crystal Crystal Oscillator Output Divider Low-Noise PLL CLK CLK# XOUT OE Cypress Semiconductor Corporation Document Number: 001-42886 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 28, 2014 CY2XL11 Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Frequency Table ............................................................... 4 Absolute Maximum Conditions ....................................... 4 Operating Conditions ....................................................... 4 DC Electrical Characteristics .......................................... 5 AC Electrical Characteristics .......................................... 6 Crystal Characteristics .................................................... 6 Switching Waveforms ...................................................... 7 Termination Circuits ......................................................... 8 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Document Number: 001-42886 Rev. *H Package Drawing and Dimensions ............................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measures ..................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC® Solutions ...................................................... 13 Cypress Developer Community ................................. 13 Technical Support ..................................................... 13 Page 2 of 13 CY2XL11 Pinouts Figure 1. 8-pin TSSOP pinout VDD VSS XOUT XIN 1 2 3 4 8 7 6 5 VDD CLK CLK# OE Pin Definitions Pin Number Pin Name I/O Type Description 1, 8 VDD Power 3.3 V or 2.5 V power supply. All supply current flows through pin 1 2 VSS Power Ground 3, 4 XOUT, XIN 5 OE CMOS input Output enable. When HIGH, the output is enabled. When LOW, the output is high-impedance 6,7 CLK#, CLK LVDS output Differential clock output XTAL output and input Parallel resonant crystal interface Document Number: 001-42886 Rev. *H Page 3 of 13 CY2XL11 Frequency Table Input Crystal Frequency (MHz) PLL Multiplier Value Output Frequency (MHz) 25 4 100 Absolute Maximum Conditions Parameter Description Condition Min Max Unit VDD Supply voltage – –0.5 4.4 V VIN[1] Input voltage, DC Relative to VSS –0.5 VDD + 0.5 V TS Temperature, storage Non operating –65 150 C TJ Temperature, junction – – 135 C ESDHBM ESD protection (human body model) JEDEC STD 22-A114-B 2000 – V UL–94 Flammability rating At 1/8 inch V–0 JA[2] Thermal resistance, junction to ambient 0 m/s airflow 100 1 m/s airflow 91 2.5 m/s airflow 87 C/W Operating Conditions Parameter VDD Description Min Max Unit 3.3 V supply voltage 3.135 3.465 V 2.5 V supply voltage 2.375 2.625 V TA Ambient temperature –5 70 C TPU Power up time for all VDD to reach minimum specified voltage (ensure power ramps is monotonic) 0.05 500 ms Notes 1. The voltage on any input or IO pin cannot exceed the power pin during power up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. Document Number: 001-42886 Rev. *H Page 4 of 13 CY2XL11 DC Electrical Characteristics Parameter IDD[4] Description Test Conditions Min Typ Max Unit Power supply current with output VDD = 3.465 V, OE = VDD, terminated output terminated – – 120 mA VDD = 2.625 V, OE = VDD, output terminated – – 115 mA VOD[6] LVDS differential output voltage VDD = 3.3 V or 2.5 V, RTERM = 100 between CLK and CLK# 247 – 454 mV VOD[6] Change in VOD between complementary output states VDD = 3.3 V or 2.5 V, RTERM = 100 between CLK and CLK# – – 50 mV VOS[7] LVDS offset output voltage VDD = 3.3 V or 2.5 V, RTERM = 100 between CLK and CLK# 1.125 – 1.375 V VOS Change in VOS between comple- VDD = 3.3 V or 2.5 V, mentary output states RTERM = 100 between CLK and CLK# – – 50 mV IOZ Output leakage current Three-state output, unterminated, measured on one pin while floating the other pin, OE = VSS –35 – 35 A VIH Input high voltage, OE pin – 0.7 × VDD – – V VIL Input low voltage, OE pin – – – 0.3 × VDD V IIH Input high current, OE pin OE = VDD – – 115 µA IIL Input low current, OE pin OE = VSS –50 – – µA CIN Input capacitance, OE pin – – 15 – pF CINX Pin capacitance, XIN & XOUT – – 4.5 – pF Notes 3. Outputs are terminated with 100 between CLK and CLK#. Refer to Figure 8 on page 8. 4. IDD includes ~4 mA of current that is dissipated externally in the output termination resistor. 5. Not 100% tested, guaranteed by design and characterization. 6. Refer to Figure 2 on page 7. 7. Refer to Figure 3 on page 7. Document Number: 001-42886 Rev. *H Page 5 of 13 CY2XL11 AC Electrical Characteristics Parameter [8] Description Min Typ Max Unit – – 100 – MHz Output rise or fall time 20% to 80% of full output swing – 0.5 1.0 ns RMS phase jitter (random) FOUT = 100 MHz, (637 kHz–10 MHz) – 0.53 – ps TDC[11] Duty cycle Measured at zero crossing point 45 – 55 % TOHZ[12] Output disable time Time from falling edge on OE to stopped outputs (Asynchronous) – – 100 ns TOE[12] Output enable time Time from rising edge on OE to outputs at a valid frequency (Asynchronous) – – 120 ns TLOCK Startup time Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) – – 5 ms Min Max Unit FOUT Output frequency TR, TF[9] TJitter()[10] Test Conditions Crystal Characteristics Parameter Description Mode of oscillation Fundamental – F Frequency 25 25 MHz ESR Equivalent series resistance – 50 CS Shunt capacitance – 7 pF Notes 8. Outputs are terminated with 100 between CLK and CLK#. Refer to Figure 8 on page 8. 9. Refer to Figure 4 on page 7. 10. Refer to Figure 7 on page 8. 11. Refer to Figure 5 on page 7. 12. Refer to Figure 6 on page 7. Document Number: 001-42886 Rev. *H Page 6 of 13 CY2XL11 Switching Waveforms Figure 2. Output Voltage Swing CLK# VOD1 VOD2 CLK VOD = VOD1 - VOD2 Figure 3. Output Offset Voltage CLK 50 V OS 50 CLK# Figure 4. Output Rise or Fall Time CLK# CLK 80% 80% 20% 20% TR TF Figure 5. Duty Cycle Timing CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Figure 6. Output Enable and Disable Timing OE VIL TOHZ VIH TOE CLK High Impedance CLK# Document Number: 001-42886 Rev. *H Page 7 of 13 CY2XL11 Switching Waveforms (continued) Figure 7. RMS Phase Jitter Phase noise Noise Power Phase noise mark Offset Frequency f1 RMS Jitter = f2 Area Under the Masked Phase Noise Plot Termination Circuits Figure 8. LVDS Termination CLK 100 CLK# Document Number: 001-42886 Rev. *H Page 8 of 13 CY2XL11 Ordering Information Part Number Package Description Product Flow CY2XL11ZXC 8-pin TSSOP Commercial, 0 °C to 70 °C CY2XL11ZXCT 8-pin TSSOP – Tape and Reel Commercial, 0 °C to 70 °C CY2XL11ZXI 8-pin TSSOP Industrial, –40 °C to +85 °C CY2XL11ZXIT 8-pin TSSOP – Tape and Reel Industrial, –40 °C to +85 °C Ordering Code Definitions CY 2X L11 Z X X X X = blank or T blank = Tube; T = Tape and Reel Temperature Range: C = Commercial Pb-free Package Type: Z = 8-pin TSSOP Part Identifier Family Company ID: CY = Cypress Document Number: 001-42886 Rev. *H Page 9 of 13 CY2XL11 Package Drawing and Dimensions Figure 9. 8-pin TSSOP (4.40 mm Body) Package Outline, 51-85093 51-85093 *E Document Number: 001-42886 Rev. *H Page 10 of 13 CY2XL11 Acronyms Acronym Document Conventions Description Units of Measures CLKOUT Clock Output CMOS Complementary Metal Oxide Semiconductor °C degree Celsius DPM Die Pick Map kHz kilohertz EPROM Erasable Programmable Read Only Memory k kilohm LVDS Low-Voltage Differential Signaling MHz megahertz NTSC National Television System Committee M megaohm OE Output Enable µA microampere PAL Phase Alternate Line PD Power Down PLL Phase Locked Loop TTL Transistor-Transistor Logic Document Number: 001-42886 Rev. *H Symbol Unit of Measure µs microsecond µV microvolt µVrms microvolts root-mean-square mA milliampere mm millimeter ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt ohm ppm parts per million v volt Page 11 of 13 CY2XL11 Document History Page Document Title: CY2XL11, 100 MHz LVDS Clock Generator Document Number: 001- 42886 Rev. ECN No. Submission Date Orig. of Change ** 2117527 See ECN WWZ / KVM / AESA New data sheet *A 2669117 03/05/2009 KVM / AESA Changed Data Sheet Status to Final Changed crystal and output frequency Removed MSL spec Changed IIL value from -20 uA to -50 uA Changed IIH value from 20 uA to 115 uA Changed phase jitter value from 1 to 0.53 ps Changed junction temp from 125C to 135C Changed IDD from 150 mA to 120 mA Rise / fall time changed to 350 ps to 500ps *B 2700242 04/30/2009 KVM / PYRS Typo correction Reformatted AC and DC tables Added IDD spec for 2.5V Added CINX and TLOCK specs Changed CIN from 7pF to 15pF *C 2718433 06/12/2009 WWZ / HMT No change. Submit to ECN for product launch. *D 2764787 09/18/2009 KVM Add clause to IOZ Test Conditions Change VOD limits from 250/450 mV to 247/454 mV Add max limit for TR, TF: 1.0 ns Change TOE max from 100 ns to 120 ns Change TLOCK max from 10 ms to 5 ms *E 3067416 10/20/20 BASH Added the industrial part in Ordering Information table. Added Ordering Code Definition. Description of Change Updated package diagram. Added Acronyms and Units of Measures. *F 3199831 03/18/11 CXQ No change. Sunset review spec. *G 4334627 04/06/2014 CINM Updated Package Drawing and Dimensions: spec 51-85093 – Changed revision from *C to *D. Updated in new template. Completing Sunset Review. *H 4582584 11/07/2014 CINM Added related documentation hyperlink in page 1. Updated the part number CY2XL11ZXI(T) to CY2XL11ZXIT, in Ordering Information. Updated Package Drawing and Dimensions from 51-85093 *D to 51-85093 *E. Document Number: 001-42886 Rev. *H Page 12 of 13 CY2XL11 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/psoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-42886 Rev. *H Revised November 28, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 13 of 13