ONSEMI ADP3193A

8-Bit, Programmable, 2- to 3-Phase,
Synchronous Buck Controller
ADP3193A
FEATURES
The ADP3193A1 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 8-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.5 V and 1.6 V.
This device uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2- or
3-phase operation, allowing for the construction of up to three
complementary buck switching stages.
The ADP3193A also includes programmable no load offset and
slope functions to adjust the output voltage as a function of the
load current, optimally positioning it for a system transient. The
ADP3193A also provides accurate and reliable short-circuit
protection, adjustable current limiting, and delayed power-good
output that accommodates on-the-fly output voltage changes
requested by the CPU.
1
10
OSCILLATOR
UVLO
SHUTDOWN
+
GND 14
CMP
EN
+
1
DAC
+150mV
PWRGD
CURRENT BALANCING
CIRCUIT
–
850mV
–
+
CSREF
+
DAC
–350mV
–
+
CMP
–
RESET
2-/3-PHASE
DRIVER LOGIC
+
CMP
–
DELAY
2
CURRENT
MEASUREMENT
AND LIMIT
7
15
OD
22
PWM1
21
PWM2
20
PWM3
RESET
CROWBAR
ILIMIT 8
DELAY
–
SET EN
RESET
CURRENT
LIMIT
+
–
19
SW1
18
SW2
17
SW3
13
CSCOMP
11
CSREF
12
CSSUM
4
FB
6
SS
IREF 16
COMP
5
PRECISION
REFERENCE
FBRTN
3
BOOT
VOLTAGE
AND
SOFT START
CONTROL
VC DAC
VIDSEL 32
ADP3193A
24
25
26
27
28
29
30
31
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
06652-001
GENERAL DESCRIPTION
9
SHUNT
REGULATOR
+
Desktop PC power supplies for
Next generation Intel® processors
VRM modules
RT RAMPADJ
23
+
–
APPLICATIONS
VCC
–
Selectable 2- or 3-phase operation at up to 1 MHz per phase
±7.7 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external high
power drivers
Fast enhanced PWM (FEPWM) flex mode for excellent load
transient performance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.5 V to 1.6 V output supports both
VR10.x and VR11 specifications
Programmable short-circuit protection with programmable
latch-off delay
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
The ADP3193A has a built-in shunt regulator that allows the
part to be connected to the 12 V system supply through a series
resistor.
The ADP3193A is specified over the extended commercial
temperature range of 0°C to 85°C and is available in a
32-lead LFCSP.
Protected by U.S. Patent Number 6,683,441; other patents pending.
©2008 SCILLC. All rights reserved.
February 2008 – Rev. 1
Publication Order Number:
ADP3193A/D
ADP3193A
TABLE OF CONTENTS
Features...............................................................................................1
Dynamic VID ..............................................................................12
Applications .......................................................................................1
Power-Good Monitoring ...........................................................12
General Description..........................................................................1
Output Crowbar..........................................................................12
Functional Block Diagram...............................................................1
Output Enable and UVLO.........................................................13
Revision History................................................................................2
Application Information ................................................................18
Specifications .....................................................................................3
Setting the Clock Frequency .....................................................18
Absolute Maximum Ratings ............................................................5
Soft Start Delay Time .................................................................18
ESD Caution ..................................................................................5
Current-Limit Latch-Off Delay Times.....................................18
Pin Configuration and Function Descriptions .............................6
Inductor Selection.......................................................................18
Typical Performance Characteristics..............................................7
Current Sense Amplifier ............................................................19
Test Circuits .......................................................................................8
Inductor DCR Temperature Correction..................................20
Theory of Operation.........................................................................9
Output Offset...............................................................................20
Start-Up Sequence ........................................................................9
COUT Selection..............................................................................21
Phase Detection Sequence ...........................................................9
Power MOSFETs .........................................................................22
Master Clock Frequency ............................................................10
Ramp Resistor Selection ............................................................23
Output Voltage Differential Sensing ........................................10
COMP Pin Ramp ........................................................................23
Output Current Sensing .............................................................10
Current-Limit Setpoint ..............................................................23
Current Control Mode and Thermal Balance.........................10
Feedback Loop Compensation Design ....................................24
Voltage Control Mode ................................................................10
CIN Selection and Input Current di/dt Reduction ..................25
Current Reference .......................................................................11
Shunt Resistor Design ................................................................25
Fast Enhanced PWM Mode.......................................................11
Tuning Procedure for ADP3193A ............................................26
Delay Timer .................................................................................11
Layout and Component Placement..........................................27
Soft Start .......................................................................................11
Outline Dimensions........................................................................29
Current-Limit, Short-Circuit, and Latch-Off Protection ......11
Ordering Guide ...........................................................................29
REVISION HISTORY
02/08—Rev 1: Conversion to ON Semiconductor
05/07—Revision 0: Initial Version
Rev. 1 | Page 2 of 29 | www.onsemi.com
ADP3193A
SPECIFICATIONS
VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1
Table 1.
Parameter
REFERENCE CURRENT
Reference Bias Voltage
Reference Bias Current
ERROR AMPLIFIER
Output Voltage Range2
Accuracy
Symbol
Conditions
Min
Typ
Max
Unit
VIREF
IIREF
RIREF = 100 kΩ
14.25
1.5
15
15.75
V
μA
4.4
+7.7
V
mV
1.108
+1
16.5
200
V
LSB
μA
μA
μA
MHz
V/μs
ms
0.4
V
V
μA
ns
μs
4
293
MHz
kHz
kHz
kHz
V
mV
μA
VCOMP
VFB
VFB(BOOT)
Differential Nonlinearity
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
Boot Voltage Hold Time
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current
VID Transition Delay Time2
No CPU Detection Turn-Off Delay Time2
OSCILLATOR
Frequency Range2
Frequency Variation
Output Voltage
RAMPADJ Output Voltage
RAMPADJ Input Current Range
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common-Mode Range
Output Voltage Range
Output Current
Current Limit Latch-Off Delay Time
CURRENT BALANCE AMPLIFIER
Common-Mode Range
Input Resistance
Input Current
Input Current Matching
IFB
IFBRTN
ICOMP
GBW(ERR)
tBOOT
VIL(VID)
VIH(VID)
IIN(VID)
Relative to nominal DAC output, referenced
to FBRTN (see Figure 4)
In startup
IFB = IIREF
VRT
VRAMPADJ
IRAMPADJ
VOS(CSA)
IBIAS(CSSUM)
GBW(CSA)
1.092
−1
13.5
FB forced to VOUT − 3%
COMP = FB
COMP = FB
CDELAY = 10 nF
VID(x), VIDSEL
VID(x), VIDSEL
1.1
15
65
500
20
25
2
0.8
−1
VID code change to FB change
VID code change to PWM going low
fOSC
fPHASE
0
−7.7
TA = 25°C, RT = 210 kΩ, 3-phase
TA = 25°C, RT = 100 kΩ, 3-phase
TA = 25°C, RT = 40 kΩ, 3-phase
RT = 243 kΩ to GND
RAMPADJ − FB
CSSUM − CSREF (see Figure 4)
CSSUM = CSCOMP
CCSCOMP = 10 pF
CSSUM and CSREF
ICSCOMP
tOC(DELAY)
CDELAY = 10 nF
VSW(x)CM
RSW(x)
ISW(x)
ΔISW(x)
SW(x) = 0 V
SW(x) = 0 V
SW(x) = 0 V
Rev. 1 | Page 3 of 29 | www.onsemi.com
400
5
0.25
240
1.9
−50
1
260
530
1000
2.0
−1.0
−10
2.1
+50
50
+1.0
+10
10
10
0
0.05
3.5
3.5
500
8
−600
10
8
−4
17
12
+200
26
20
+4
mV
nA
MHz
V/μs
V
V
μA
ms
mV
kΩ
μA
%
ADP3193A
Parameter
CURRENT LIMIT COMPARATOR
ILIMIT Bias Current
ILIMIT Voltage
Maximum Output Voltage
Current-Limit Threshold Voltage
Current-Limit Setting Ratio
DELAY TIMER
Normal Mode Output Current
Output Current in Current Limit
Threshold Voltage
SOFT START
Output Current
ENABLE INPUT
Threshold Voltage
Hysteresis
Input Current
Delay Time
OD OUTPUT
2
Conditions
Min
Typ
Max
Unit
IILIMIT
VILIMIT
IILIMIT = 2/3 × IIREF
RILIMIT = 121 kΩ (VILIMIT = (IILIMIT × RILIMIT))
10
1.21
11
1.33
VCL
VCSREF − VCSCOMP, RILIMIT = 121 kΩ
VCL/VILIMIT
9
1.09
3
80
100
82.6
125
μA
V
V
mV
mV/V
IDELAY
IDELAY(CL)
VDELAY(TH)
IDELAY = IIREF
IDELAY(CL) = 0.25 × IIREF
12
3.0
1.6
15
3.75
1.7
18
4.5
1.8
μA
μA
V
ISS
During startup, ISS = IIREF
12
15
18
μA
800
80
850
100
−1
2
900
125
mV
mV
μA
ms
160
500
mV
VTH(EN)
VHYS(EN)
IIN(EN)
tDELAY(EN)
Output Low Voltage
VOL(OD)
Output High Voltage
VOH(OD)
POWER-GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Power-Good Delay Time
During Soft Start2
VID Code Changing
VID Code Static
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
PWM OUTPUTS
Output Low Voltage
Output High Voltage
SUPPLY
VCC2
DC Supply Current
UVLO Turn-On Current
UVLO Threshold Voltage
UVLO Turn-Off Voltage
1
Symbol
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
EN > 950 mV, CDELAY = 10 nF
Relative to nominal DAC output
Relative to nominal DAC output
IPWRGD(SINK) = −4 mA
4
5
−400
100
−350
150
150
CDELAY = 10 nF
100
VCROWBAR
tCROWBAR
Relative to nominal DAC output
Relative to FBRTN
Overvoltage to PWM going low
100
320
100
VOL(PWM)
VOH(PWM)
VCC
IVCC
IPWM(SINK) = −400 μA
IPWM(SOURCE) = 400 μA
VSYSTEM = 12 V, RSHUNT = 340 Ω (see Figure 4)
2
250
200
150
375
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Guaranteed by design or bench characterization, not tested in production.
Rev. 1 | Page 4 of 29 | www.onsemi.com
mV
mV
mV
200
430
ms
μs
ns
mV
mV
μs
ns
160
5
500
4.0
mV
V
4.65
5
5.55
25
11
V
mA
mA
V
V
VSYSTEM = 13.2 V, RSHUNT = 340 Ω
VCC rising
VCC falling
−300
200
300
250
400
6.5
VUVLO
V
9
4.1
ADP3193A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC
FBRTN
PWM1 to PWM3, RAMPADJ
SW1 to SW3
<200 ns
All Other Inputs and Outputs
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA)
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to VCC + 0.3 V
−5 V to +25 V
−10 V to +25 V
−0.3 V to VCC + 0.3 V
−65°C to +150°C
0°C to 85°C
125°C
32.6°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages
are referenced to GND.
ESD CAUTION
300°C
260°C
Rev. 1 | Page 5 of 29 | www.onsemi.com
ADP3193A
32
31
30
29
28
27
26
25
VIDSEL
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
ADP3193A
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VID7
VCC
PWM1
PWM2
PWM3
SW1
SW2
SW3
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN
ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND.
06652-005
RT
RAMPADJ
CSREF
CSSUM
CSCOMP
GND
OD
IREF
9
10
11
12
13
14
15
16
EN
PWRGD
FBRTN
FB
COMP
SS
DELAY
ILIMIT
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
EN
PWRGD
FBRTN
FB
5
6
7
COMP
SS
DELAY
8
9
ILIMIT
RT
10
11
RAMPADJ
CSREF
12
CSSUM
13
CSCOMP
14
15
GND
OD
16
17 to 19
IREF
SW3 to SW1
20 to 22
PWM3 to PWM1
23
VCC
24 to 31
VID7 to VID0
32
VIDSEL
Description
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range.
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin
and the output voltage sets the no load offset point.
Error Amplifier Output and Compensation Point.
Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start ramp-up time.
Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latch-off
delay time, boot voltage hold time, EN delay time, and PWRGD delay time.
Current-Limit Set Point. An external resistor from this pin to GND sets the current-limit threshold of the converter.
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp.
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier
and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors.
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents
to measure the total output current.
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the
current sense amplifier and the positioning loop response time.
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO
threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.
Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IDELAY, ISS, and IILIMIT.
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be
left open.
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3120A.
Connecting PWM3 output to VCC causes that phase to turn off, allowing the ADP3193A to operate as a 2- or 3-phase
controller.
Supply Voltage. A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal
shunt regulator maintains VCC = 5 V.
Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open. When
in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V (see Table 4).
VID DAC Selection Pin. The logic state of this pin determines whether the internal VID DAC decodes VID0 to VID7 as
extended VR10 or VR11 inputs.
Rev. 1 | Page 6 of 29 | www.onsemi.com
ADP3193A
TYPICAL PERFORMANCE CHARACTERISTICS
6000
4000
MASTER CLOCK
3000
2000
1000
0
13
27
39
50
68
82
130 210 248 270 430 742 850
RT (kΩ)
06652-017
FREQUENCY (kHz)
5000
Figure 3. Master Clock Frequency vs. RT
Rev. 1 | Page 7 of 29 | www.onsemi.com
ADP3193A
TEST CIRCUITS
8-BIT CODE
ADP3193A
12V
32
10nF
ADP3193A
VID7
VCC
PWM1
PWM2
PWM3
SW1
SW2
SW3
+
1μF
250kΩ
VCC
23
COMP
100nF
5
10kΩ
FB
4
100kΩ
CSREF
11
1V
06652-002
100nF
Figure 4. Closed-Loop Output Voltage Accuracy
ADP3193A
680Ω
VCC
23
CSCOMP
13
39kΩ
100nF
CSSUM
12
1kΩ
CSREF
11
1V
GND
14
VOS =
14
Figure 6. Positioning Voltage
12V
680Ω
+
CSCOMP – 1V
40
Figure 5. Current Sense Amplifier Offset Voltage (VOS)
Rev. 1 | Page 8 of 29 | www.onsemi.com
VID
DAC
GND
20kΩ
06652-003
10nF
EN
PWRGD
FBRTN
FB
COMP
SS
DELAY
ILIMIT
680Ω
680Ω
06652-004
1kΩ
VIDSEL
VID0
VID1
VID2
VID3
VID4
VID5
VID6
1.25V
680Ω
680Ω
RT
RAMPADJ
CSREF
CSSUM
CSCOMP
GND
OD
IREF
1
12V
ADP3193A
THEORY OF OPERATION
5V
SUPPLY
VTT I/O
(ADP3193A EN)
•
•
•
•
•
•
•
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
Minimizing thermal switching losses by using lower
frequency operation
Tight load line regulation and accuracy
High current output due to 3-phase operation
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
Flexibility in design by allowing optimization for either low
cost or high performance
START-UP SEQUENCE
The ADP3193A follows the VR11 start-up sequence shown in
Figure 7. After both the EN and UVLO conditions are met,
the DELAY pin goes through one cycle (TD1). The first three
clock cycles of TD2 are blanked from the PWM outputs and
used for phase detection, as explained in the Phase Detection
Sequence section. Then, the soft start ramp is enabled (TD2),
and the output increases to the boot voltage of 1.1 V. The boot
hold time is determined by the DELAY pin as it goes through a
second cycle (TD3). During TD3, the processor VID pins settle
to the required VID code. When TD3 is over, the ADP3193A
soft starts either up or down to the final VID voltage (TD4).
After TD4 has been completed and the PWRGD masking time
(equal to VID on-the-fly masking) is completed, a third ramp
on the DELAY pin sets the PWRGD blanking (TD5).
VDELAY(TH)
(1.7V)
VBOOT
(1.1V)
1V
SS
VVID
TD3
VCC_CORE
•
0.85V
DELAY
The multimode control of the ADP3193A ensures a stable,
high performance topology for the following:
•
UVLO
THRESHOLD
VBOOT
(1.1V)
TD1
VVID
TD4
TD2
VR READY
(ADP3193A PWRGD)
50μs
CPU
VID INPUTS
VID INVALID
TD5
VID VALID
06652-006
The ADP3193A combines a multimode, fixed-frequency PWM
control with multiphase logic outputs for use in 2- and 3-phase
synchronous buck CPU core supply power converters. The internal
VID DAC is designed to interface with the Intel 8-bit VRD/VRM 11
and 7-bit VRD/VRM 10.x CPUs. Multiphase operation is important for producing the high currents and low voltages demanded by
today’s microprocessors. Handling the high currents in a singlephase converter increases thermal demands on the components
in the system, such as the inductors and MOSFETs.
Figure 7. System Start-Up Sequence
PHASE DETECTION SEQUENCE
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3193A operates
as a 3-phase PWM controller. Connecting the PWM3 pin to
VCC programs 2-phase operation.
Prior to soft start, while EN is low, the PWM3 pin sinks approximately 100 μA. An internal comparator checks the voltage on
PWM3 and compares it with a threshold of 3 V. If the pin is tied
to VCC, it is above the threshold. Otherwise, an internal
current sink pulls the pin to GND, which is below the
threshold. PWM1 and PWM2 are low during the phase detection
interval that occurs during the first three clock cycles of TD2. After
this time, if PWM3 is not pulled to VCC, the 100 μA current
sink is removed, and it functions as normal PWM output. If
PWM3 is pulled to VCC, the 100 μA current source is removed,
and it is put into a high impedance state.
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3120A. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. In addition, more than one output can be on at
the same time to allow overlapping phases.
Rev. 1 | Page 9 of 29 | www.onsemi.com
ADP3193A
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3193A is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 3. To determine the frequency per
phase, the clock is divided by the number of phases in use. If all
phases are in use, divide by 3. If PWM3 is tied to VCC, divide
the master clock by 2 for the frequency of the remaining phases.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3193A includes differential sensing, high accuracy
VID DAC and reference, and a low offset error amplifier. This
maintains a worst-case specification of ±7.7 mV differential
sensing error over its full operating output voltage and temperature
range. The output voltage is sensed between the FB pin and the
FBRTN pin. FB should be connected through a resistor to the
regulation point, usually the remote sensing pin of the microprocessor. FBRTN should be connected directly to the remote
sensing ground point. The internal VID DAC and precision
reference are referenced to FBRTN, which has a minimal current
of 65 μA to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
OUTPUT CURRENT SENSING
To provide the best accuracy for sensing current, the CSA has a
low offset input voltage and the sensing gain is set by the external
resistor.
CURRENT CONTROL MODE AND
THERMAL BALANCE
The ADP3193A has individual inputs (SW1 to SW3) for each
phase that are used to monitor the current. This information is
combined with an internal ramp to create a current-balancing
feedback system that has been optimized for initial current balance
accuracy and dynamic thermal balancing during operation. This
current balance information is independent of the average output
current information used for positioning, as described in the
Output Current Sensing section.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply voltage
for feedforward control for changes in the supply. A resistor
connected from the power input voltage to the RAMPADJ pin
determines the slope of the internal PWM ramp. External resistors
can be placed in series with individual phases to create an intentional current imbalance, such as when one phase has better
cooling and can support higher currents. Resistors RSW1 through
RSW3 (see Figure 10) can be used for adjusting thermal balance
in this 3-phase example. It is best to have the ability to add these
resistors during the initial design; therefore, ensure that placeholders are provided in the layout.
The ADP3193A provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current-limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sensing element, such as the low-side MOSFET.
Depending on the objectives of the system, this amplifier can be
configured in several ways:
To increase the current in any given phase, enlarge RSW for that
phase (make RSW = 0 for the hottest phase, and do not change it
during balancing). Increasing RSW to only 500 Ω results in a
substantial increase in phase current. Increase each RSW value
by small amounts to achieve balance, starting with the coolest
phase first.
•
VOLTAGE CONTROL MODE
•
•
Output inductor DCR sensing without a thermistor for
lowest cost.
Output inductor DCR sensing with a thermistor for
improved accuracy in tracking inductor temperature.
Sensing resistor for highest accuracy measurements.
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element, such as the switch node side of the output
inductors,
to the inverting input CSSUM. The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifier, and a filter
capacitor is placed in parallel with this resistor. The gain of the
amplifier is programmable by adjusting the feedback resistor.
The difference between CSREF and CSCOMP is also used as a
differential input for the current-limit comparator.
A high gain, high bandwidth voltage mode error amplifier is used
for the voltage mode control loop. The control input voltage to
the positive input is set via the VID logic according to the voltages
listed in Table 4.
This voltage is also offset by the droop voltage for active
positioning of the output voltage as a function of current,
commonly known as active voltage positioning. The output
of the amplifier is the COMP pin, which sets the termination
voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
Resistor RB and is used for sensing and controlling the output
voltage at this point. A current source (equal to IREF) from the
FB pin flowing through RB is used for setting the no load offset
voltage from the VID voltage. The no load voltage is negative with
Rev. 1 | Page 10 of 29 | www.onsemi.com
ADP3193A
respect to the VID DAC. The main loop compensation is incorporated into the feedback network between FB and COMP pins.
the inrush current during startup. The soft start time depends
on the value of the boot voltage and CSS.
CURRENT REFERENCE
When the SS voltage is within 100 mV of the boot voltage, the
boot voltage delay time (TD3 in Figure 7) starts. The end of the
boot voltage delay time signals the beginning of the second soft
start time (TD4 in Figure 7). The SS voltage changes from the
boot voltage to the programmed VID DAC voltage (either higher
or lower) using the SS amplifier with the output current equal
to IREF. The voltage of the FB pin follows the ramping voltage
of the SS pin, limiting the inrush current during the transition
from the boot voltage to the final DAC voltage. The second soft
start time depends on the boot voltage, the programmed VID
DAC voltage, and the CSS.
The IREF pin is used to set an internal current reference. This
reference current sets IFB, IDELAY, ISS, and ILIMIT. A resistor to
ground programs the current based on the 1.5 V output.
IREF =
1.5 V
R IREF
Typically, RIREF is set to 100 kΩ to program IREF = 15 μA.
Therefore,
IFB = IREF = 15 μA
IDELAY = IREF = 15 μA
If EN is taken low or if VCC drops below UVLO, DELAY and
SS are reset to ground to be ready for another soft start cycle.
Figure 8 shows typical start-up waveforms for the ADP3193A.
ISS = IREF = 15 μA
ILIMIT = 2/3 (IREF) = 10 μA
FAST ENHANCED PWM MODE
Fast enhanced PWM mode is intended to improve the transient
response of the ADP3193A to a load step-up. In previous generations of controllers, when a load step-up occurred, the controller
could only respond to the load change after the PWM signal
was turned on. Enhanced PWM mode allows the controller to
immediately respond when a load step-up occurs. This allows the
phases to respond more quickly when a load increase takes place.
1
2
3
The delay times for the start-up timing sequence are set with
a capacitor from the DELAY pin to ground. In UVLO or when
EN is logic low, the DELAY pin is held at ground. After the
UVLO and EN signals are asserted, the first delay time (TD1 in
Figure 7) is initiated. A current flows out of the DELAY pin to
charge CDLY. This current is equal to IREF, which is normally
15 μA. A comparator monitors the DELAY voltage with a
threshold of 1.7 V. The delay time is therefore set by the IREF
current charging a capacitor from 0 V to 1.7 V. This DELAY pin
is used for multiple delay timings (TD1, TD3, and TD5) during
the start-up sequence. In addition, DELAY is used for timing
the current-limit latch-off, as explained in the Current-Limit,
Short-Circuit, and Latch-Off Protection section.
SOFT START
The soft start times for the output voltage are set with a capacitor
from the SS pin to ground. After TD1 and the phase detection
cycle have been completed, the SS time (TD2 in Figure 7) starts.
The SS pin is disconnected from GND, and the capacitor is charged
up to the 1.1 V boot voltage by the SS amplifier, which has an
output current equal to IREF (normally 15 μA). The voltage at
the FB pin follows the ramping voltage on the SS pin, limiting
4
CH1 1V
CH3 1V
CH2 1V
CH4 10V
M 1ms
T 40.4%
A CH1
700mV
06652-007
DELAY TIMER
Figure 8. Typical Start-Up Waveforms
(Channel 1: CSREF, Channel 2: DELAY,
Channel 3: SS, Channel 4: Phase 1 Switch Node)
CURRENT-LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3193A compares a programmable current-limit
setpoint to the voltage from the output of the current sense
amplifier. The level of current limit is set with the resistor from
the ILIMIT pin to ground. During operation, the current from
ILIMIT is equal to 2/3 of IREF, resulting in 10 μA normally. This
current through the external resistor sets the ILIMIT voltage,
which is internally scaled to provide a current limit threshold of
82.6 mV/V. If the difference in voltage between CSREF and
CSCOMP rises above the current-limit threshold, the internal
current-limit amplifier controls the internal COMP voltage to
maintain the average output current at the limit.
If the limit is reached and TD5 in Figure 7 has completed, a
latch-off delay time starts, and the controller shuts down if the
fault is not removed. The current-limit delay time shares the
Rev. 1 | Page 11 of 29 | www.onsemi.com
ADP3193A
DELAY pin timing capacitor with the start-up sequence timing.
However, during current limit, the DELAY pin current is reduced
to IREF/4. A comparator monitors the DELAY voltage and shuts
off the controller when the voltage reaches 1.7 V. Therefore,
the current-limit latch-off delay time is set by the current of
IREF/4 charging the delay capacitor from 0 V to 1.7 V. This delay
is four times longer than the delay time during the start-up
sequence.
The current-limit delay time starts only after the TD5 is
complete. If there is a current limit during startup, the
ADP3193A goes through TD1 to TD5, and then starts the
latch-off time. Because the controller continues to cycle the
phases during the latch-off delay time, the controller returns to
normal operation and the DELAY capacitor is reset to GND if
the short is removed before the 1.7 V threshold is reached.
The latch-off function can be reset by either removing and
reapplying the supply voltage to the ADP3193A or by briefly
toggling the EN pin low. To disable the short-circuit latch-off
function, an external resistor should be placed in parallel with
CDLY. This prevents the DELAY capacitor from charging up to
the 1.7 V threshold. The addition of this resistor causes a slight
increase in the delay times.
During startup, when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage
to the PWM comparators to 1.5 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry. An inherent per-phase current limit protects individual
phases if one or more phases stop functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage. Typical overcurrent latch-off waveforms are
shown in Figure 9.
1
DYNAMIC VID
The ADP3193A can dynamically change the VID inputs while
the controller is running. This allows the output voltage to
change while the supply is running and supplying current to the
load. This is commonly referred to as VID on-the-fly (OTF). A
VID OTF can occur under light or heavy load conditions. The
processor signals the controller by changing the VID inputs in
multiple steps from the start code to the finish code. This
change can be positive or negative.
When a VID input changes state, the ADP3193A detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the eight
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and crowbar blanking functions for a
minimum of 100 μs to prevent a false PWRGD or crowbar
event. Each VID change resets the internal timer.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output whose
high level, when connected to a pull-up resistor, indicates that
the output voltage is within the specified nominal limits, which
are based on the VID voltage setting. PWRGD goes low if the
output voltage is outside of this specified range, if the VID DAC
inputs are in no CPU mode, or if the EN pin is pulled low. PWRGD
is blanked during a VID OTF event for a period of 200 μs to
prevent false signals during the time the output is changing.
The PWRGD circuitry also incorporates an initial turn-on
delay time (TD5) based on the DELAY timer. Prior to the
SS voltage reaching the programmed VID DAC voltage and the
PWRGD masking time finishing, the PWRGD pin is held low.
When the SS pin is within 100 mV of the programmed DAC
voltage, the capacitor on the DELAY pin begins to charge.
A comparator monitors the DELAY voltage and enables
PWRGD when the voltage reaches 1.7 V. The PWRGD delay
time is, therefore, set by a current of IREF charging a capacitor
from 0 V to 1.7 V.
OUTPUT CROWBAR
To protect the load and output components of the supply, the
PWM outputs are driven low, which turns on the low-side
MOSFETs when the output voltage exceeds the upper crowbar
threshold. This crowbar action stops when the output voltage
falls below the release threshold of approximately 300 mV.
2
4
CH1 1V
CH3 2V
CH2 1V
CH4 10V
M 2ms
T 61.8%
A CH1
680mV
Figure 9. Overcurrent Latch-Off Waveforms
(Channel 1: CSREF, Channel 2: DELAY,
Channel 3: COMP, Channel 4: Phase 1 Switch Node)
06652-008
3
Turning on the low-side MOSFETs pulls down the output as
the reverse current builds up in the inductors. If the output
overvoltage is due to a short in the high-side MOSFET, this
action current limits the input supply or blows its fuse,
protecting the microprocessor from being destroyed.
Rev. 1 | Page 12 of 29 | www.onsemi.com
ADP3193A
OUTPUT ENABLE AND UVLO
In the application circuit (see Figure 10), the OD pin should be
connected to the OD inputs of the ADP3120A drivers. Grounding
OD disables the drivers such that both DRVH and DRVL are
grounded. This feature is important in preventing the discharge
of the output capacitors when the controller is shut off. If the
driver outputs are not disabled, a negative voltage can be generated
during output due to the high current discharge of the output
capacitors through the inductors.
For the ADP3193A to begin switching, the input supply (VCC)
to the controller must be higher than the UVLO threshold and
the EN pin must be higher than its 0.85 V threshold. This
initiates a system start-up sequence. If either UVLO or EN is
less than its respective threshold, the ADP3193A is disabled.
This holds the PWM outputs at ground, shorts the DELAY
capacitor to ground, and forces PWRGD and OD signals low.
Table 4. VR11 and VR10.x VID Codes for the ADP3193A
Output
Off
Off
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
VID7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VR11 DAC Codes: VIDSEL = High
VID5 VID4 VID3 VID2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 1 | Page 13 of 29 | www.onsemi.com
VR10.x DAC Codes: VIDSEL = Low
VID3 VID2 VID1 VID0 VID5
N/A
N/A
1
0
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
VID6
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
ADP3193A
Output
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
Off
Off
Off
Off
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
VID7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VR11 DAC Codes: VIDSEL = High
VID5 VID4 VID3 VID2
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
N/A
N/A
N/A
N/A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 1 | Page 14 of 29 | www.onsemi.com
VR10.x DAC Codes: VIDSEL = Low
VID3 VID2 VID1 VID0 VID5
0
1
0
1
1
0
1
0
1
1
0
1
1
0
0
0
1
1
0
0
0
1
1
0
1
0
1
1
0
1
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
VID6
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
ADP3193A
Output
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
0.82500
0.81875
0.81250
0.80625
0.80000
0.79375
0.78750
0.78125
0.77500
0.76875
0.76250
0.75625
0.75000
0.74375
0.73750
0.73125
0.72500
0.71875
0.71250
0.70625
0.70000
0.69375
0.68750
0.68125
0.67500
0.66875
0.66250
0.65625
0.65000
0.64375
0.63750
0.63125
VID7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VR11 DAC Codes: VIDSEL = High
VID5 VID4 VID3 VID2
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 1 | Page 15 of 29 | www.onsemi.com
VR10.x DAC Codes: VIDSEL = Low
VID3 VID2 VID1 VID0 VID5
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
1
0
0
0
1
1
0
0
0
1
1
0
1
0
1
1
0
1
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VID6
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
ADP3193A
Output
0.62500
0.61875
0.61250
0.60625
0.60000
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
0.55000
0.54375
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
Off
Off
VID7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
VR11 DAC Codes: VIDSEL = High
VID5 VID4 VID3 VID2
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
VID4
1
1
Rev. 1 | Page 16 of 29 | www.onsemi.com
VR10.x DAC Codes: VIDSEL = Low
VID3 VID2 VID1 VID0 VID5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
1
1
1
1
1
1
1
VID6
0
1
C8
1nF
Figure 10. Typical 3-Phase Application Circuit
Rev. 1 | Page 17 of 29 | www.onsemi.com
R3
1Ω
1.21kΩ
RB
560pF
CB
18nF
RLIM
100kΩ
1%
CSS
18nF
32
RT
+
12V
12V
680Ω
C2
FROM CPU
C7
1nF
CCS1
1nF
5% NPO
88.7kΩ
RCS2
158kΩ
1%
1%
RPH2
RPH3 158kΩ
RPH1
158kΩ
1%
RSW1*
RSW2*
RSW3*
RCS1
35.7kΩ
100kΩ CCS2
1nF
5% NPO
RIREF
IREF
VID7
VCC
PWM1
PWM2
PWM3
SW1
SW2
SW3
VID6
C4
1μF
680Ω
U1
ADP3193A
EN
PWRGD
FBRTN
FB
COMP
SS
DELAY
ILIMIT
RT
169kΩ
1%
1
VIDSEL
R2
178kΩ
1%
C3
100μF
(OPTIONAL)
C1
+ +
*FOR A DESCRIPTION OF OPTIONAL RSW RESISTORS, SEE THE THEORY OF OPERATION SECTION.
**CONNECT NEAR EACH INDUCTOR.
22.1kΩ
RA
CDLY
220pF
CA
CFB
15pF
POWER GOOD
C5
1nF
VTT I/O
1μF
1kΩ
VIN RTN
12V
VIN
C14
1μF
C10
1μF
C18
1μF
SW 7
PGND 6
C15
C13
18nF
SW 7
PGND 6
C19
C17
18nF
SW 7
PGND 6
4 VCC DRVL 5
3 OD
2 IN
1 BST DRVH 8
U4 10nF
ADP3120A
R6
2.2Ω
4 VCC DRVL 5
3 OD
2 IN
1 BST DRVH 8
U3 10nF
ADP3120A
R5
2.2Ω
4 VCC DRVL 5
3 OD
2 IN
1 BST DRVH 8
C11
U2
10nF
ADP3120A
Q1
NTD40N03
Q11
NTD110N02
Q12
NTD110N02
Q9
NTD40N03
C20
4.7μF
Q8
NTD110N02
Q6
NTD40N03
L3
320nH/1.4mΩ
C16
4.7μF
10Ω**
RTH2
100kΩ, 5%
NTC
10Ω**
10Ω**
C25
+
C32
+
560μF/4V x 8
SANYO SEPC SERIES
L2
5mΩ EACH
320nH/1.4mΩ
Q2
NTD40N03
C12
4.7μF
Q10
NTD40N03
L4
320nH/1.4mΩ
Q7
NTD110N02
Q5
NTD40N03
Q3
NTD110N02
C9
18nF
Q4
NTD110N02
R4
2.2Ω
VSS(SENSE)
VCC(SENSE)
10μF × 26
MLCC IN
SOCKET
VCC(CORE) RTN
0.5V TO 1.6V
56A TDC, 65A PK
VCC(CORE)
06652-009
2700μF/16V/3.3A × 2
SANYO MV-WX SERIES
VID0
VID1
VID2
VID3
VID4
VID5
RAMPADJ
CSREF
CSSUM
CSCOMP
GND
OD
D2, 1N4148
D3, 1N4148
D4, 1N4148
L1
370nH
18A
ADP3193A
ADP3193A
APPLICATION INFORMATION
The design parameters for a typical Intel VRD 11 compliant
CPU application are as follows:
•
Input voltage (VIN) = 12 V
•
VID setting voltage (VVID) = 1.400 V
•
Duty cycle (D) = 0.117
•
Nominal output voltage at no load (VONL) = 1.381 V
•
Nominal output voltage at 65 A load (VOFL) = 1.316 V
•
Static output voltage drop based on a 1.0 mΩ load line (RO)
from no load to full load (VD) = VONL − VOFL =
1.381 V − 1.316 V = 65 mV
•
Maximum output current (IO) = 65 A
•
Maximum output current step (ΔIO) = 50 A
•
Maximum output current slew rate (SR) = 200 A/μs
•
Number of phases (n) = 3
•
Switching frequency per phase (fSW) = 330 kHz
specification for TD4 is 0 ns. This means that as long as the TD2
time requirement is met, TD4 is within the specification.
SETTING THE CLOCK FREQUENCY
In this example, 2 ms is chosen for all three delay times, which
meets Intel specifications. Solving for CDLY results in a value of
17.6 nF. The closest standard value for CDLY is 18 nF.
The ADP3193A uses a fixed-frequency control architecture.
The frequency is set by an external timing resistor (RT). The
clock frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses as
well as to the sizes of the inductors, the input capacitors, and
the output capacitors. With n = 3 for three phases, a clock
frequency of 990 kHz sets the switching frequency (fSW) of each
phase to 330 kHz, which represents a practical trade-off
between the switching losses and the sizes of the output filter
components. Figure 3 shows that to achieve a 990 kHz oscillator
frequency,
the correct value for RT is 169 kΩ (closest 1% resistor is 169 kΩ).
Alternatively, the value for RT can be calculated using
RT =
1
n × f SW × 6 pF
(1)
where 6 pF is the internal IC component values. For good initial
accuracy and frequency stability, a 1% resistor is recommended.
SOFT START DELAY TIME
The value of CSS sets the soft start time. The ramp is generated
with a 15 μA internal current source. The value for CSS can be
found using
C SS = 15 μA ×
TD2
V BOOT
(2)
where TD2 is the desired soft start time, and VBOOT is internally
set to 1.1 V.
Assuming a desired TD2 time of 1.4 ms, CSS is 19 nF. The closest
standard value for CSS is 18 nF. Although CSS also controls the time
delay for TD4 (determined by the final VID voltage), the minimum
CURRENT-LIMIT LATCH-OFF DELAY TIMES
The start-up and current-limit delay times are determined by
the capacitor connected to the DELAY pin. The first step is to
set CDLY for the TD1, TD3, and TD5 delay times (see Figure 7).
The DELAY ramp (IDELAY) is generated using a 15 μA internal
current source. The value for CDLY can be approximated using
C DLY = I DELAY ×
TD( x )
VDELAY (TH )
(3)
where:
TD(x) is the desired delay time for TD1, TD3, and TD5.
VDELAY(TH) is the DELAY threshold voltage and is given as 1.7 V.
When the ADP3193A surpasses the current limit, the internal
current source changes from 15 μA to 3.75 μA. As a result, the
latch-off delay time becomes four times longer than the start-up
delay time. Note that longer latch-off delay times can be achieved
by placing a resistor in parallel with CDLY.
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs. However, using smaller inductors allows
the converter to meet a specified peak-to-peak transient deviation
with less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
more output capacitance is required to meet the same peak-topeak transient deviation.
In any multiphase converter, a practical value for the peak-topeak inductor ripple current is less than 50% of the maximum
dc current in the same inductor. Equation 4 shows the relationship
between the inductance, oscillator frequency, and peak-to-peak
ripple current in the inductor.
IR =
VVID × (1 − D )
f SW × L
(4)
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
L≥
VVID × R O × (1 − (n × D ))
Rev. 1 | Page 18 of 29 | www.onsemi.com
f SW × V RIPPLE
(5)
ADP3193A
Solving Equation 5 for an output ripple voltage of 10 mV p-p yields
L≥
1.4 V × 1.0 mΩ × (1 − 0.35)
330 kHz × 10 mV
The following power inductor manufacturers can provide design
consultation and upon request deliver power inductors optimized
for high power applications.
= 276 nH
If the resulting ripple voltage is less than what is designed for,
the inductor can be made smaller until the ripple value is met.
This allows optimal transient response and minimum output
decoupling.
The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 320 nH inductor is a
good choice for a starting point, and it provides a calculated
ripple current of 11.7 A. The inductor should not saturate at the
peak current of 27.6 A, and it should be able to handle the sum
of the power dissipation caused by the average current of 21.7 A
in the winding and core loss.
Another important factor in the inductor design is the dc resistance
(DCR), which is used for measuring the phase currents. Too large
of a DCR causes excessive power losses, whereas too small of a
value leads to increased measurement error. A good rule is to
have the DCR (RL) be about 1× to 1½× the droop resistance (RO).
This example uses an inductor with a DCR of 1.4 mΩ.
Designing an Inductor
After the inductance and DCR are known, the next step is
either to design an inductor or to find a standard inductor that
best meets the overall design goals. It is also important to have
the inductance and DCR tolerance specified to control the
accuracy of the system. Reasonable tolerances that most
manufacturers can meet are 20% inductance and 7% DCR at room
temperature.
The first decision in designing the inductor is choosing the core
material. Several possibilities for providing low core loss at high
frequencies include the powder cores (from Micrometals, Inc., for
example, or Kool-Mu® from Magnetics®) and the gapped soft ferrite
cores (for example, 3F3 or 3F4 from Philips). Low frequency
powdered iron cores should be avoided due to their high core
loss, especially when the inductor value is relatively low and the
ripple current is high.
The best choice for a core geometry is a closed-loop type of
inductor, such as a potentiometer core; a PQ, U, or E core; or a
toroid. A good compromise between price and performance is a
core with a toroidal shape.
Many useful magnetics design references are available for
quickly designing a power inductor, such as
•
•
Selecting a Standard Inductor
•
•
•
Coilcraft, Inc.
Coiltronics
Sumida Corporation
CURRENT SENSE AMPLIFIER
Most designs require the regulator output voltage measured at
the CPU pins to droop when the output current increases. The
specified voltage drop corresponds to a dc output resistance (RO),
also referred to as a load line.
The output current is measured by summing the voltage across
each inductor and passing the signal through a low-pass filter. This
summer filter is the CS amplifier configured with Resistor RPH(x)
(summer) and Resistors RCS and CCS (filters). The impedance gain
of the regulator is set by the following equations, where RL is the
DCR of the output inductors:
R
RO = CS × RL
(6)
RPH ( x )
CCS =
L
R L × RCS
(7)
The user has the flexibility to choose either RCS or RPH(x). However,
it is best to select RCS equal to 100 kΩ, and then solve for RPH(x)
by rearranging Equation 6. In the following example, RO = 1 mΩ
to equal the design load line.
R
RPH ( x ) = L × RCS
RO
RPH ( x ) =
1.4 mΩ
1.0 mΩ
× 100 kΩ = 140 kΩ
Next, use Equation 7 to solve for CCS.
CCS =
320 nH
1.4 mΩ × 100 kΩ
= 2.28 nF
It is best to include two locations for CCS in the layout so that
standard values can be used in parallel to better achieve the
desired value. For best accuracy, CCS should be a 5% or 10%
NPO capacitor. This example uses a 5% combination for CCS
of two 1 nF capacitors in parallel. Recalculating RCS and RPH(x)
using this capacitor combination yields 114 kΩ and 160 kΩ.
The closest standard 1% value for RPH(x) is 158 kΩ.
Magnetic Designer Software from Intusoft
Designing Magnetic Components for High Frequency DCDC Converters, by William T. McLyman, K G Magnetics,
Inc., ISBN 1883107008
Rev. 1 | Page 19 of 29 | www.onsemi.com
ADP3193A
INDUCTOR DCR TEMPERATURE CORRECTION
4.
When the inductor DCR is used as the sense element and
copper wire is used as the source of the DCR, the user needs to
compensate for temperature changes of the inductor’s winding.
Fortunately, copper has a well-known temperature coefficient (TC)
of 0.39%/°C.
rCS2 =
rCS1 =
If RCS is designed to have an opposite and equal percentage of
change in resistance to that of the wire, it cancels the temperature variation of the inductor DCR. Due to the nonlinear nature of
negative temperature coefficient (NTC) thermistors, Resistors RCS1
and RCS2 are needed. See Figure 11 to linearize the NTC and
produce the desired temperature tracking.
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
OR LOW-SIDE MOSFET
TO
SWITCH
NODES
RTH
RPH1
ADP3193A
RPH2
rTH =
CSCOMP
TO
VOUT
SENSE
k=
CCS1
12
CCS2
(1 − A)
1
A
−
1 − rCS2 r1 − rCS2
1
1
1
−
1 − rCS2 rCS1
(9)
(10)
RTH ( ACTUAL )
(11)
RTH (CALCULATED )
RPH3
RCS2
13
CSSUM
( A − B ) × r1 × r2 − A × (1 − B ) × r2 + B × (1 − A ) × r1
(8)
A × (1 − B ) × r1 − B × (1 − A ) × r2 − ( A − B )
Calculate RTH = rTH × RCS, and then select the closest value
thermistor available. In addition, compute a scaling factor (k)
based on the ratio of the actual thermistor value used relative
to the computed one.
5.
RCS1
Compute the relative values for RCS1, RCS2, and RTH using
KEEP THIS PATH
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
CSREF
06652-010
11
Figure 11. Temperature-Compensation Circuit Values
The following procedure and equations yield values to use for
RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given
RCS value.
1.
Select an NTC based on type and value. Because the value
is unknown, use a thermistor with a value close to RCS. The
NTC should also have an initial tolerance of better than 5%.
2.
Based on the type of NTC, find its relative resistance value
at two temperatures. The temperatures that work well are
50°C and 90°C. These resistance values are called
A (RTH(50°C))/RTH(25°C)) and B (RTH(90°C))/RTH(25°C)). The relative
value of the NTC is always 1 at 25°C.
3.
Find the relative value of RCS required for each of these
temperatures. This is based on the percentage of change
needed, which in this example is initially 0.39%/°C. These
temperatures are called r1 (1/(1 + TC × (T1 − 25°C)))
and r2 (1/(1 + TC × (T2 − 25°C))), where TC = 0.0039 for
copper, T1 = 50°C, and T2 = 90°C. From this, r1 = 0.9112 and
r2 = 0.7978.
Calculate values for RCS1 and RCS2 using Equation 12 and
Equation 13.
RCS1 = RCS × k × rCS1
(12)
RCS2 = RCS × ((1 − k ) + (k × rCS2 ))
(13)
In this example, RCS is calculated to be 114 kΩ. Look for an
available 100 kΩ, 0603-size thermistor. One such thermistor
is the Vishay NTHS0603N01N1003JR NTC thermistor with
A = 0.3602 and B = 0.09174. From these values, rCS1 = 0.3795,
rCS2 = 0.7195, and rTH = 1.075.
Solving for RTH yields 122.55 kΩ; therefore, 100 kΩ is chosen,
making k = 0.816. Next, find RCS1 and RCS2 to be 35.3 kΩ and
87.9 kΩ. Finally, choose the closest 1% resistor values, which
yields a choice of 35.7 kΩ and 88.7 kΩ.
OUTPUT OFFSET
The Intel specification requires that with no load the nominal
output voltage of the regulator be offset to a value lower than the
nominal voltage corresponding to the VID code. The offset is
set by a constant current source flowing out of the FB pin (IFB)
and flowing through RB. The value of RB can be found using
Equation 14.
RB =
RB =
VVID − VONL
(14)
I FB
1.4 V − 1.381 V
15 μA
= 1.27 kΩ
The closest standard 1% resistor value is 1.27 kΩ.
Rev. 1 | Page 20 of 29 | www.onsemi.com
ADP3193A
COUT SELECTION
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
Use some simple design guidelines to determine the requirements. These guidelines are based on having both bulk
capacitors and ceramic capacitors in the system.
First, select the total amount of ceramic capacitance. This is
based on the number and type of capacitor to be used. The best
location for ceramic capacitors is inside the socket, with twelve
to eighteen 1206-size pieces being the physical limit. Other
capacitors can be placed along the outer edge of the socket as well.
To meet the conditions of these equations and transient response,
the ESR of the bulk capacitor bank (RX) should be less than two
times the droop resistance (RO). If CX(MIN) is larger than CX(MAX),
the system cannot meet the VID on-the-fly specification and
to maintain the output ripple may require the use of a smaller
inductor or more phases (in addition to increasing the switching
frequency).
This example uses twenty-six 10 μF 1206 MLC capacitors
(CZ = 260 μF). The VID on-the-fly step change is 450 mV in
230 μs with a settling error of 2.5 mV. The maximum allowable
load release overshoot for this example is 50 mV; therefore,
solving for the bulk capacitance yields
To determine the minimum amount of ceramic capacitance
required, start with a worst-case load step that occurs immediately
after a switching cycle has stopped. The ceramic capacitance then
delivers the charge to the load while the load is ramping up until
the VR responds with the next switching cycle.
⎛
⎞
⎜
⎟
⎜
⎟
320 nH × 50 A
− 260 μF ⎟ = 1.64 mF
C X ( MIN ) ≤ ⎜
50 mV ⎞
⎜ ⎛
⎟
⎟ × 1.4 V
⎜⎜ 3 × ⎜⎜1.0 mΩ +
⎟⎟
⎟
50
A
⎠
⎝ ⎝
⎠
Equation 15 provides the designer with a rough approximation
for determining the minimum ceramic capacitance. Due to the
complexity of the PCB parasitics and bulk capacitors, the actual
amount of ceramic capacitance required can vary.
C X ( MAX ) ≤
C Z ( MIN )
⎡ 1 ⎛1
ΔI ⎤
1
≥
×⎢
× ⎜ − D ⎞⎟ − O ⎥
2RO ⎣ f SW ⎝ n
⎠ 2S R ⎦
(15)
The typical ceramic capacitors consist of multiple 10 μF or
22 μF capacitors. For this example, Equation 15 yields 265 μF,
so twenty-six 10 μF ceramic capacitors suffice.
Next, there is an upper limit imposed on the total amount of bulk
capacitance (CX), considering the VID on-the-fly voltage stepping
of the output (voltage step, VV, in time, tV, with error of VERR).
A lower limit is based on meeting the capacitance for load
release at a given maximum load step (ΔIO) and a maximum
allowable overshoot. The total amount of load release voltage
is ΔVO = ΔIO × RO + ΔVrl, where ΔVrl is the maximum allowable
overshoot voltage.
⎛
⎞
⎜
⎟
⎜
⎟
L × Δ IO
C X ( MIN ) ≥ ⎜
− CZ ⎟
⎜ n × ⎛⎜ R + ΔVrl ⎞⎟ × V
⎟
⎜ O ΔI ⎟ VID
⎜
⎟
O
⎝
⎠
⎝
⎠
C X ( MAX ) ≤
⎛
⎛ V
nKRO
VV
L
⎜
×
×
1 + ⎜⎜ t V VID ×
⎜
2 2
nk RO VVID ⎜
V
L
V
⎝
⎝
⎛V
where k = − ln ⎜⎜ ERR
⎝ VV
⎞
⎟.
⎟
⎠
(16)
⎞
⎟
⎟
⎠
2
⎞
⎟
− 1⎟ − C Z
⎟
⎠
(17)
320 nH × 450 mV
3 × 5.2 2 × (1.0 mΩ )2 × 1.4 V
×
2
⎛
⎞
⎛ 230 μs × 1.4 V × 3 × 5.2 × 1.0 mΩ ⎞
⎜
⎟
⎜
⎟
− 1⎟ − 260 μF = 42.7 mF
⎜ 1+ ⎜
⎟
450 mV × 320 nH
⎜
⎟
⎝
⎠
⎝
⎠
where k = 5.2.
Using eight 560 μF aluminum-poly capacitors with a typical
ESR of 6 mΩ each yields CX = 4.48 mF with an RX = 0.75 mΩ.
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the high frequency
ringing during a load change.
This is tested using
L X ≤ C Z × RO 2 × Q 2
L X ≤ 260 μF × (1 mΩ )2 ×
4
= 347 pH
3
(18)
where Q2 is limited to 4/3 to ensure a critically damped system.
In this example, LX is approximately 240 pH for the eight
aluminum-poly capacitors, which satisfies this limitation. If the
LX of the chosen bulk capacitor bank is too large, the number of
ceramic capacitors needs to be increased, or lower ESL bulks
need to be used if there is excessive undershoot during a load
transient.
For this multimode control technique, all ceramic designs can
be used if the conditions of Equation 15 through Equation 18
are satisfied.
Rev. 1 | Page 21 of 29 | www.onsemi.com
ADP3193A
POWER MOSFETS
For our example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive
voltage (the supply voltage to the ADP3120A) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With VGATE ~10 V, logic-level threshold MOSFETs
(VGS(TH) < 2.5 V) are recommended.
The maximum output current (IO) determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. With
the ADP3193A, currents are balanced between phases; therefore,
the current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (nSF). With conduction losses
being dominant, Equation 19 shows the total power that is
dissipated in each synchronous MOSFET in terms of the ripple
current per phase (IR) and the average total output current (IO):
⎡⎛ I
PSF = (1 − D ) × ⎢⎜⎜ O
⎢⎣⎝ n SF
2
⎞
1 ⎛ n IR
⎟ +
×⎜
⎟
12 ⎜⎝ n SF
⎠
⎞
⎟
⎟
⎠
2
⎤
⎥ × R DS ( SF )
⎥⎦
(19)
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, the user can find the
required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to
an ambient temperature of 50°C, a safe limit for PSF is 1 W to
1.5 W at 120°C junction temperature. Therefore, for this example
(56 A maximum), RDS(SF) (per MOSFET) is less than 4.7 mΩ. This
RDS(SF) is also at a junction temperature of about 120°C. As a result,
users need to account for this when making this selection. This
example uses two low-side MOSFETs at 4.8 mΩ, each at 120°C.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to the input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous
MOSFETs when the switch node goes high.
In addition, the time to switch the synchronous MOSFETs off
should not exceed the nonoverlap dead time of the MOSFET
driver (45 ns typical for the ADP3120A). The output impedance
of the driver is approximately 2 Ω, and the typical MOSFET
input gate resistances are about 1 Ω to 2 Ω. Therefore, a total
gate capacitance of less than 6000 pF should be adhered to.
Because two MOSFETs are in parallel, the input capacitance for
each synchronous MOSFET should be limited to 6000 pF.
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss is related to the amount of time for
the main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed on
the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET:
PS ( MF ) = 2 × f SW ×
VCC × I O
n MF
× RG ×
n MF
× C ISS
n
(20)
where:
nMF is the total number of main MOSFETs.
RG is the total gate resistance (2 Ω for the ADP3120A and about
1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω).
CISS is the input capacitance of the main MOSFET.
Adding more main MOSFETs (nMF) does not help the switching
loss per MOSFET because the additional gate capacitance slows
switching. Use lower gate capacitance devices to reduce
switching loss.
The conduction loss of the main MOSFET is given by the
following:
⎡⎛ I
PC ( MF ) = D × ⎢⎜⎜ O
n
⎣⎢⎝ MF
2
⎞
1 ⎛ n × IR
⎟ + ×⎜
⎟ 12 ⎜ n
⎠
⎝ MF
2
⎞ ⎤
⎟ ⎥ × RDS( MF )
⎟ ⎥
⎠ ⎦
(21)
where RDS(MF) is the on resistance of the MOSFET.
Typically, for main MOSFETs, the highest speed (low CISS)
device is preferred, but such devices usually have higher on
resistance. Select a device that meets the total power dissipation
(about 1.5 W for a single D-PAK) when combining the switching
and conduction losses.
For this example, an NTD40N03L is selected as the main MOSFET
(three total, nMF = 3), with CISS = 584 pF (maximum) and RDS(MF) =
19 mΩ (maximum at TJ = 120°C). An NTD110N02L is selected as
the synchronous MOSFET (three total, nSF = 3), with CISS = 2710 pF
(maximum) and RDS(SF) = 4.8 mΩ (maximum at TJ = 120°C). The
synchronous MOSFET CISS is less than 6000 pF, satisfying this
requirement.
Solving for the power dissipation per MOSFET at IO = 56 A and
IR = 11.7 A yields 1.53 W for each synchronous MOSFET and
1.06 W for each main MOSFET. As a guide, limit the MOSFET
power dissipation to 1.5 W. The values calculated in Equation 20
and Equation 21 will comply with this guideline.
Finally, consider the power dissipation in the driver for each
phase. This is best expressed as QG for the MOSFETs and is
given by Equation 22.
⎡f
⎤
PDRV = ⎢ SW × (n MF × QGMF + nSF × Q GSF ) + I CC ⎥ × VCC (22)
⎣⎢ 2 × n
⎦⎥
where QGMF is the total gate charge for each main MOSFET, and
QGSF is the total gate charge for each synchronous MOSFET
Rev. 1 | Page 22 of 29 | www.onsemi.com
ADP3193A
Also shown is the standby dissipation factor (ICC × VCC) of the
driver. For the ADP3120A, the maximum dissipation should be
less than 400 mW. In this example, with ICC = 7 mA, QGMF = 5.8 nC,
and QGSF = 48 nC, there is 191 mW in each driver, which is below
the 400 mW dissipation limit. See the ADP3120A data sheet for
more details.
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor should be chosen to provide
the best combination of thermal balance, stability, and transient
response. Equation 23 is used for determining the optimum value.
AR × L
RR =
(23)
3 × A D × R DS × C R
0.2 × 320 nH
RR =
3 × 5 × 4.8 mΩ × 5 pF
= 178 kΩ
where:
AR is the internal ramp amplifier gain.
AD is the current-balancing amplifier gain.
RDS is the total low-side MOSFET on resistance.
CR is the internal ramp capacitor value.
VR =
A R × (1 − D ) × VVID
(24)
R R × C R × f SW
0.2 × (1 − 0.117 ) × 1.4 V
178 kΩ × 5 pF × 330 kHz
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, first find the resistor value
for RLIM. The current-limit threshold for the ADP3193A is set with
a constant current source flowing out of the ILIMIT pin, which
sets up a voltage (VLIM) across RLIM with a gain of 82.6 mV/V (ALIM).
Therefore, increasing RLIM now increases the current limit. RLIM
can be found using the following equation:
R LIM =
VCL
A LIM × I ILIMIT
=
I LIM × RCSA
× R REF
82.6 mV
(26)
In this equation, ILIM is the peak average current limit for the
supply output and is equal to the dc current limit plus the
output ripple current. In this example, choosing a dc current
limit of 88.3 A and having a ripple current of 11.7 A yields an
ILIM of 100 A, resulting in an RLIM of 121 kΩ, for which 121 kΩ
is chosen as the nearest 1% value.
The per-phase initial duty cycle limit and peak current during a
load step are determined by
The internal ramp voltage magnitude can be calculated as follows:
VR =
to be at least 0.5 V by decreasing the ramp resistor for noise
immunity.
= 842 mV
The size of the internal ramp can be increased or decreased. If it is
increased, stability and noise rejection improve, but the transient
response degrades. Conversely, if the ramp size is decreased, the
transient response improves, but noise rejection and stability
degrade.
In the denominator of Equation 23, the factor of 3 sets a ramp
size that produces an optimal balance for good stability, transient
response, and thermal balance.
D MAX = D ×
I PHMAX ≅
VCOMP ( MAX ) − V BIAS
V RT
D MAX (VIN − VVID )
×
f SW
L
(27)
(28)
For the ADP3193A, the maximum COMP voltage (VCOMP(MAX))
is 3.4 V, and the COMP pin bias voltage (VBIAS) is 1.1 V. In this
example, the maximum duty cycle is 0.23. Because this is small
due to the VRT being much larger than 0.5 V, reduce the ramp
resistor to get closer to 0.5 V VRT and to obtain a larger duty
cycle. Choosing a ramp resistor of 267 kΩ results in a VRT of
0.79 V, a DMAX of 0.34, and a peak current of 34 A.
The limit of the peak per-phase current during the secondary
current limit is determined by
I PHLIM ≅
VCOMP (CLAMPED ) − V BIAS
A D × R DS ( MAX )
(29)
COMP PIN RAMP
In addition to the internal ramp, there is a ramp signal on the
COMP pin due to the droop voltage and output voltage ramps.
This ramp amplitude adds to the internal ramp to produce the
following overall ramp signal at the PWM input:
VRT =
VR
⎛
2 × (1 − n × D )
⎜1 −
⎜ n× f ×C × R
X
SW
O
⎝
(25)
⎞
⎟
⎟
⎠
For the ADP3193A, the current balancing amplifier gain (AD) is 5
and the clamped COMP pin voltage is 2 V. Using an RDS(MAX) of
5.6 mΩ (low-side on resistance at 150°C) results in a per-phase
peak current limit of 36 A. This current level can be reached only
with an absolute short at the output, and the current-limit latch-off
function shuts down the regulator before overheating can occur.
In this example, the overall ramp signal is 1.19 V. However,
if the ramp size is smaller than 0.5 V, increase the ramp size
Rev. 1 | Page 23 of 29 | www.onsemi.com
ADP3193A
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3193A allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make the
regulator and output decoupling appear as an output impedance
that is entirely resistive over the widest possible frequency range,
including dc, and that is equal to the droop resistance (RO). With
the resistive output impedance, the output voltage droops in
proportion to the load current at any load current slew rate.
This ensures optimal positioning and minimizes the output
decoupling.
Because of the multimode feedback structure of the ADP3193A, it
is necessary to set the feedback compensation so that the converter
R E = n × RO + A D × R DS +
R L × V RT
VVID
R E = 3 × 1 mΩ + 5 × 4.8 mΩ +
TA = C X × (R O − R ' ) +
+
output impedance works in parallel with the output decoupling
to make the load look entirely resistive. In addition, it is necessary
to compensate for several poles and zeros created by the output
inductor and the decoupling capacitors (output filter).
A Type III compensator on the voltage feedback is adequate for
proper compensation of the output filter.
Equation 30 to Equation 34 are intended to yield an optimal
starting point for the design; some adjustments may be necessary
to account for PCB and component parasitic effects (see the
Tuning Procedure for ADP3193A section).
First, compute the time constants for all the poles and zeros in
the system using Equation 30 to Equation 34.
2 × L × (1 − n × D ) × VRT
(30)
n × C X × RO × VVID
1.4 mΩ × 0.79 V
1.4 V
+
2 × 320 nH × (1 − 0.35) × 0.79 V
3 × 4.48 mF × 1 mΩ × 1.4 V
= 45.3 mΩ
347 pH 1 mΩ − 0.5 mΩ
L X RO − R'
×
= 4.48 mF × (1 mΩ − 0.5 mΩ ) +
×
= 2.47 μs
1 mΩ
0.75 mΩ
RO
RX
TB = (R X + R ' − RO ) × C X = (0.75 mΩ + 0.5 mΩ − 1 mΩ ) × 4.48 mF = 1120 ns
⎛
A D × R DS
V RT × ⎜ L −
⎜
2 × f SW
⎝
TC =
VVID × R E
⎞
⎟
⎟
⎠
(32)
⎛
5 × 4.8 mΩ ⎞
⎟
0.79 V × ⎜ 320 nH −
⎜
2 × 330 kHz ⎟⎠
⎝
=
= 3.53 μs
1.4 V × 45.3 mΩ
C X × C Z × RO2
TD =
C X × (R O − R ' ) + C Z × RO
=
4.48 mF × 260 μF × (1 mΩ )2
4.48 mF × (1 mΩ − 0.5 mΩ ) + 260 μF × 1 mΩ
(31)
(33)
= 466 ns
(34)
where:
R' is the PCB resistance from the bulk capacitors to the ceramics and is approximately 0.5 mΩ (assuming a 4-layer, 1 oz motherboard).
RDS is the total low-side MOSFET on resistance per phase.
AD = 5.
VRT = 0.79 V.
LX = 347 pH for the eight aluminum-poly capacitors.
The compensation values can then be solved using
CA =
n × RO × TA
RE × R B
=
3 × 1 mΩ × 2.47 μs
45.3 mΩ × 1.27 kΩ
= 128 pF
(35)
RA =
TC 3.53 μs
=
= 27.5 kΩ
C A 128 pF
(36)
CB =
TB 1120 ns
=
= 882 pF
R B 1.27 kΩ
(37)
C FB =
TD
466 ns
=
= 16.9 pF
R A 27.5 kΩ
These equations result in the starting values prior to tuning the
design that account for layout and other parasitic effects (see
the Tuning Procedure for ADP3193A section). The final values
selected after tuning are
CA = 220 pF
RA = 22.1 kΩ
CB = 560 pF
CFB = 15 pF
(38)
Rev. 1 | Page 24 of 29 | www.onsemi.com
ADP3193A
two 2700 μF, 16 V aluminum electrolytic capacitors and eight
4.7 μF ceramic capacitors.
Figure 12 and Figure 13 show the typical transient response
using these compensation values.
To reduce the input current, di/dt, to a level below the recommended maximum of 0.1 A/μs, an additional small inductor
(L > 370 nH at 18 A) should be inserted between the converter
and the supply bus. This inductor also acts as a filter between
the converter and the primary power source.
SHUNT RESISTOR DESIGN
550
0.50
500
0.45
RSHUNT (Ω)
450
20mV/DIV
CIN SELECTION AND INPUT CURRENT
di/dt REDUCTION
ICRMS = 0.117 × 65 A ×
0.35
350
0.30
300
0.25
250
0.20
200
0.15
7.5
8.0
8.5
9.0
9.5
10.0
10.5
0.10
11.0
Figure 14. Typical Shunt Resistor Value and Power Dissipation
for Different UVLO Voltages
The maximum power dissipated is calculated using Equation 40.
In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude of one-nth the
maximum output current. To prevent large voltage transients,
use a low ESR input capacitor sized for the maximum rms
current. The maximum rms capacitor current is given by
1
−1
N×D
RSHUNT
VIN (UVLO)
Figure 13. Typical Transient Response for Design Example Load Release
I CRMS = D × I O ×
400
150
7.0
06652-016
2μs/DIV
0.40
PSHUNT
PSHUNT (W)
Figure 12. Typical Transient Response for Design Example Load Step
The ADP3193A uses a shunt to generate 5 V from the 12 V
supply range. A trade-off can be made between the power
dissipated in the shunt resistor and the UVLO threshold.
Figure 14 shows the typical resistor value needed to realize
certain UVLO voltages and the maximum power dissipated in
the shunt resistor for these UVLO voltages.
06652-018
2μs/DIV
06652-015
20mV/DIV
(39)
1
− 1 = 10. 3 A
3 × 0.117
The capacitor manufacturer’s ripple-current ratings are often
based on only 2000 hours of life. As a result, it is advisable to
further derate the capacitor or to choose a capacitor rated at a
higher temperature than is required. Several capacitors can be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
PMAX =
(V
IN ( MAX )
− VCC ( MIN )
R SHUNT
)
2
(40)
where:
VIN(MAX) is the maximum voltage from the 12 V input supply
(if the 12 V input supply is 12 V ± 5%, VIN(MAX) = 12.6 V;
if the 12 V input supply is 12 V ± 10%, VIN(MAX) = 13.2 V).
VCC(MIN) is the minimum VCC voltage of the ADP3193A. This is
specified as 4.75 V.
RSHUNT is the shunt resistor value.
The CECC standard specification for power rating in surfacemount resistors is 0.1 W for 0603-size resistors, 0.125 W for 0805size resistors, and 0.25 W for 1206-size resistors.
Rev. 1 | Page 25 of 29 | www.onsemi.com
ADP3193A
TUNING PROCEDURE FOR ADP3193A
RCS2 ( NEW ) = R CS2 (OLD ) ×
Set Up and Test the Circuit
1.
2.
3.
4.
Build a circuit based on the compensation values
computed from the design spreadsheet.
Connect a dc load to the circuit.
Turn on the ADP3193A and verify that it operates properly.
Check for jitter with no load and full load conditions.
Set the DC Load Line
1.
Measure the output voltage with no load (VNL) and verify
that it is within the specified tolerance range.
2.
Measure the output voltage with a full load when the
device is cold (VFLCOLD). Allow the board to run for ~10
minutes at full load, and then measure the output when the
device is hot (VFLHOT). If the difference between the two
measured voltages is more than a few millivolts, adjust RCS1
and RCS2 using Equation 41 and Equation 43.
Repeat Step 2 until no adjustment of RCS1 and RCS2 is needed.
4.
Compare the output voltage with no load to that with a full
load using 5 A steps. Compute the load line slope for each
change, and then calculate the average to determine the
overall load line slope (ROMEAS).
5.
If the difference between ROMEAS and RO is more than 0.05 mΩ,
use Equation 42 to adjust the RPH values.
R
(42)
R PH ( NEW ) = R PH (OLD ) × OMEAS
RO
6.
Repeat Step 6 and Step 7 until no adjustment of RPH is needed.
Once this is achieved, do not change RPH, RCS1, RCS2, or RTH
for the remainder of the procedure.
7.
Measure the output ripple with no load and with a full load
with scope, making sure both are within specifications.
RCS1(OLD) × RTH (25°C ) + (R CS1(OLD) − RCS2(NEW) ) × (RCS1(OLD) − RTH (25°C ) )
Set the AC Load Line
1.
Remove the dc load from the circuit and connect the
dynamic load.
2.
Connect the scope to the output voltage and set it to dccoupling mode with the time scale of 100 μs/div.
3.
Set the dynamic load for a transient step of about 40 A at
1 kHz with 50% duty cycle.
4.
Measure the output waveform. (Note that use of a dc offset
on the scope may be necessary to see the waveform.) Try to
use a vertical scale of 100 mV/div or finer. This waveform
should look similar to Figure 15.
(41)
3.
1
R CS1(OLD) + RTH (25°C )
RCS1( NEW ) =
V NL − VFLCOLD
V NL − VFLHOT
−
1
(43)
RTH (25°C )
5.
Use the horizontal cursors to measure VACDRP and VDCDRP,
as shown in Figure 15. Do not measure the undershoot or
overshoot that occurs immediately after this step.
6.
If the difference between VACDRP and VDCDRP is more than a
few millivolts, use Equation 44 to adjust CCS. It may be
necessary to try several parallel values to obtain an adequate
one, because there are limited standard capacitor values
available. It is a good idea to have locations for two capacitors
in the layout for this reason.
V
C CS ( NEW ) = C CS (OLD ) × ACDRP
(44)
V DCDRP
7.
Repeat Step 5 and Step 6 until no further adjustment of CCS
is needed. Once this is achieved, do not change CCS for the
remainder of the procedure.
8.
Set the dynamic load step to its maximum step size (but do
not use a step size that is larger than needed) and verify
that the output waveform is square, meaning VACDRP and
VDCDRP are equal.
VACDRP
VDCDRP
Set the Initial Transient
06652-012
1.
Figure 15. AC Load Line Waveform
With the dynamic load set at the maximum step size,
expand the scope time scale to either 2 μs/div or 5 μs/div.
This may result in a waveform that has two overshoots and
one minor undershoot before achieving the final desired
value after VDROOP (see Figure 16).
Rev. 1 | Page 26 of 29 | www.onsemi.com
ADP3193A
VTRAN1 by the amount of ripple while still meeting the
specifications.
If VTRAN1 and VTRANREL are less than the desired final droop, this
implies that capacitors can be removed. When removing capacitors, also check the output ripple voltage to ensure that it is still
within specifications.
VDROOP
LAYOUT AND COMPONENT PLACEMENT
VTRAN2
06652-013
VTRAN1
General Recommendations
Figure 16. Transient Setting Waveform
2.
If both overshoots are larger than desired, try the following
adjustments in the order shown:
•
•
•
Increase the ramp resistor by 25% (RRAMP).
For VTRAN1, increase CB or increase the switching
frequency.
For VTRAN2, increase RA by 25% and decrease CA by 25%.
If these adjustments do not change the response, it is
because the system is limited by the output decoupling.
Check the output response and the switching nodes each
time a change is made to ensure that the response is stable.
3.
For load release (see Figure 17), if VTRANREL is larger than
the allowed overshoot, there is not enough output
capacitance. Either increase the capacitance directly or
decrease the inductor values. If the inductors are changed,
however, it will be necessary to redesign the circuit using
the information from the spreadsheet and to repeat all
tuning guide procedures.
VDROOP
06652-014
VTRANREL
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
Figure 17. Transient Setting Waveform
Because the ADP3193A turns off all of the phases (switches
inductors to ground), no ripple voltage is present during load
release. Therefore, the user does not have to add headroom for
ripple, which allows load release VTRANREL to be larger than
For good results, a PCB with at least four layers is recommended.
This provides the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the remainder of the power-delivery current paths.
Keep in mind that each square unit of 1 oz copper trace has a
resistance of ~0.53 mΩ at room temperature.
When high currents must be routed between PCB layers, use
vias liberally to create several parallel current paths so that the
resistance and inductance introduced by these current paths are
minimized and the via current rating is not exceeded.
If critical signal lines (including the output voltage sense lines of
the ADP3193A) must cross through power circuitry, it is best to
interpose a signal ground plane between those signal lines and
the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
increasing signal ground noise.
An analog ground plane should be used around and under the
ADP3193A as a reference for the components associated with
the controller. This plane should be tied to the nearest outputdecoupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing into it.
The components around the ADP3193A should be located close
to the controller with short traces. The most important traces to
keep short and away from other traces are those to the FB and
CSSUM pins. The output capacitors should be connected as
close as possible to the load (or connector) that receives the
power, for example, as close as possible to a microprocessor
core. If the load is distributed, the capacitors should also be
distributed and placed in greater proportion where the load
tends to be more dynamic.
Avoid crossing any signal lines over the switching power path loop
(described in the Power Circuitry Recommendations section).
Rev. 1 | Page 27 of 29 | www.onsemi.com
ADP3193A
Power Circuitry Recommendations
The switching power path on the PCB should be routed to
encompass the shortest possible length to minimize radiated
switching noise energy (that is, EMI) and conduction losses in
the board. Failure to take proper precautions often results in
EMI problems for the entire PC system and noise-related
operational problems in the power-converter control circuitry.
The switching power path is the loop formed by the current
path through the input capacitors and the power MOSFETs,
including all interconnecting PCB traces and planes. Using
short, wide interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance in the switching
loop, which can cause high energy ringing, and it accommodates
the high current demand with minimal voltage loss.
When a power-dissipating component, such as a power MOSFET,
is soldered to a PCB, it is recommended to use vias liberally both
directly on the mounting pad and immediately surrounding it. Two
important reasons for this are improved current rating through
the vias and improved thermal performance from vias extended
to the opposite side of the PCB, where a plane can more readily
transfer the heat to the air. Make a mirror image on the opposite
side of the PCB of any pad being used to heat-sink the MOSFETs.
This helps achieve the best thermal dissipation in the air around
the board. To further improve thermal performance, use the largest
pad area possible.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
For best EMI containment, a solid power ground plane should
be used as one of the inner layers, extending fully under all the
power components.
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the FB and
FBRTN pins, which connect to the signal ground at the load. To
avoid differential mode noise pickup in the sensed signal, the
loop area should be small. Therefore, the FB and FBRTN traces
should be routed adjacent to each other on top of the power
ground plane back to the controller.
The feedback traces from the switch nodes should be connected
as close as possible to the inductor, and the CSREF signal
should be connected to the output voltage at the nearest
inductor to the controller.
Rev. 1 | Page 28 of 29 | www.onsemi.com
ADP3193A
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
17
16
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
32
25
24
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3193AJCPZ-RL1
1
Temperature Range
0°C to 85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option
CP-32-2
Ordering Quantity
2,500
Z = RoHS Compliant Part.
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
ON Semiconductor and
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
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Rev. 1 | Page 29 of 29 | www.onsemi.com
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