TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 2.25-MHz 400-mA/600-mA DUAL STEP-DOWN CONVERTER Check for Samples: TPS62404-Q1 FEATURES 1 • • • • • • • Qualified for Automotive Applications High Efficiency—Up to 95% VIN Range From 2.5 V to 6 V 2.25-MHz Fixed Frequency Operation Output Current 400 mA and 600 mA Adjustable Output Voltage From 0.6 V to VIN Pin Selectable Output Voltage Supports Simple Dynamic Voltage Scaling • • • • • EasyScale™ Optional One-Pin Serial Interface Power Save Mode at Light Load Currents 180° Out of Phase Operation Output Voltage Accuracy in PWM Mode ±1% Typical 32-mA Quiescent Current for Both Converters 100% Duty Cycle for Lowest Dropout Available in a 10-Pin QFN (3mm×3mm) • • DESCRIPTION The TPS6240x device series are synchronous dual step-down DC-DC converters optimized for battery powered portable applications. They provide two independent output voltage rails powered by 1-cell Li-Ion or 3-cell NiMH/NiCD batteries. The devices are also suitable to operate from a standard 3.3-V or 5-V voltage rail. With the EasyScale™ serial interface the output voltages can be modified during operation. The fixed output voltage versions TPS62401, TPS62402, TPS62403, and TPS62404 support one pin controlled simple Dynamic Voltage Scaling for low power processors. The TPS6240x operates at 2.25-MHz fixed switching frequency and enters the power save mode operation at light load currents to maintain high efficiency over the entire load current range. For low noise applications the devices can be forced into fixed frequency PWM mode by pulling the MODE/DATA pin high. In the shutdown mode, the current consumption is reduced to 1.2-mA, typical. The devices allow the use of small inductors and capacitors to achieve a small solution size. The TPS62400 is available in a 10-pin leadless package (3mm×3mm QFN) 100 TPS62404 VIN 2.5 V – 6 V VIN 10 mF FB 1 90 2.2 mH SW1 Vout1: 1.575 V 80 400 mA 10 mF EN_1 EN_2 SW2 2.2 mH ADJ2 GND VOUT2 = 1.8 V VIN = 3.6 V MODE/DATA = 0 60 50 VOUT1 = 1.575 V 40 Vout2: 3.3 V 600 mA MODE/ DATA Efficiency 70 DEF_1 10 mF 30 20 10 0 0.01 0.1 1 10 100 1000 IOUT mA 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PART NUMBER TJ TPS62400 TPS62401 DEFAULT OUTPUT VOLTAGE (1) OUT1 Fixed default OUT2 OUT1 –40°C to 125°C TPS62402 TPS62403 OUT1 OUT1 Fixed default DEF_1 = Low 1.2V DEF_1 = High 1.1V DEF_1 = Low 1.575V Fixed default 2.8V Fixed default OUT2 (1) (2) DEF_1 = High 1.8V Fixed default 3.3V OUT2 TPS62404 DEF_1 = Low 1.575V Fixed default 1.8V OUT2 ORDERING (2) PACKAGE MARKING DRC TPS62400QDRCQ1 PREVIEW DRC TPS62401QDRCQ1 PREVIEW DRC TPS62402QDRCQ1 PREVIEW DRC TPS62403QDRCQ1 PREVIEW DRC TPS62404QDRCQ1 OET 600mA DEF_1 = High 1.1V Fixed default QFN PACKAGE 400mA Adjustable OUT2 OUT1 OUTPUT CURRENT DEF_1 = High 1.9V DEF_1 = Low 1.575V Fixed default 3.3V 400mA 600mA 400mA 600mA 400mA 600mA 400mA 600mA Contact TI for other fixed output voltage options. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Input voltage range on VIN (2) V V ≤ 0.5 mA Voltage on SW1, SW2 –0.3 to 7 V Voltage on ADJ2, FB1 –0.3 to VIN +0.3, ≤ 7 V 150 °C –65 to 150 °C current into MODE/DATA TJ(max) Maximum operating junction temperature Tstg Storage temperature range (2) UNIT –0.3 to VIN +0.3, ≤ 7 Voltage range on EN, MODE/DATA, DEF_1 (1) VALUE –0.3 to 7 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS 2 PACKAGE RqJA POWER RATING FOR TA ≤ 25°C DERATING FACTOR ABOVE TA = 25°C DRC 49°C/W 2050mW 21mW/°C Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VIN TJ NOM MAX UNIT Supply voltage 2.5 6 Output voltage range for adjustable voltage 0.6 VIN V V Operating junction temperature -40 125 °C ELECTRICAL CHARACTERISTICS VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2mH, COUT = 20mF, TA = TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN Input voltage range IQ 2.5 Operating quiescent current ISD Shutdown current VUVLO Undervoltage lockout threshold 6.0 V One converter, IOUT = 0mA. PFM mode enabled (Mode = 0) device not switching, EN1 = 1 OR EN2 = 1 19 29 mA Two converter, IOUT = 0mA. PFM mode enabled (Mode = 0) device not switching, EN1 = 1 AND EN2 = 1 32 48 mA IOUT = 0mA, MODE/DATA = GND, for one converter, VOUT 1.575V (1) 23 mA IOUT = 0mA, MODE/DATA = VIN, for one converter, VOUT 1.575V (1) 3.6 mA EN1, EN2 = GND, VIN = 3.6V (2) 1.2 3 EN1, EN2 = GND, VIN ramped from 0V to 3.6V (3) 0.1 1 Falling 1.5 2.35 Rising 2.4 mA V ENABLE EN1, EN2 VIH High-level input voltage, EN1, EN2 1.2 VIN V VIL Low-level input voltage, EN1, EN2 0 0.4 V IIN Input bias current, EN1, EN2 1.0 mA EN1, EN2 = GND or VIN 0.05 DEF_1 INPUT VDEF_1H DEF_1 high level input voltage DEF_1 pin is a digital input at TPS62401 fixed output voltage option 0.9 VIN V VDEF_1L DEF_1 low level input voltage DEF_1 pin is a digital input at TPS62401 fixed output voltage option 0 0.4 V IIN Input bias current DEF_1 DEF_1 GND or VIN 1.0 mA 0.01 MODE/DATA VIH High-level input voltage, MODE/DATA 1.2 VIN V VIL Low-level input voltage, MODE/DATA 0 0.4 V IIN Input bias current, MODE/DATA MODE/DATA = GND or VIN VOH Acknowledge output voltage high Open drain, via external pullup resistor VOL Acknowledge output voltage low Open drain, sink current 500mA 0.01 0 1.0 mA VIN V 0.4 V INTERFACE TIMING tStart Start time tH_LB High time low bit, logic 0 detection tL_LB (1) (2) (3) Low time low bit, logic 0 detection 2 Signal level on MODE/DATA pin is > 1.2V Signal level on MODE/DATA pin < 0.4V 2 2x tH_LB ms 200 ms 400 ms Device is switching with no load on the output, L = 3.3mH, value includes losses of the coil These values are valid after the device has been already enabled one time (EN1 or EN2 = high) and supply voltage VIN has not powered down. These values are valid when the device is disabled (EN1 and EN2 low) and supply voltage VIN is powered up. The values remain valid until the device has been enabled first time (EN1 or EN2 = high). After first enable, Note 3 becomes valid. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 3 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.6V, VOUT = 1.8V, EN = VIN, MODE = GND, L = 2.2mH, COUT = 20mF, TA = TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN tL_HB Low time high bit, logic 1 detection Signal level on MODE/DATA pin < 0.4V tH_HB High time high bit, logic 1 detection Signal level on MODE/DATA pin is > 1.2V TEOS End of Stream TEOS tACKN Duration of acknowledge condition (MODE/DATE line pulled low by the device) VIN 2.5V to 6V tvalACK Acknowledge valid time ttimeout Timeout for entering power save mode MAX UNIT 2 TYP 200 ms 2x tL_HB 400 ms 2 ms 400 520 ms 2 ms 520 ms 620 mΩ 1 mA 200 450 mΩ 6 7.5 mA 0.68 0.8 0.92 0.85 1.0 1.15 MODE/DATA Pin changes from high to low POWER SWITCH RDS(ON) P-Channel MOSFET on-resistance, Converter 1,2 VIN = VGS = 3.6V ILK_PMOS P-Channel leakage current VDS = 6.0V RDS(ON) N-Channel MOSFET on-resistance Converter 1,2 VIN = VGS = 3.6V ILK_SW1/SW2 Leakage current into SW1/SW2 pin Includes N-Chanel leakage current, VIN = open, VSW = 6.0V, EN = GND (4) ILIMF Forward Current Limit OUTPUT 1 PMOS and NMOS OUTPUT 2 2.5V ≤ VIN ≤ 6.0V TSD Thermal shutdown Increasing junction temperature 150 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C 280 A OSCILLATOR fSW 2.5V ≤ VIN ≤ 6V Oscillator frequency 2.0 2.25 2.5 MHz OUTPUT VOUT Adjustable output voltage range Vref Reference voltage 0.6 Voltage positioning active, MODE/DATA = GND, device operating in PFM mode, VIN = 2.5V to 5.0V (6) (7) VOUT (PFM) DC output voltage accuracy adjustable and fixed output voltage (5) VOUT(PWM) VIN 600 V mV –1.5% 1.01 VOUT 2.5% MODE/DATA = GND; device operating in PWM Mode, VIN = 2.5V to 6.0V (7) –1% 0% 1% VIN = 2.5V to 6.0V, Mode/Data = VIN , Fixed PWM operation, 0mA < IOUT1 < 400mA ; 0mA < IOUT2 < 600mA (8) –1% 0% 1% DC output voltage load regulation PWM operation mode tStart up Start-up time Activation time to start switching (9) 170 ms tRamp VOUT Ramp UP time Time to ramp from 5% to 95% of VOUT 750 ms (4) (5) (6) (7) (8) (9) 4 0.5 %/A On pins SW1 and SW2 an internal resistor of 1MΩ is connected to GND. Output voltage specification does not include tolerance of external voltage programming resistors Configuration L typ 2.2mH, COUT typ 20mF, see parameter measurement information, the output voltage ripple in PFM mode depends on the effective capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance. In Power Save Mode, PWM operation is typically entered at IPSM = VIN/32Ω. For VOUT > 2V, VIN min = VOUT +0.5V This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 = 1) AND the other converter is already enabled (e.g., EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = low) to active mode (EN1 and/or EN2=1) a value of typ 80 ms for ramp up of internal circuits needs to be added. After tStart the converter starts switching and ramps VOUT. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 PIN ASSIGNMENTS ADJ2 1 MODE/DATA 2 VIN 3 FB1 4 DEF_1 5 e w o P AD rP 10 SW2 9 EN2 8 GND 7 EN1 6 SW1 Top view DRC package TERMINAL FUNCTIONS TERMINAL NAME ADJ2 NO. (QFN) 1 I/O DESCRIPTION I Input to adjust output voltage of converter 2. In adjustable version (TPS62400) connect a external resistor divider between VOUT2, this pin and GND to set output voltage between 0.6V and VIN. At fixed output voltage version (TPS62401) this pin MUST be directly connected to the output. If EasyScale Interface is used for converter 2, this pin must be directly connected to the output, too. This Pin has 2 functions: MODE/DATA 2 I/0 1. Operation Mode selection: With low level, Power Save Mode is enabled where the device operates in PFM mode at light loads and enters automatically PWM mode at heavy loads. Pulling this PIN to high forces the device to operate in PWM mode over the whole load range. 2. EasyScale™ Interface function: One wire serial interface to change the output voltage of both converters. The pin has an open drain output to provide an acknowledge condition if requested. The current into the open drain output stage may not exceed 500mA. The interface is active if either EN1 or EN2 is high. VIN 3 FB1 4 Supply voltage, connect to VBAT, 2.5V to 6V I Direct feedback voltage sense input of converter 1, connect directly to Vout 1. An internal feed forward capacitor is connected between this pin and the error amplifier. In case of fixed output voltage versions or when the Interface is used, this pin is connected to an internal resistor divider network. This pin defines the output voltage of converter 1. The pin acts either as analog input for output voltage setting via external resistors (TPS62400), or digital input to select between two fixed default output voltages (TPS62401, TPS62402, TPS62403, TPS62404). DEF_1 5 I For the TPS62400, an external resistor network needs to be connected to this pin to adjust the default output voltage. Using the fixed output voltage device options this pin selects between two fixed default output voltages, see table ordering information SW1 6 I/O EN1 7 I GND 8 Enable Input for Converter1, active high GND for both converters; connect this pin to the PowerPAD™ EN2 9 I SW2 10 I/O PowerPAD™ Switch Pin of Converter1. Connect to Inductor Enable Input for Converter 2, active high Switch Pin of Converter 2. Connect to Inductor. Connect to GND Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 5 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM VIN PMOS Current Limit Comparator Converter 1 VIN FB_VOUT Thermal Shutdown Softstart VREF +1% Skip Comp. EN1 FB_VOUT VREF- 1% Ext. res. network DEF1 Skip Comp. Low VREF Control Stage Error Amp. Internal FB VOUT1 compensated Int. Resistor Network PWM Comp. Cff 25pF SW1 MODE Register RI 1 Sawtooth Generator DEF1_High RI3 RI..N FB1 Gate Driver GND DEF1_Low Average Current Detector Skip Mode Entry Note 1 NMOS Current Limit Comparator CLK 0° Reference Easy Scale Interface Mode/ DATA ACK MOSFET Open drain Undervoltage Lockout PMOS Current Limit Comparator CLK 180° Converter 2 Int. Resistor Network Load Comparator 2.25MHz Oscillator VIN FB_VOUT VREF +1% Skip Comp. Register FB_VOUT DEF2 Note 2 Cff 25pF VREF- 1% Skip Comp. Low VREF Error Amp. RI 1 Internal compensated RI..N Control Stage Gate Driver PWM Comp. SW2 MODE FB_VOUT2 ADJ2 Thermal Shutdown Softstart Sawtooth Generator CLK 180° GND Average Current Detector Skip Mode Entry NMOS Current Limit Comparator EN2 Load Comparator GND 6 (1) In fixed output voltage version, the PIN DEF_1 is connected to an internal digital input and disconnected from the error amplifier (2) To set the output voltage of Converter 2 via EasyScale™ Interface, ADJ2 pin must be directly connected to VOUT2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 PARAMETER MEASUREMENT INFORMATION TPS62400 VIN 2.5 V – 6 V FB 1 VIN L1 CIN VOUT1 SW1 2.2 mH LSP4018 10 mF R11 COUT1 2x10 mF GRM21BR61A106K DEF_1 R12 EN_1 L2 EN_2 VOUT2 SW2 2.2 mH LSP4018 MODE/ DATA R21 C ff2 33 pF ADJ2 COUT2 2x10 mF GRM21BR61A106K R22 GND TYPICAL CHARACTERISTICS TABLE OF GRAPHS AND FIGURES FIGURE NO. Efficiency TPS62401 VOUT1 = 1.1V 1 Efficiency TPS62401 VOUT1 = 1.575V 2 Efficiency VOUT 2 = 1.8V 3 Efficiency TPS62400 VOUT2 = 3.3V 4 Efficiency TPS62402 5 Efficiency TPS62403 6 Efficiency vs VIN 7,8 DC Output Accuracy VOUT1 = 1.1V 9 DC Output Accuracy VOUT2 = 3.3V 10 DC Output Accuracy VOUT2 = 1.8V 11 DC Output Accuracy VOUT1 1.575V, L = 2.2mH, COUT = 22mF 12 DC Output Accuracy VOUT1 1.575V, L = 3.3mH, COUT = 10mF 13 FOSC vs VIN 14 Iq for one converter 15 Iq for both converters, not switching 16 RDSON PMOS vs VIN 17 RDSON NMOS vs VIN 18 Light Load Output Voltage Ripple in Power Save Mode 19 Output Voltage Ripple in Forced PWM Mode 20 Output Voltage Ripple in PWM Mode 21 Forced PWM/ PFM Mode Transition 22 Load Transient Response PFM/PWM 23 Load Transient Response PWM Operation 24 Line Transient Response 25 Startup Timing One Converter 26 TPS62401 DEF1_pin Function for Output Voltage Selection 27 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 7 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) FIGURE NO. Typical Operation VIN = 3.6V, VOUT1 = 1.575V, VOUT2 = 1.8V 28 Typical Operation VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 3.0V 29 Typical Operation VIN = 3.6V, VOUT1 = 1.2V, VOUT2 = 1.2V 30 VOUT1 Change With EasyScale 31 Dynamic Voltage Positioning 32 Soft Start 33 EasyScale™ Protocol Overview 34 EasyScale Protocol Without Acknowledge 35 EasyScale Protocol Including Acknowledge 36 EasyScale – Bit Coding 37 MODE/DATA PIN: Mode Selection 38 MODE/DATA Pin: Power Save Mode / Interface Communication 39 Typical Application Circuit 1.5V / 2.85V Adjustable Outputs, low PFM voltage ripple optimized 40 Typical Application Circuit 1.5V / 2.85V Adjustable Outputs 41 TPS62401 Fixed 1.575V/1.8 V Outputs, low PFM voltage ripple optimized 42 TPS62401 Fixed 1.1V/1.8 V Outputs, low PFM voltage ripple optimized 43 TPS62401 Fixed 1.575V/1.8 V Outputs 44 Dynamic Voltage Scaling on Vout1 Controlled by DEF_1 pin 45 TPS62403 1.575V/2.8V Outputs 46 Layout Diagram 47 PCB Layout 48 EFFICIENCY TPS62401 VOUT1 = 1.1V 100 VOUT1 = 1.1 V VOUT1 = 1.575 V 90 90 80 80 70 VIN = 2.7 V VIN = 2.7 V 60 VIN = 3.6 V 50 VIN = 3.6 V VIN = 5 V VIN = 5 V 40 Power Save Mode MODE/DATA = 0 30 Efficiency % 70 Efficiency % EFFICIENCY TPS62401 VOUT1 = 1.575V 100 20 10 10 0 0.01 0.1 1 10 100 1000 0 0.01 VIN = 5 V Power Save Mode MODE/DATA = 0 0.1 IOUT mA 1 Forced PWM Mode MODE/DATA = 1 10 100 1000 IOUT mA Figure 1. 8 VIN = 3.6 V VIN = 5 V 40 20 VIN = 2.7 V VIN = 3.6 V 50 30 Forced PWM Mode MODE/DATA = 1 VIN = 2.7 V 60 Figure 2. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 EFFICIENCY VOUT 2 = 1.8V EFFICIENCY TPS62400 VOUT 2 = 3.3V 100 100 90 VOUT2 = 1.8 V 90 80 80 VIN = 2.7 V 60 VIN = 3.6 V VIN = 3.6 V 50 VIN = 5 V VIN = 5 V 40 Power Save Mode MODE/DATA = 0 Forced PWM Mode MODE/DATA = 1 VIN = 5 V 50 40 10 10 1 10 100 0 0.01 1000 Forced PWM Mode MODE/DATA = 1 Power Save Mode MODE/DATA = 0 30 20 0.1 VIN = 5 V 60 20 0 0.01 VIN = 3.6 V VIN = 3.6 V 70 VIN = 2.7 V Efficiency % Efficiency % 70 30 VOUT2 = 3.3 V 0.1 1 10 IOUT mA Figure 3. 90 EFFICIENCY TPS62403 VOUT1/VOUT2 100 VI = 3.7 V VI = 4.2 V VO2 = 3.3 V MODE/DATA = Low 90 80 80 VI = 3.7 V VI = 4.2 V VO1 = 1.8 V MODE/DATA = Low 60 40 30 20 VI = 3.7 V VI = 4.2 V VO2 = 1.8 V MODE/DATA = High VI = 3.7 V VI = 4.2 V VO1 = 1.2 V MODE/DATA = Low 50 VI = 3.7 V VI = 4.2 V VO2 = 1.2 V MODE/DATA = High VI = 3.7 V VI = 4.2 V VO2 = 3.3 V MODE/DATA = High 0.1 60 VOUT2 = 2.8 V VIN = 3.3 V VIN = 3.6 V MODE/DATA = high TPS62403 Efficiency VOUT1/VOUT2, MODE/DATA = 0, DEF_1 = 0 50 40 30 VOUT1 = 1.575 V VIN = 3.3 V VIN = 3.6 V MODE/DATA = low 20 VOUT1 = 1.575 V VIN = 3.3 V VIN = 3.6 V MODE/DATA = high 10 10 0 0.01 VOUT2 = 2.8 V VIN = 3.3 V VIN = 3.6 V MODE/DATA = low 70 Efficiency - % Efficiency - % 70 1000 Figure 4. EFFICIENCY TPS62402 VOUT1/VOUT2 100 100 IOUT mA 1 10 100 1000 0 0.01 IO - Output Current - mA Figure 5. 0.1 1 10 IOUT - mA 100 1000 Figure 6. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 9 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com EFFICIENCY vs VIN EFFICIENCY vs VIN 100 100 MODE/DATA = 0 VOUT = 1.575 V 95 90 90 IOUT = 10 mA 80 IOUT = 1 mA Efficiency % 85 Efficiency % MODE/DATA = 0 VOUT = 3.3 V IOUT = 100 mA IOUT = 10 mA IOUT = 200 mA 75 70 IOUT = 1 mA 80 70 65 60 60 55 50 50 2 3 4 5 6 3 4 5 6 VIN - V VIN - V Figure 7. Figure 8. DC OUTPUT ACCURACY VOUT1 = 1.1V DC OUTPUT ACCURACY VOUT2 = 3.3V 3.400 1.150 VOUT2 = 3.3V VOUT1 = 1.1 V MODE/DATA = low, PFM Mode, voltage positioning active VIN = 4.2 V 1.125 MODE/DATA = low, PFM Mode, voltage positioning active VIN = 5 V 3.350 PWM Mode PWM Mode Operation VIN = 2.7 V VIN = 3.6 V VIN = 2.7 V VIN = 3.6 V VOUT DC - V VOUT DC - V Operation 1.100 VIN = 4.2 V MODE/DATA = high, forced PWM Mode 3.300 VIN = 3.6 V VIN = 5 V MODE/DATA = high, forced PWM Mode 0.10 1 10 100 1000 3.200 0.01 IOUT - mA Figure 9. 10 VIN = 4.2 V 3.250 1.075 1.050 0.01 VIN = 4.2 V VIN = 3.6 V 0.10 1 10 100 1000 IOUT - mA Figure 10. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 DC OUTPUT ACCURACY VOUT1 = 1.575V, L = 2.2mH, COUT = 22mF DC OUTPUT ACCURACY VOUT2 = 1.8V 1.854 1.836 1.650 VOUT2 = 1.8 V VOUT1 = 1.575 V MODE/DATA = low, PFM Mode, voltage positioning active MODE/DATA = low, PFM Mode, voltage positioning active 1.625 VIN = 4.2 V VOUT DC - V 1.818 VIN = 5 V V = 4.2 V V = 3.6 V IN IN VIN = 2.7 V 1.800 VIN = 3.6 V VIN = 2.7 V VOUT DC - V PWM Mode Operation VIN = 4.2 V VIN = 5 V MODE/DATA = high, forced PWM Mode 1.782 1.575 VIN = 2.7 V 0.10 1 10 100 1.500 0.01 1000 0.10 100 1 10 IOUT - mA 1000 Figure 12. DC OUTPUT ACCURACY VOUT1 = 1.575V, L = 3.3mH, COUT = 10mF FOSC vs VIN 2.5 VOUT1 = 1.575 V 2.45 MODE/DATA = low, PFM Mode, voltage positioning active 1.625 2.4 VIN = 4.2 V PWM Mode Operation 1.600 VIN = 2.7 V VIN = 3.6 V 1.575 VIN = 2.7 V VIN = 3.6 V VIN = 4.2 V 2.35 Fosc - MHz VOUT DC - V VIN = 4.2 V 1.525 Figure 11. 1.550 VIN = 3.6 V MODE/DATA = high, forced PWM Mode IOUT - mA 1.650 VIN = 3.6 V VIN = 2.7 V 1.550 1.764 1.746 0.01 PWM Mode Operation 1.600 2.3 -40°C 2.25 2.2 MODE/DATA = high, forced PWM Mode 25°C 2.15 2.1 1.525 85°C 2.05 1.500 0.01 0.10 1 10 IOUT - mA 100 1000 2 2.5 3 Figure 13. 3.5 4 4.5 VIN - V 5 5.5 6 Figure 14. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 11 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com Iq FOR ONE CONVERTER, NOT SWITCHING Iq FOR BOTH CONVERTERS, NOT SWITCHING 24 42 23 40 85°C 22 38 Iddq - mA Iddq - mA 85°C 25°C 21 20 36 25°C 34 -40°C 19 32 18 30 17 -40°C 28 2.5 3 3.5 4 4.5 VIN - V 5 5.5 6 2.5 3 3.5 4 4.5 5 5.5 6 VIN - V Figure 15. Figure 16. RDSON PMOS vs VIN RDSON NMOS vs VIN 0.55 0.3 0.5 0.25 0.45 RDSon - W RDSon - W 0.4 85°C 0.35 25°C 0.3 0.2 85°C 25°C 0.15 -40°C 0.25 0.1 -40°C 0.2 0.15 2.5 3 3.5 4 4.5 5 5.5 6 0.05 2.5 3 VIN - V 4 4.5 5 5.5 6 VIN - V Figure 17. 12 3.5 Figure 18. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 LIGHT LOAD OUTPUT VOLTAGE RIPPLE IN POWER SAVE MODE Power Save Mode Mode/Data = low IOUT = 10mA OUTPUT VOLTAGE RIPPLE IN FORCED PWM MODE Mode/Data = high, forced PWM MODE operation IOUT = 10mA VOUT = 1.8V 20mV/Div VOUT = 1.8V 20mV/Div Inductor current 100mA/Div Inductor current 100mA/Div Time base - 400 ns/Div Time base - 10 ms/Div Figure 19. Figure 20. OUTPUT VOLTAGE RIPPLE IN PWM MODE FORCED PWM/PFM MODE TRANSITION PWM MODE OPERATION VOUT = 1.8V IOUT = 400mA VOUT ripple 20mV/Div Forced PWM Mode MODE/DATA 1V/Div Enable Power Save Mode Entering PFM Mode Voltage positioning active VOUT 20mV/Div Inductor current 200mA/Div VOUT = 1.8V IOUT = 20mA Time base - 200 ms/Div Time base - 200 ns/Div Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 13 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com LOAD TRANSIENT RESPONSE PFM/PWM VOUT = 1.575V 50mV/Div MODE/DATA = low Voltage positioning in PFM Mode reduces voltage drop during load step LOAD TRANSIENT RESPONSE PWM OPERATION MODE/DATA = high PWM Mode operation VOUT = 1.575V 50mV/Div PWM Mode operation IOUT 200mA/Div IOUT 200mA/Div IOUT1 = 360mA IOUT1 = 360mA IOUT= 40mA IOUT= 40mA Time base - 50 ms/Div Time base - 50 ms/Div Figure 23. Figure 24. LINE TRANSIENT RESPONSE STARTUP TIMING ONE CONVERTER VIN 3.6V to 4.6V VIN 1V/Div MODE/DATA = high EN1 / EN2 5V/Div VIN = 3.8V IOUT1 max = 400mA VOUT1 500mV/Div VOUT 1.575 IOUT 200mA SW1 1V/Div VOUT 50mV/Div Icoil 500mA/Div 14 Time base - 400 ms/Div Time base - 200 ms/Div Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 TPS62401DEF1_PIN FUNCTION FOR OUTPUT VOLTAGE SELECTION TYPICAL OPERATION VIN = 3.6V, VOUT1 = 1.575V, VOUT2 = 1.8V VIN = 3.6V, MODE/DAT = low IOUT1 = 40mA DEF_1 pin 2V/Div SW1 5V/Div VOUT1 = 1.575V I coil1 200mA/Div VOUT1 500mV/Div VOUT1 = 1.1V SW2 5V/Div Icoil2 200mA/Div Icoil 500mA/Div VIN 3.6V, VOUT1: 1.575V VOUT2: 1.8V I OUT1 = IOUT2 = 200mA Time base - 100 ms/Div Time base - 100 ns/Div Figure 27. Figure 28. TYPICAL OPERATION VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 3.0V TYPICAL OPERATION VIN = 3.6V, VOUT1 = 1.2V, VOUT2 = 1.2V SW1 5V/Div SW1 5V/Div I coil1 200mA/Div I coil1 200mA/Div SW2 5V/Div SW2 5V/Div Icoil2 200mA/Div VIN 3.6V, VOUT1 : 1.8V VOUT2 : 3.0V I OUT1 = I OUT2 = 200mA I coil2 200mA/Div VIN 3.6V, VOUT1 : 1.2V VOUT2 : 1.2V I OUT1 = I OUT2 = 200mA Time base - 100 ns/Div Time base - 100 ns/Div Figure 29. Figure 30. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 15 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com VOUT1 CHANGE WITH EASYSCALE MODE/DATA 2V/Div VOUT1 : 200mV/Div VOUT1: 1.1V VOUT1 : 1.5V VIN 3.8V ACKN = off IOUT1 = 150mA REG_DEF_1_Low Time base - 100 ms/Div Figure 31. DETAILED DESCRIPTION OPERATION The TPS62400 includes two synchronous step-down converters. The converters operate with typically 2.25MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If Power Safe Mode is enabled, the converters automatically enter Power Save Mode at light load currents and operate in PFM (Pulse Frequency Modulation). During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit. The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and converter 2 decreases the input RMS current. Converter 1 In the adjustable output voltage version TPS62400 the converter 1 default output voltage can be set via an external resistor network on PIN DEF_1, which operates as an analog input. In this case, the output voltage can be set in the range of 0.6V to VIN V. The FB1 Pin must be directly connected to the converter 1 output voltage VOUT1. It feeds back the output voltage directly to the regulation loop. The output voltage of converter 1 can also be changed by the EasyScale™ serial Interface. This makes the device very flexible for output voltage adjustment. In this case, the device uses an internal resistor network. In the fixed default output voltage version TPS62401, the DEF_1 Pin is configured as a digital input. The converter 1 defaults to 1.1V or 1.575V depending on the level of DEF_1 pin. If DEF_1 is low the default is 1.575V; if high, the default is 1.1V. With the EasyScale™ interface, the output voltage for each DEF_1 Pin condition (high or low) can be changed. 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 Converter 2 In the adjustable output voltage version TPS62400, the converter 2 output voltage is set by an external resistor divider connected to ADJ2 Pin and uses an external feed forward capacitor of 33pF. In fixed output voltage version TPS62401, the default output voltage is fixed to 1.8V. In this case, the ADJ2 pin must be connected directly to the converter 2 output voltage VOUT2. It is also possible to change the output voltage of converter 2 via the EasyScale™ Interface. In this case, the ADJ2 Pin must be directly connected to converter 2 output voltage VOUT2 and no external resistors may be connected. POWER SAVE MODE The Power Save Mode is enabled with Mode/Data Pin set to low for both converters. If the load current of a converter decreases, this converter will enter Power Save Mode operation automatically. The transition to Power Save Mode of a converter is independent from the operating condition of the other converter. During Power Save Mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter will position the output voltage in PFM mode to typically 1.01×VOUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step. In order to optimize the converter efficiency at light load the average inductor current is monitored. The device changes from PWM Mode to Power Save Mode, if in PWM mode the inductor current falls below a certain threshold. The typical output current threshold depends on VIN and can be calculated according to Equation 1 for each converter. Equation 1: Average output current threshold to enter PFM Mode VINDCDC I OUT_PFM_enter + 32 W (1) Equation 2: Average output current threshold to leave PFM Mode VINDCDC I OUT_PFM_leave + 24 W (2) In order to keep the output voltage ripple in Power Save Mode low, the output voltage is monitored with a single threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip comp) of 1.01 x VOUTnominal, the corresponding converter starts switching for a minimum time period of typ. 1ms and provides current to the load and the output capacitor. Therefore the output voltage will increase and the device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this moment all switching activity is stopped and the quiescent current is reduced to minimum. The load is supplied by the output capacitor until the output voltage has dropped below the threshold again. Hereupon the device starts switching again. The Power Save Mode is left and PWM Mode entered in case the output current exceeds the current IOUT_PFM_leave or if the output voltage falls below a second comparator threshold, called skip comparator low (Skip Comp Low) threshold. This skip comparator low threshold is set to -2% below nominal Vout, and enables a fast transition from Power Save Mode to PWM Mode during a load step. In Power Save Mode the quiescent current is reduced typically to 19mA for one converter and 32mA for both converters active. This single skip comparator threshold method in Power Save Mode results in a very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing output capacitor values will minimize the output ripple. The Power Save Mode can be disabled through the MODE/DATA pin set to high. Both converters will then operate in fixed PWM mode. Power Save Mode Enable/Disable applies to both converters. Dynamic Voltage Positioning This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is activated in Power Save Mode operation. It provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. This improves load transient behavior. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 17 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com At light loads, in which the converter operates in PFM Mode, the output voltage is regulated typically 1% higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch. Smooth increased load +1% Fast load transient PFM Mode light load PFM Mode light load VOUT_NOM PWM Mode medium/heavy load PWM Mode medium/heavy load PWM Mode medium/heavy load COMP_LOW threshold -2% Figure 32. Dynamic Voltage Positioning Soft Start The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 33. EN 95% 5% VOUT t Startup tRAMP Figure 33. Soft Start 100% Duty Cycle Low Dropout Operation The converters offer a low input-to-output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: Vin min + Vout max ) Iout max ǒRDSonmax ) R LǓ (3) with: Ioutmax = maximum output current plus inductor ripple current RDSonmax = maximum P-channel switch RDSon. RL = DC resistance of the inductor Voutmax = nominal output voltage plus maximum output voltage tolerance 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 With decreasing load current, the device automatically switches into pulse skipping operation in which the power stage operates intermittently based on load demand. By running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current, maintaining high efficiency. Under-Voltage Lockout The under-voltage lockout circuit prevents the device from malfunctioning at low input voltages, and from excessive discharge of the battery, and disables the converters. The under-voltage lockout threshold is typically 1.5V; maximum of 2.35V. In case the default register values are overwritten by the Interface, the new values in the registers REG_DEF_1_High, REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall below the under-voltage lockout threshold, independent of whether the converters are disabled. MODE SELECTION The MODE/DATA pin allows mode selection between forced PWM Mode and Power Save Mode for both converters. Furthermore, this pin is a multipurpose pin and provides (besides Mode selection) a one-pin interface to receive serial data from a host to set the output voltage. This is described in the EasyScale™ Interface section. Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters operates in fixed-frequency PWM mode at moderate-to-heavy loads, and in the PFM mode during light loads, maintaining high efficiency over a wide load current range. Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode, even at light load currents. The advantage is that the converters operate with a fixed frequency, allowing simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads. For additional flexibility, it is possible to switch from power save mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements. In case the operation mode is changed from forced PWM mode (MODE/DATA = high) to Power Save Mode Enable (MODE/DATA = 0), the Power Save Mode is enabled after a delay time of ttimeout , which is max. 520ms. The forced PWM Mode operation is enabled immediately with Pin MODE/DATA set to 1. ENABLE The device has a separate EN pin for each converter to start up each converter independently. If EN1 and EN2 are set to high, the corresponding converter starts up with soft start as previously described. Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2mA. In this mode, the P and N-Channel MOSFETs are turned-off and the entire internal control circuitry is switched-off. For proper operation the EN1 and EN2 pins must be terminated and must not be left floating. DEF_1 PIN FUNCTION The DEF_1 pin is dedicated to converter 1 and makes the output voltage selection very flexible to support dynamic voltage management. Depending on the device version, this pin works either as: 1. Analog input for adjustable output voltage setting (TPS62400): – Connecting an external resistor network to this pin adjusts the default output voltage to any value starting from 0.6V to VIN 2. Digital input for fixed default output voltage selection (TPS62401): – In case this pin is tied to low level, the output voltage is set according to the value in register REG_DEF_1_Low. The default voltage will be 1.575V. If tied to high level, the output voltage is set according to the value in register REG_DEF_1_High. The default value in this case is 1.1V. Depending on the level of Pin DEF_1, it selects between the two registers REG_DEF_1_Low and REG_DEF_1_High for output voltage setting. Each register content (and therefore output voltage) can be changed individually via the EasyScale™ interface. This makes the device very flexible in terms of output voltage setting; see Table 4. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 19 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com 180° OUT-OF-PHASE OPERATION In PWM Mode the converters operate with a 180° turn-on phase shift of the PMOS (high side) transistors. This prevents the high-side switches of both converters from being turned on simultaneously, and therefore smooths the input current. This feature reduces the surge current drawn from the supply. SHORT-CIRCUIT PROTECTION Both outputs are short-circuit protected with maximum output current = ILIMF(P-MOS and N-MOS). Once the PMOS switch reaches its current limit, it is turned off and the NMOS switch is turned on. The PMOS only turns on again, once the current in the NMOS decreases below the NMOS current limit. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis. EasyScale™: One-Pin Serial Interface for Dynamic Output Voltage Adjustment General EasyScale is a simple but very flexible one pin interface to configure the output voltage of both DC/DC converters. The interface is based on a master – slave structure, where the master is typically a microcontroller or application processor. Figure 34 and Table 3. give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byte consists of five bits for information, two address bits, and the RFA bit. RFA bit set to high indicates the Request For Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale™ compared to other one pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to 160kBit/sec. Furthermore, the interface is shared with the Mode/Data Pin and requires no additional pin. Protocol All bits are transmitted MSB first and LSB last. Figure 35 shows the protocol without acknowledge request (bit RFA = 0), Figure 36 with acknowledge (bit RFA = 1) request. Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the Mode/Data pin need be pulled high for at least tStart before the bit transmission starts with the falling edge. In case the Mode/Data line was already at high level (forced PWM Mode selection), no start condition need be applied prior the device address byte. The transmission of each byte needs to be closed with an End Of Stream condition for at least TEOS. Addressable Registers Three registers with a data content of 5 bits can be addressed. With 5 bit data content, 32 different values for each register are available. Table 1 shows the addressable registers to set the output voltage when DEF_1 pin works as digital input. In this case, converter 1 has a related register for each DEF_1 Pin condition, and one register for converter 2. With a high/low condition on pin DEF_1 (TPS62401) either the content of register REG_DEF_1_high/REG_DEF1_low is selected. The output voltage of converter 1 is set according to the values in Table 4. Table 2 shows the addressable registers if DEF_1 pin acts as analog input with external resistors connected. In this case one register is available for each converter. The output voltage of converter 1 is set according to the values in Table 5. For converter 2, the available voltages are shown in Table 6. To generate these output voltages a precise internal resistor divider network is used, making external resistors unnecessary (less board space), and provides higher output voltage accuracy. The Interface is activated if at least one of the converters is enabled (EN1 or EN2 is high). After the startup-time tStart (170ms) the interface is ready for data reception. 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 Table 1. Addressable Registers for default Fixed Output Voltage Options (PIN DEF_1 = digital input) DEVICE REGISTER TPS62401, TPS62402, TPS62403, TPS62404 DESCRIPTION DEF_1 PIN A1 A0 D4 D3 D2 D1 REG_DEF_1_High Converter 1 output voltage setting for DEF_1 = High condition. The content of the register is active with DEF1_ Pin high. High 0 1 Output voltage setting, see Table 4 REG_DEF_1_Low Converter 1 output voltage setting for DEF_1 = Low condition. Low 0 0 Output voltage setting, see Table 4 REG_DEF_2 Converter 2 output voltage Not applicable 1 0 Output voltage setting, see Table 6 1 1 Don’t use D0 Table 2. Addressable Registers for Adjustable Output Voltage Options (PIN DEF_1 = analog input) DEVICE TPS62400 REGISTER DESCRIPTION A1 A0 Converter 1 output voltage setting 0 0 see Table 5 Converter 2 output voltage 1 0 see Table 6 Don’t’ use 1 1 REG_DEF_1_High not available REG_DEF_1_Low REG_DEF_2 D4 D3 D2 D1 D0 Bit Decoding The bit detection is based on a PWM scheme, where the criterion is the relation between tLOW and tHIGH. It can be simplified to: High Bit: tHigh > tLow, but with tHigh at least 2x tLow, see Figure 34 Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 34 The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge. Depending on the relation between tLow and tHigh a 0 or 1 is detected. Acknowledge The Acknowledge condition is only applied if: • Acknowledge is requested by a set RFA bit • The transmitted device address matches with the device address of the device • 16 bits were received correctly In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time tACKN, which is 520ms maximum . The Acknowledge condition is valid after an internal delay time tvalACK. This means the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master controller keeps the line low during this time. The master device can detect the acknowledge condition with its input by releasing the MODE/DATA pin after tvalACK and read back a 0. In case of an invalid device address, or not-correctly-received protocol, no-acknowledge condition is applied; thus, the internal MOSFET is not turned on and the external pullup resistor pulls MODE/DATA pin high after tvalACK. The MODE/DATA pin can be used again after the acknowledge condition ends. NOTE The acknowledge condition may only be requested in case the master device has an open drain output. In case of a push-pull output stage it is recommended to use a series resistor in the MODE/DATA line to limit the current to 500 mA in case of an accidentally requested acknowledge, to protect the internal ACKN-MOSFET. MODE Selection Because the MODE/DATA pin is used for two functions, interface and a MODE selection, the device needs to determine when it has to decode the bit stream or to change the operation mode. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 21 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level. The device also stays in forced PWM mode during the entire protocol reception time. With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for at least ttimeout, the device gets an internal timeout and Power Save Mode operation is enabled. A protocol sent within this time is ignored because the falling edge for the Mode change is first interpreted as start of the first bit. In this case it is recommended to send the protocol first, and then change at the end of the protocol to Power Save Mode. DATA IN Start Start Device Address DA7 DA6 DA5 DA4 0 1 0 0 DATABYTE DA3 DA2 DA1 1 1 1 DA0 EOS Start RFA 0 A1 A0 D4 D3 D2 D1 D0 EOS DATA OUT ACK Figure 34. EasyScale™ Protocol Overview Table 3. EasyScale™ Bit Description BYTE BIT NUMBER NAME TRANSMISSION DIRECTION Device Address Byte 7 DA7 IN 0 MSB device address 6 DA6 IN 1 5 DA5 IN 0 4 DA4 IN 0 3 DA3 IN 1 2 DA2 IN 1 1 DA1 IN 1 4Ehex Databyte DESCRIPTION 0 DA0 IN 0 LSB device address 7(MSB) RFA IN Request For Acknowledge, if high, Acknowledge condition will applied by the device 6 A1 Address Bit 1 5 A0 Address Bit 0 4 D4 Data Bit 4 3 D3 Data Bit 3 2 D2 Data Bit 2 1 D1 Data Bit 1 0(LSB) D0 Data Bit 0 ACK OUT Acknowledge condition active 0, this condition will only be applied in case RFA bit is set. Open drain output, Line needs to be pulled high by the host with a pullup resistor. This feature can only be used if the master has an open drain output stage. In case of a push pull output stage Acknowledge condition may not be requested! tStart DATA IN tStart Address Byte DATA Byte Mode, Static High or Low Mode, Static High or Low DA7 0 DA0 0 TEOS RFA 0 D0 1 TEOS Figure 35. EasyScale™ Protocol Without Acknowledge 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 tStart tStart Address Byte DATA Byte Mode, Static High or Low Mode, Static High or Low DATA IN DA7 0 DA0 0 D0 1 RFA 1 T EOS tvalACK ACKN tACKN Controller needs to Pullup Data Line via a resistor to detect ACKN DATA OUT Acknowledge true, Data Line pulled down by device Acknowledge false, no pull down Figure 36. EasyScale™ Protocol Including Acknowledge t Low tHigh t Low t High Low Bit High Bit (Logic 0) (Logic 1) Figure 37. EasyScale™ – Bit Coding MODE/DATA ttimeout Power Save Mode Forced PWM MODE Power Save Mode Figure 38. MODE/DATA PIN: Mode Selection tStart Address Byte tStart DATA Byte MODE/DATA TEOS TEOS t timeout Power Save Mode Forced PWM MODE Power Save Mode Figure 39. MODE/DATA Pin: Power Save Mode/Interface Communication Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 23 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com Table 4. Selectable Output Voltages for Converter 1, With Pin DEF_1 as Digital Input (TPS62401) TPS62401 OUTPUT VOLTAGE [V] REGISTER REG_DEF_1_LOW 24 TPS62401 OUTPUT VOLTAGE [V] REGISTER REG_DEF_1_HIGH D4 D3 D2 D1 D0 0 0.8 0.9 0 0 0 0 0 1 0.825 0.925 0 0 0 0 1 2 0.85 0.95 0 0 0 1 0 3 0.875 0.975 0 0 0 1 1 4 0.9 1.0 0 0 1 0 0 5 0.925 1.025 0 0 1 0 1 6 0.95 1.050 0 0 1 1 0 7 0.975 1.075 0 0 1 1 1 8 1.0 1.1(default TPS62401, TPS62403) 0 1 0 0 0 9 1.025 1.125 0 1 0 0 1 10 1.050 1.150 0 1 0 1 0 11 1.075 1.175 0 1 0 1 1 12 1.1 1.2 0 1 1 0 0 13 1.125 1.225 0 1 1 0 1 14 1.150 1.25 0 1 1 1 0 15 1.175 1.275 0 1 1 1 1 16 1.2 (default TPS62402) 1.3 1 0 0 0 0 17 1.225 1.325 1 0 0 0 1 18 1.25 1.350 1 0 0 1 0 19 1.275 1.375 1 0 0 1 1 20 1.3 1.4 1 0 1 0 0 21 1.325 1.425 1 0 1 0 1 22 1.350 1.450 1 0 1 1 0 23 1.375 1.475 1 0 1 1 1 24 1.4 1.5 1 1 0 0 0 25 1.425 1.525 1 1 0 0 1 26 1.450 1.55 1 1 0 1 0 27 1.475 1.575 1 1 0 1 1 28 1.5 1.6 1 1 1 0 0 29 1.525 1.7 1 1 1 0 1 30 1.55 1.8 (default TPS62402) 1 1 1 1 0 31 1.575 (default TPS62401, TPS62403, TPS62404) 1.9 (default TPS624024) 1 1 1 1 1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 Table 5. Selectable Output Voltages for Converter 1, With DEF1 Pin as Analog Input (Adjustable, TPS62400) 0 TPS62400 OUTPUT VOLTAGE [V] REGISTER REG_DEF_1_LOW D4 D3 D2 D1 D0 VOUT1 Adjustable with Resistor Network on DEF_1 Pin (default TPS62400) 0 0 0 0 0 0.6V with DEF_1 connected to VOUT1 (default TPS62400) 1 0.825 0 0 0 0 1 2 0.85 0 0 0 1 0 3 0.875 0 0 0 1 1 4 0.9 0 0 1 0 0 5 0.925 0 0 1 0 1 6 0.95 0 0 1 1 0 7 0.975 0 0 1 1 1 8 1.0 0 1 0 0 0 9 1.025 0 1 0 0 1 10 1.050 0 1 0 1 0 11 1.075 0 1 0 1 1 12 1.1 0 1 1 0 0 13 1.125 0 1 1 0 1 14 1.150 0 1 1 1 0 15 1.175 0 1 1 1 1 16 1.2 1 0 0 0 0 17 1.225 1 0 0 0 1 18 1.25 1 0 0 1 0 19 1.275 1 0 0 1 1 20 1.3 1 0 1 0 0 21 1.325 1 0 1 0 1 22 1.350 1 0 1 1 0 23 1.375 1 0 1 1 1 24 1.4 1 1 0 0 0 25 1.425 1 1 0 0 1 26 1.450 1 1 0 1 0 27 1.475 1 1 0 1 1 28 1.5 1 1 1 0 0 29 1.525 1 1 1 0 1 30 1.55 1 1 1 1 0 31 1.575 1 1 1 1 1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 25 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com Table 6. Selectable Output Voltages for Converter 2, (ADJ2 Connected to VOUT) OUTPUT VOLTAGE [V] FOR REGISTER REG_DEF_2 D4 D3 D2 D1 D0 VOUT2 Adjustable with resistor network and Cff on ADJ2 pin (default TPS62400) 0 0 0 0 0 0.85 0 0 0 0 1 2 0.9 0 0 0 1 0 3 0.95 0 0 0 1 1 4 1.0 0 0 1 0 0 5 1.05 0 0 1 0 1 6 1.1 0 0 1 1 0 7 1.15 0 0 1 1 1 8 1.2 0 1 0 0 0 0 0.6V with ADJ2 pin directly connected to VOUT2 (default TPS62400) 1 26 9 1.25 0 1 0 0 1 10 1.3 0 1 0 1 0 11 1.35 0 1 0 1 1 12 1.4 0 1 1 0 0 13 1.45 0 1 1 0 1 14 1.5 0 1 1 1 0 15 1.55 0 1 1 1 1 16 1.6 1 0 0 0 0 17 1.7 1 0 0 0 1 18 1.8 (default TPS62401) 1 0 0 1 0 19 1.85 1 0 0 1 1 20 2.0 1 0 1 0 0 21 2.1 1 0 1 0 1 22 2.2 1 0 1 1 0 23 2.3 1 0 1 1 1 24 2.4 1 1 0 0 0 25 2.5 1 1 0 0 1 26 2.6 1 1 0 1 0 27 2.7 1 1 0 1 1 28 2.8 (default TPS62403) 1 1 1 0 0 29 2.85 1 1 1 0 1 30 3.0 1 1 1 1 0 31 3.3 (default TPS62402, TPS62404) 1 1 1 1 1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 APPLICATION INFORMATION OUTPUT VOLTAGE SETTING Converter1 Adjustable Default Output Voltage Setting: TPS62400 The output voltage can be calculated to: V OUT + VREF ǒ R 1 ) 11 R 12 Ǔ with an internal reference voltage VREF typical 0.6V (4) To keep the operating current to a minimum, it is recommended to select R12 within a range of 180kΩ to 360kΩ. The sum of R12 and R11 should not exceed ~1MΩ. For higher output voltages than 3.3V, it is recommended to choose lower values than 180kΩ for R12. Route the DEF_1 line away from noise sources, such as the inductor or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. A feedforward capacitor is not necessary. Converter1 Fixed Default Output Voltage Setting (TPS62401, TPS62402, TPS62403, TPS62404). The output voltage VOUT1 is selected with DEF_1 pin. Pin DEF_1 = low: TPS62401, TPS62403, TPS62404 = 1.575V TPS62402 = 1.2V Pin DEF_1 = high: TPS62401, TPS62403 = 1.1V TPS62402: = 1.8V TPS62404: = 1.9V Converter 2 Adjustable Default Output Voltage Setting TPS62400: The output voltage of converter 2 can be set by an external resistor network. For converter 2 the same recommendations apply as for converter1. In addition to that, a 33pF feedforward Capacitor Cff2 for good load transient response should be used. The output voltage can be calculated to: V OUT + VREF ǒ R 1 ) 21 R 22 Ǔ with an internal reference voltage VREF typical 0.6V (5) Converter 2 Fixed Default Output Voltage Setting ADJ2 pin must be directly connected with VOUT2 TPS62401, VOUT2 default = 1.8V TPS62403, VOUT2 default = 2.8V TPS62402, VOUT2 default = 3.3V TPS62404, VOUT2 default = 3.3V Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 27 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com TPS62400 VIN 3.3 V – 6 V FB 1 VIN SW1 CIN 10 mF L1 2.2 mH VOUT1 = 1.5 V R11 270 kW DEF_1 R12 180 kW IOUT1 up to 400 mA COUT1 22 mF EN_1 L2 EN_2 VOUT2 = 2.85 V SW2 3.3 mH MODE/ DATA C ff2 R21 825 kW 33 pF ADJ2 R22 220 kW IOUT2 up to 600 mA COUT2 22 mF GND Figure 40. Typical Application Circuit 1.5V/2.85V Adjustable Outputs, low PFM Voltage Ripple Optimized TPS62400 VIN 3.3 V – 6 V VIN CIN FB 1 L1 SW1 10 mF 2.2 mH VOUT1 = 1.5 V R11 270 kW COUT1 10 mF DEF_1 R12 180 kW EN_1 EN_2 L2 VOUT2 = 2.85 SW2 3.3 mH MODE/ DATA IOUT1 up to 400 mA ADJ2 C ff2 R21 825 kW 33 pF IOUT2 up to 600 mA COUT2 10 mF R22 220 kW GND Figure 41. Typical Application Circuit 1.5V/2.85V Adjustable Outputs 28 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 TPS62401 VIN 2.5 V – 6 V FB 1 VIN 2.2 mH SW1 10 mF VOUT1 = 1.575 V 400 mA 22 mF DEF_1 EN_1 EN_2 2.2 mH SW2 MODE/ DATA VOUT2 = 1.8 V 600 mA 22 mF ADJ2 GND Figure 42. TPS62401 Fixed 1.575V/1.8V Outputs, low PFM Voltage Ripple Optimized TPS62401 VIN 2.5 V – 6 V FB 1 VIN 2.2 mH 10 mF SW1 DEF_1 VOUT1 = 1.1 V 400 mA 22 mF EN_1 EN_2 2.2 mH SW2 MODE/ DATA VOUT2 = 1.8 V 600 mA 22 mF ADJ2 GND Figure 43. TPS62401 Fixed 1.1V/1.8V Outputs, low PFM Ripple Voltage Optimized Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 29 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com TPS62401 VIN 2.5 V – 6 V FB 1 VIN 2.2 mH SW1 10 mF VOUT1 = 1.575 V 400 mA 10 mF DEF_1 EN_1 EN_2 2.2 mH SW2 MODE/ DATA VOUT2 = 1.8 V 600 mA 10 mF ADJ2 GND Figure 44. TPS62401 Fixed 1.575V/1.8V Outputs TPS62401/03 VIN 2.5 V – 6 V VIN Processor FB 1 L1 SW 1 10 µF EN_1 Vout 1 400 mA: DEF _1 = 0: 1.575 V DEF _1 = 1: 1.1 V 10 µF DEF _1 V Core_Sel L2 EN_2 SW 2 MODE / DATA ADJ 2 V Core Vout 2 600 mA: TPS 62401 : 1.8 V TPS 62403 : 2.8 V V I/O 10 µF GND Figure 45. Dynamic Voltage Scaling on Vout1 Controlled by DEF_1 pin 30 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 TPS62403 VIN 2.5 V – 6 V VIN FB 1 2.2 µH Vout 1 : 1.575 V 400 mA SW 1 10 m F 10 µF DEF _1 EN _1 3.3 µH EN _2 SW 2 MODE/ DATA ADJ 2 Vout 2: 2.8 V 600 mA 10 µF GND Figure 46. TPS62403 1.575V/2.8V Outputs OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) The converters are designed to operate with a minimum inductance of 1.75mH and minimum capacitance of 6mF. The device is optimized to operate with inductors of 2.2mH to 4.7mH and output capacitors of 10mF to 22mF. Inductor selection The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductor will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency. Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is recommended because during heavy load transient the inductor current rises above the calculated value. DI L + Vout 1 * Vout Vin L I Lmax + I outmax ) ƒ (6) DI L 2 (7) with: f = Switching Frequency (2.25MHz typical) L = Inductor Value ΔIL = Peak-to-Peak inductor ripple current ILmax = Maximum Inductor current The highest inductor current occurs at maximum Vin. Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. Take into consideration that the core material from inductor to inductor differs and this difference has an impact on the efficiency. Refer to Table 7 and the typical application circuit examples for possible inductors. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 31 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com Table 7. List of Inductors 3 DIMENSIONS [mm ] INDUCTOR TYPE SUPPLIER 3.2×2.6×1.0 MIPW3226 FDK 3×3×0.9 LPS3010 Coilcraft 2.8×2.6×1.0 VLF3010 TDK 2.8x2.6×1.4 VLF3014 TDK 3×3×1.4 LPS3015 Coilcraft 3.9×3.9×1.7 LPS4018 Coilcraft Output Capacitor Selection The advanced fast response voltage mode control scheme of the converters allows the use of tiny ceramic capacitors with a typical value of 10mF to 22mF, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors with low ESR values results in lowest output voltage ripple, and are therefore recommended. The output capacitor requires either X7R or X5R dielectric. Y5V and Z5U dielectric capacitors are not recommended due to their wide variation in capacitance. If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. The RMS ripple current is calculated as: 1 * Vout 1 Vin I RMSCout + Vout ƒ L 2 Ǹ3 (8) At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR, plus the voltage ripple caused by charging and discharging the output capacitor: DVout + Vout 1 * Vout Vin L ƒ ǒ8 1 Cout ƒ Ǔ ) ESR (9) Where the highest output voltage ripple occurs at the highest input voltage Vin. At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. Higher output capacitors like 22mF values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in PFM Mode. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interference with other circuits in the system. An input capacitor of 10mF is sufficient. LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low-inductance, impedance ground path. Therefore, use wide and short traces for the main current paths as indicated in bold in Figure 47. The input capacitor should be placed as close as possible to the IC pins VIN and GND, the inductor and output capacitor as close as possible to the pins SW1 and GND. 32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 www.ti.com SLVSA67 – FEBRUARY 2010 Connect the GND Pin of the device to the PowerPAD of the PCB and use this Pad as a star point. For each converter use a common Power GND node and a different node for the signal GND to minimize the effects of ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the common path to the GND PIN, which returns the small signal components and the high current of the output capacitors, as short as possible to avoid ground noise. The output voltage sense lines (FB 1, DEF_1, ADJ2) should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW1 and SW2 lines). If the EasyScale™ interface is operated with high transmission rates, the MODE/DATA trace must be routed away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between the MODE/DATA pin and ADJ2 pin avoids potential noise coupling. TPS62400 VIN 3 V – 6 V VIN EN_1 CIN EN_2 10 mF MODE/ DATA FB 1 L2 SW2 COUT2 Cff2 33 pF SW1 3.3 mH R21 L1 3.3 mH R11 ADJ2 DEF_1 R22 COUT1 R12 PowerPAD GND Figure 47. Layout Diagram Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 33 TPS62400-Q1, TPS62401-Q1 TPS62402-Q1, TPS62403-Q1 TPS62404-Q1 SLVSA67 – FEBRUARY 2010 www.ti.com COUT1 CIN GND Pin connected with Power Pad COUT2 Figure 48. PCB Layout 34 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS62404-Q1 PACKAGE OPTION ADDENDUM www.ti.com 24-Feb-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPS62404QDRCRQ1 ACTIVE SON DRC Pins Package Eco Plan (2) Qty 10 3000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS62404QDRCRQ1 Package Package Pins Type Drawing SON DRC 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 3.3 1.1 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62404QDRCRQ1 SON DRC 10 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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