TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 2.25-MHz, 600-mA Step-Down Converter in TSOT and 2 × 2 × 0.8-mm QFN Package Check for Samples: TPS62560, TPS62561, TPS62562 FEATURES DESCRIPTION • • • • • • • The TPS62560 device is a high efficiency synchronous step down converter, optimized for battery powered portable applications. It provides up to 1000-mA output current from batteries, such as single Li-Ion or other common chemistry AA and AAA cells. 1 • Output Current up to 600 mA VIN Range from 2.5 V to 5.5 V Output Voltage Accuracy in PWM Mode ±2.5% Typical 15-μA Quiescent Current 100% Duty Cycle for Lowest Dropout Soft Start Available in a Small TSOT, and 2 mm × 2 mm × 0.8 mm QFN Package For Improved Features Set, see TPS62260 APPLICATIONS • • • PDAs, Pocket PCs, Portable Media Players Low-Power DSP Supply POL Applications With an input voltage range of 2.5 V to 5.5 V, the device is targeted to power a large variety of portable handheld equipment or POL applications. The TPS62560 family operates at 2.25-MHz fixed switching frequency and enters a Power Save Mode operation at light load currents to maintain a high efficiency over the entire load current range. The Power Save Mode is optimized for low output voltage ripple. For low noise applications, the device can be forced into fixed frequency PWM mode by pulling the MODE pin high. In the shutdown mode the current consumption is reduced to less than 1 µA. The TPS62560 allows the use of small inductors and capacitors to achieve a small solution size. TPS62560 and TPS62562 are available in a 2-mm × 2-mm, 6-terminal QFN package, whereas the TPS62561 is available in a 5-terminal TSOT23 package. 100 90 V = 2.7 V IN VIN = 2.5 V to 5.5 V VIN CIN L 2.2 mH SW R1 EN 4.7 mF GND MODE FB R2 C1 22 pF Up to 600 mA VOUT COUT 10 mF h – Efficiency – % 80 VIN = 3 V TPS62560DRV VIN = 3.6 V 70 VIN = 4.5 V 60 50 40 VOUT = 1.8 V MODE = GND L = 2.2 mH DCR 110 mR 30 20 10 0 0.01 0.1 1 10 100 IOUT – Output Current – mA 1000 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA PART NUMBER (1) OUTPUT VOLTAGE (2) PACKAGE (3) –40°C to 85°C TPS62560 Adjustable QFN 2×2-6 DRV TPS62560DRV CEY –40°C to 85°C TPS62561 Adjustable TSOT-23-5 DDC TPS62561DDC CVO –40°C to 85°C TPS62562 1.8-V fixed QFN 2×2-6 DRV TPS62562DRV NXT (1) (2) (3) PACKAGE DESIGNATOR ORDERING PACKAGE MARKING The DRV (2-mm x 2-mm 6-terminal QFN) and the DDC (TSOT-23-5) packages are available in tape on reel. Add R suffix to order quantities of 3000 parts per reel and T suffix to order quantities with 250 parts per reel. Contact TI for other fixed-output-voltage options. For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Input voltage range (2) UNIT –0.3 to 7 –0.3 to VIN +0.3, ≤ 7 Voltage range at EN, MODE Voltage on SW V –0.3 to 7 Peak output current ESD rating (3) Internally limited HBM human-body model 2 CDM charged-device model 1 Machine model A kV 200 V TJ Maximum operating junction temperature –40 to 125 °C Tstg Storage temperature range –65 to 150 °C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal. The human-body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each terminal. The machine model is a 200-pF capacitor discharged directly into each terminal. DISSIPATION RATINGS PACKAGE RθJA POWER RATING FOR TA ≤ 25°C DERATING FACTOR ABOVE TA = 25°C DRV 76°C/W 1300 mW 13 mW/°C DDC 250°C/W 400 mW 4 mW/°C RECOMMENDED OPERATING CONDITIONS MIN VIN Supply voltage NOM MAX 2.5 5.5 UNIT V Output voltage range for adjustable voltage 0.85 VIN V TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C 2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6 V. External components CIN = 4.7 μF 0603, COUT = 10 μF 0603, L = 2.2 μH; see the Parameter Measurement Information section. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input voltage range IOUT Output current 2.5 VIN 2.5 V to 5.5 V IOUT = 0 mA, PFM mode enabled (MODE = GND), device not switching IQ Operating quiescent current ISD Shutdown current UVLO Undervoltage lockout threshold 5.5 V 600 mA 15 μA IOUT = 0 mA, PFM mode enabled (MODE = GND), device switching, VOUT = 1.8 V, See (1) 18.5 IOUT = 0 mA, switching with no load (MODE = VIN), PWM operation, VOUT = 1.8 V, VIN = 3 V 3.8 mA EN = GND 0.5 μA Falling 1.85 Rising 1.95 V ENABLE, MODE VIH High-level input voltage, EN, MODE 2 V ≤ VIN ≤ 5.5 V 1 VIN V VIL Low-level input voltage, EN, MODE 2 V ≤ VIN ≤ 5.5 V 0 0.4 V IIN Input bias current, EN, MODE EN, MODE = GND or VIN 0.01 1 μA 252 492 194 391 1 1.2 POWER SWITCH RDS(on) ILIMF TSD High side MOSFET on-resistance Low side MOSFET on-resistance VIN = VGS = 3.6 V, TA = 25°C Forward current limit, high and low VIN = VGS = 3.6 V side MOSFET 0.8 Thermal shutdown Increasing junction temperature 140 Thermal-shutdown hysteresis Decreasing junction temperature 20 mΩ A °C OSCILLATOR fSW 2 V ≤ VIN ≤ 5.5 V Oscillator frequency 2.25 MHz OUTPUT VOUT Adjustable-output voltage range VOUT TPS62562 fixed output voltage Vref Reference voltage 0.85 VIN ≥ 1.8 V Feedback voltage, PWM mode MODE = VIN, PWM operation, for fixed-output-voltage versions VFB = VOUT, 2.5 V ≤ VIN ≤ 5.5 V, 0 mA ≤ IOUT ≤ 600 mA Feedback voltage, PFM mode MODE = GND, device in PFM mode, voltage positioning active (1) Load regulation PWM mode tStart Up Start-up time Time from active EN to reach 95% of VOUT nominal tRamp VOUT ramp-up time Time to ramp from 5% to 95% of VOUT Ilkg Leakage current into SW terminal VIN = 3.6 V, VIN = VOUT = VSW, EN = GND VFB (1) (2) (3) (2) –2.5% VIN V 600 mV 0% 2.5% 1% –1 %/A 500 μs μs 250 (3) V 1.8 0.5 1 μA In PFM mode, the internal reference voltage is set to typ. 1.01 × Vref. See the Parameter Measurement Information section. For VIN = VOUT + 0.6 V In fixed-output-voltage versions, the internal resistor divider network is disconnected from the FB terminal. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 3 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com PIN ASSIGNMENTS DDC PACKAGE TSOT23-5 (TOP VIEW) VIN 1 5 DRV PACKAGE SON-6 (TOP VIEW) SW SW MODE GND 6 GND 2 Thermal 5 Pad VIN 3 EN 2 FB EN 1 3 4 4 FB Figure 1. PIN FUNCTIONS PIN No. QFN-6 No. TSOT23-5 I/O DESCRIPTION EN 4 3 I This is the enable terminal of the device. Pulling this terminal to low forces the device into shutdown mode. Pulling this terminal to high enables the device. This terminal must be terminated. FB 3 4 I Feedback terminal for the internal regulation loop. Connect the external resistor divider to this terminal. In the fixed-output-voltage option, connect this terminal directly to the output capacitor. GND 6 2 — NAME GND supply terminal MODE 2 — I This terminal is only available as an QFN package option. MODE terminal = high forces the device to operate in the fixed-frequency PWM mode. MODE terminal = low enables the power-save mode with automatic transition from PFM mode to fixed-frequency PWM mode. SW 1 5 O This is the switch terminal and is connected to the internal MOSFET switches. Connect the external inductor between this terminal and the output capacitor. VIN 5 1 — VIN power-supply terminal 4 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 FUNCTIONAL BLOCK DIAGRAM VIN CurrentLimit Comparator Thermal Shutdown VIN Undervoltage Lockout 1.8 V Limit High Side EN PFM Comparator +1% Voltage positioning Reference 0.6 V VREF FB VREF +1% Only in 2x2SON MODE MODE Softstart VOUT RAMP CONTROL Error Amplifier Control Stage Gate Driver AntiShoot-Through SW1 VREF Integrator FB FB PWM Comp. Zero-Pole Amp. Limit Low Side RI 1 RI3 RI..N Int. Resistor Network CurrentLimit Comparator 2.25-MHz Oscillator Sawtooth Generator GND GND PARAMETER MEASUREMENT INFORMATION TPS62560DRV VIN CIN 4.7 mF MODE VOUT SW R1 EN GND L 2.2 mH C1 22 pF FB COUT 10 mF R2 L: LPS3015, 2.2 mH, 110 mW CIN: GRM188R60J475K, 4.7 mF, Murata, 0603 size COUT: GRM188R60J106M, 10 mF, Murata, 0603 size Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 5 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS Table 1. Table of Graphs FIGURE η Efficiency Typical Operation Mode Transition vs Output Current, VOUT = 1.8 V, Power Save Mode, MODE = GND Figure 2 vs Output Current, VOUT = 1.8 V, PWM Mode, MODE = VIN Figure 3 vs Output Current, VOUT = 3.3 V, PWM Mode, MODE = VIN Figure 4 vs Output Current, VOUT = 3.3 V, Power Save Mode, MODE = GND Figure 5 vs Output Current, MODE = VIN Figure 6 vs Output Current, MODE = GND Figure 7 PWM Mode, VOUT = 1.8 V Figure 8 MODE Terminal Transition From PFM to Forced PWM Mode at Light Load Figure 9 MODE Terminal Transition From Forced PWM to PFM Mode at Light Load Figure 10 Start-up Timing Load Transient Line Transient Typical Operation Quiescent Current Static Drain-Source On-State Resistance 6 Submit Documentation Feedback Figure 11 Forced PWM Mode, VOUT = 1.5 V, 50 mA to 200 mA Figure 12 Forced PWM Mode, VOUT = 1.5 V, 200 mA to 400 mA Figure 13 Forced PFM Mode to PWM Mode, VOUT = 1.5 V, 150 μA to 400 mA Figure 14 Forced PWM Mode to PFM Mode, VOUT = 1.5 V, 400 mA to 150 μA Figure 15 PFM Mode, VOUT = 1.5 V, 1.5 mA to 50 mA Figure 16 PFM Mode, VOUT = 1.5 V, 50 mA to 1.5 mA Figure 17 PFM Mode to PWM Mode, VOUT = 1.8 V, 50 mA to 250 mA Figure 18 PFM Mode to PWM Mode, VOUT = 1.5 V, 50 mA to 400 mA Figure 19 PWM Mode to PFM Mode, VOUT = 1.5 V, 400 mA to 50 mA Figure 20 PFM Mode, VOUT = 1.8 V, 50 mA Figure 21 PFM Mode, VOUT = 1.8 V, 250 mA Figure 22 PFM Mode, VOUT Ripple, VOUT = 1.8 V, 10 mA, L = 2.2 μH, COUT = 10 μF Figure 23 PFM Mode, VOUT Ripple, VOUT = 1.8 V, 10 mA, L = 4.7 μH, COUT = 10 μF Figure 24 vs Input Voltage, (TA = 85°C, TA = 25°C, TA = –40°C) Figure 25 vs Input Voltage, (TA = 85°C, TA = 25°C, TA = –40°C), High-Side Switching Figure 26 vs Input Voltage, (TA = 85°C, TA = 25°C, TA = –40°C), Low-Side Switching Figure 27 Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 EFFICIENCY (Power Save Mode) vs OUTPUT CURRENT EFFICIENCY (Forced PWM Mode) vs OUTPUT CURRENT 100 100 90 90 VIN = 2.7 V 80 VIN = 2.7 V VIN = 3.6 V 70 h – Efficiency – % h – Efficiency – % 80 V = 3 V IN VIN = 4.5 V 60 50 40 30 10 0 0.01 VIN = 3 V 60 VIN = 3.6 V VIN = 4.5 V 50 40 30 VOUT = 1.8 V MODE = GND L = 2.2 mH DCR 110 mR 20 70 VOUT = 1.8 V MODE = VIN L = 2.2 mH 20 10 0 0.1 1 10 100 1000 1 10 100 IOUT – Output Current – mA IOUT – Output Current – mA 1000 G003 G002 Figure 2. Figure 3. EFFICIENCY (Forced PWM Mode) vs OUTPUT CURRENT EFFICIENCY (Power Save Mode) vs OUTPUT CURRENT 100 100 VIN = 4.2 V 90 80 90 VIN = 5 V h – Efficiency – % h – Efficiency – % 70 VIN = 4.5 V 50 40 VOUT = 3.3 V MODE = VIN L = 2.2 mH DCR 110 mW COUT = 10 mF 0603 30 20 10 VIN = 5 V 10 100 IOUT – Output Current – mA 70 VIN = 4.5 V 60 50 40 VOUT = 3.3 V MODE = GND L = 2.2 mH DCR = 110 mH COUT = 10 mF 0603 30 20 10 0 1 VIN = 3.6 V 80 VIN = 3.6 V 60 VIN = 4.2 V 1000 0 0.01 0.1 1 10 100 1000 IOUT – Output Current – mA Figure 4. Figure 5. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 7 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com EFFICIENCY (Forced PWM Mode) vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 VIN = 2.7 V 80 80 60 h − Efficiency − % h − Efficiency − % VIN = 4.5 V 70 VIN = 4.5 V 50 VIN = 3.6 V 40 VOUT = 1.2 V MODE = VIN L = 2 mH MIPSA2520 COUT = 10 mF 0603 30 20 10 10 100 VIN = 3.6 V 60 50 VIN = 2.7 V 40 30 VOUT = 1.2 V MODE = GND L = 2 mH MIPSA2520 COUT = 10 mF 0603 20 10 0 1 70 1000 0 0.01 0.1 IOUT − Output Current − mA 1 10 100 G005 G004 Figure 6. Figure 7. TYPICAL OPERATION (PWM Mode) MODE TERMINAL TRANSITION FROM PFM TO FORCED PWM MODE AT LIGHT LOAD VIN 3.6V VOUT 1.8V, IOUT 150mA L 2.2mH, COUT 10mF 0603 VOUT 10 mV/Div 1000 IOUT − Output Current − mA VIN = 3.6 V VOUT = 1.8 V IOUT = 10 mA MODE 2V/Div SW 2 V/Div SW 2V/Div PFM Mode Forced PWM Mode ICOIL 200 mA/Div Icoil 200mA/Div 8 Time Base - 10 ms/Div Time Base - 1 ms/Div Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 MODE TERMINAL TRANSITION FROM PWM TO PFM MODE AT LIGHT LOAD MODE 2 V/Div VIN = 3.6 V VOUT = 1.8 V IOUT = 10 mA SW 2 V/Div START-UP TIMING EN 2 V/Div VIN = 3.6 V RLoad = 10 Ω VOUT = 1.8 V IIN into CIN MODE = GND SW 2 V/Div PFM Mode Forced PWM Mode VOUT 2 V/Div ICOIL 200 mA/Div IIN 100 mA/Div Time Base - 100 ms/Div Time Base - 2.5 ms/Div Figure 10. Figure 11. LOAD TRANSIENT (Forced PWM Mode) LOAD TRANSIENT (Forced PWM Mode) VIN 3.6 V VOUT 1.5 V IOUT 50 mA to 200 mA MODE = VIN VOUT 50 mV/Div VIN 3.6 V VOUT 1.5 V IOUT 200 mA to 400 mA VOUT 50 mV/Div IOUT 200 mA/Div 400 mA 200 mA IOUT 200 mA/Div ICOIL 500 mA/Div ICOIL 500 mA/Div Time Base - 20 ms/Div Time Base - 20 ms/Div Figure 12. Figure 13. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 9 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 LOAD TRANSIENT (Forced PFM Mode To PWM Mode) www.ti.com LOAD TRANSIENT (Forced PWM Mode To PFM Mode) SW 2 V/Div SW 2 V/Div VIN 3.6 V VOUT 1.5 V IOUT 150 mA to 400 mA VOUT 50mV/Div MODE = GND 400 mA IOUT 500 mA/Div VIN 3.6 V VOUT 1.5 V IOUT 150 mA to 400 mA MODE = GND VOUT 50 mV/Div 400 mA IOUT 500 mA/Div 150 mA 150 mA ICOIL500 mA/Div ICOILl 500mA/Div Time Base – 500 ms/Div Time Base – 500 ms/Div Figure 14. Figure 15. LOAD TRANSIENT (PFM Mode) LOAD TRANSIENT (PFM Mode) SW 2 V/Div VIN 3.6 V VOUT 1.5 V IOUT 1.5 mA to 50 mA MODE = GND SW 2 V/Div VIN 3.6 V VOUT 1.5 V IOUT 50 mA to 1.5mA MODE = GND VOUT 50 mV/Div VOUT 50mV/Div 50 mA 50 mA IOUT 50 mA/Div IOUT 50 mA/Div 1.5 mA 1.5 mA ICOIL 500 mA/Div ICOIL 500 mA/Div Time Base – 50 ms/Div Time Base – 50 ms/Div Figure 16. 10 Submit Documentation Feedback Figure 17. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 LOAD TRANSIENT (PFM Mode To PWM Mode) SW 2 V/Div LOAD TRANSIENT (PFM Mode To PWM Mode) SW 2 V/Div VIN 3.6 V VOUT 1.5 V IOUT 50 mA to 400 mA MODE = GND VOUT 50 mV/Div VIN 3.6 V VOUT 1.8 V IOUT 50 mA to 250 mA MODE = GND VOUT 50 mV/Div PWM Mode PFM Mode 250 mA 400 mA IOUT 500 mA/Div IOUT 200 mA/Div 50 mA 50 mA ICOIL 500 mA/Div ICOIL 500mA/Div Time Base – 20 ms/Div Time Base – 20 ms/Div Figure 18. Figure 19. LOAD TRANSIENT (PWM Mode To PFM Mode) LINE TRANSIENT (PFM Mode) SW 2 V/Div VIN 3.6V to 4.2V 500 mV/Div VIN 3.6 V VOUT 1.5 V IOUT 50 mA to 400 mA MODE = GND VOUT 50 mV/Div PFM Mode PWM Mode 400 mA IOUT 500 mA/Div 50 mA VOUT = 1.8 V 50 mV/Div IOUT = 50 mA MODE = GND ICOIL 500 mA/Div Time Base – 20 ms/Div Figure 20. Figure 21. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 11 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com LINE TRANSIENT (PWM Mode) TYPICAL OPERATION (PFM Mode) VOUT 20 mV/Div VIN 3.6V to 4.2V 500 mV/Div SW 2 V/Div VOUT = 1.8 V 50 mV/Div IOUT = 250 mA MODE = GND ICOIL 200 mA/Div Time Base – 10 ms/Div Time Base – 100ms/Div Figure 22. Figure 23. TYPICAL OPERATION (PFM Mode) QUIESCENT CURRENT vs INPUT VOLTAGE 20 VIN 3.6 V; VOUT 1.8 V, IOUT 10 mA, L = 4.7 mH, COUT = 10 mF 0603, MODE = GND VOUT 20 mV/Div IQ – Quiescent Current – mA 18 SW 2 V/Div ICOIL 200 mA/Div MODE == GND, GND MODE EN == VIN, VIN EN Device Device Not Not Switching Switching o TTAA == 85 85°C 16 o C TTAA = 25 °C 14 12 C TTAA == –40 -40o°C 10 Time Base – 2 ms/Div 8 8 222 2.5 3 3.5 44 4.5 4.5 55 5.5 5.5 66 V VIN InputVoltage Voltage–−VV IN–−Input Figure 24. 12 Submit Documentation Feedback Figure 25. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 0.8 0.4 High-Side Switching 0.7 0.6 o TA = 85 C 0.5 TA = 25oC 0.4 0.3 0.2 o TA = −40 C 0.1 0 2 2.5 3 3.5 4 4.5 5 RDS(on) − Static Drain-Source On-State Resistance − W RDS(on) − Static Drain-Source On-State Resistance − W www.ti.com Low-Side Switching 0.35 0.3 TA = 85oC 0.25 o TA = 25 C 0.2 0.15 0.1 o TA = –40 C 0.05 0 2 2.5 3 3.5 4 4.5 5 VIN − Input Voltage − V VIN − Input Voltage − V G012 Figure 26. Figure 27. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 13 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com DETAILED DESCRIPTION OPERATION The TPS62560/62 step-down converters operate with typically 2.25-MHz fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. At light load currents, the converter can automatically enter power-save mode, and then operates in PFM mode. However, the TPS62561 operates with fixed-frequency PWM only, also at light load conditions. During PWM operation, the converter uses a unique fast-response voltage-mode control scheme with input-voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch is turned on. The current flows from the input capacitor via the high-side MOSFET switch through the inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the control logic turns off the switch. The current-limit comparator also turns off the switch in case the current limit of the high-side MOSFET switch is exceeded. After a dead time, which prevents shoot-through current, the low-side MOSFET rectifier is turned on and the inductor current ramps down. The current flows from the inductor to the output capacitor and to the load. It returns back to the inductor through the low-side MOSFET rectifier. The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the on the high-side MOSFET switch. POWER-SAVE MODE The power-save mode is enabled with the MODE terminal set to the low level. If the load current decreases, the converter enters the power-save mode of operation automatically. During power-save mode, the converter skips switching and operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically 1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. The transition from PWM mode to PFM mode occurs once the inductor current in the low-side MOSFET switch becomes zero, which indicates discontinuous conduction mode. During the power-save mode, the output voltage is monitored with a PFM comparator. As the output voltage falls below the PFM comparator threshold of VOUT nominal + 1%, the device starts a PFM current pulse. The high-side MOSFET switch turns on, and the inductor current ramps up. After the on-time expires, the switch is turned off and the low-side MOSFET switch is turned on until the inductor current becomes zero. The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered current, the output voltage rises. If the output voltage is equal to or higher than the PFM comparator threshold, the device stops switching and enters a sleep mode with typical 15-μA current consumption. If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses is generated until the PFM comparator threshold is reached. The converter starts switching again once the output voltage drops below the PFM comparator threshold. With a fast single-threshold comparator, the output-voltage ripple during PFM-mode operation can be kept small. The PFM pulse is time controlled, which allows modifying the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output-voltage ripple and PFM frequency depend primarily on the size of the output capacitor and the inductor value. Increasing output capacitor values and inductor values minimizes the output ripple. The PFM frequency decreases with smaller inductor values and increases with larger values. The PFM mode is left and PWM mode entered in case the output current can no longer be supported in PFM mode. The power-save mode can be disabled by setting the MODE terminal to high. The converter then operates in the fixed-frequency PWM mode. Dynamic Voltage Positioning This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is active in power-save mode and regulates the output voltage 1% higher than the nominal value. This provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. 14 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 Output voltage Voltage Positioning Vout +1% PFM Comparator threshold Light load PFM Mode Vout (PWM) moderate to heavy load PWM Mode Figure 28. Power Save Mode Operation With Automatic Mode Transition 100% Duty-Cycle Low-Dropout Operation The device starts to enter 100% duty-cycle mode once the input voltage comes close to the nominal output voltage. In order to maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more cycles. With further decreasing VIN, the high-side MOSFET switch is turned on completely. In this case, the converter offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery-voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: VINmin = VOUTmax + IOUTmax × (RDS(on)max + RL) with: IOUTmax = maximum output current plus inductor ripple current RDS(on)max = maximum P-channel switch RDS(on) RL = dc resistance of the inductor VOUTmax = nominal output voltage plus maximum output voltage tolerance Undervoltage Lockout The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the output stage of the converter. The undervoltage lockout threshold is typically 1.85 V with falling VIN. MODE SELECTION The MODE terminal allows mode selection between forced-PWM mode and power-save mode. Connecting this terminal to GND enables the power-save mode with automatic transition between PWM and PFM modes. Pulling the MODE terminal high forces the converter to operate in fixed-frequency PWM mode even at light load currents. This allows simple filtering of the switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save mode during light loads. The state of the MODE terminal can be changed during operation to allow efficient power management by adjusting the operation mode of the converter to the specific system requirements. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 15 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com ENABLE The device is enabled by setting the EN terminal to high. During the start-up time tStart Up, the internal circuits are settled and the soft-start circuit is activated. The EN input can be used to control power sequencing in a system with various dc/dc converters. The EN terminal can be connected to the output of another converter, to drive the EN terminal high to achieve a sequencing of the given supply rails. With EN = GND, the device enters shutdown mode, in which all internal circuits are disabled. In fixed-output-voltage versions, the internal resistor divider network is then disconnected from the FB terminal. SOFT START The TPS62560 has an internal soft-start circuit that controls the ramp-up of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value typically within 250 μs. This limits the inrush current into the converter during ramp-up and prevents possible input voltage drops when a battery or high-impedance power source is used. The soft-start circuit is enabled within the start-up time tStart Up. SHORT-CIRCUIT PROTECTION The high-side and low-side MOSFET switches are short-circuit protected with maximum switch current = ILIMF. The current in the switches is monitored by current-limit comparators. Once the current in the high-side MOSFET switch exceeds the threshold of its current-limit comparator, it turns off and the low-side MOSFET switch is activated to ramp down the current in the inductor and high-side MOSFET switch. The high-side MOSFET switch can only turn on again after the current in the low-side MOSFET switch has decreased below the threshold of its current-limit comparator. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds 140°C (typical), the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis. 16 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 APPLICATION INFORMATION TPS62560DRV VIN = 2.5 V to 5.5 V VIN CIN 4.7 mF VOUT = 1.2 V SW R1 360 kW EN GND L1 2.2 mH C1 22 pF COUT 10 mF FB R2 360 kW MODE S0364_01 Figure 29. TPS62560 Adjustable 1.2-V Output TPS62560DRV VIN = 2.5 V to 5.5 V VIN CIN 4.7 mF VOUT = 1.5 V Up to 600 mA SW R1 540 kW EN GND L1 2.2 mH C1 22 pF COUT 10 mF FB R2 360 kW MODE S0365-01 Figure 30. TPS62560 Adjustable 1.5-V Output TPS62562DRV VIN = 2 V to 6 V VIN CIN 4.7 mF L1 2.2 mH SW COUT 10 mF EN GND VOUT = 1.8 V Up to 600 mA FB MODE S0366-01 Figure 31. TPS62562 Fixed 1.8-V Output Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 17 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com OUTPUT VOLTAGE SETTING For adjustable output voltage versions, the output voltage can be calculated as: æ R ö VOUT = VREF ´ ç 1+ 1 ÷ è R2 ø with an internal reference voltage VREF, typically 0.6 V. To minimize the current through the feedback divider network, R2 should be 180 kΩ or 360 kΩ. The sum of R1 and R2 should not exceed ~1 MΩ, to keep the network robust against noise. An external feed-forward capacitor, C1, is required for optimum load transient response. The value of C1 should be in the range between 22 pF and 33 pF. In case of using the fixed output voltage version (TPS62562), Vout has to be connected to the feedback pin FB. Route the FB line away from noise sources, such as the inductor or the SW line. OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR) The TPS62560 is designed to operate with inductors in the range of 1.5 μH to 4.7 μH and with output capacitors in the range of 4.7 μF to 22 μF. The part is optimized for operation with a 2.2-μH inductor and 10-μF output capacitor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For stable operation, the L and C values of the output filter may not fall below 1 μH effective inductance and 3.5 μF effective capacitance. Inductor Selection The inductor value has a direct effect on the ripple current. The selected inductor must be rated for its dc resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN or VOUT. The inductor selection also impacts the output voltage ripple in PFM mode. Higher inductor values lead to lower output voltage ripple and higher PFM frequency; lower inductor values lead to a higher output voltage ripple but lower PFM frequency. Equation 1 calculates the maximum inductor current in PWM mode under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 2. This is recommended because during heavy load transients the inductor current rises above the calculated value. V 1 * OUT V DI L + VOUT L I L max + I out max ) IN f DI L (1) 2 (2) where: f = Switching frequency (2.25 MHz, typical) L = Inductor value ΔIL = Peak-to-peak inductor ripple current ILmax = Maximum inductor current Table 2. List of Inductors 18 DIMENSIONS, mm INDUCTANCE, μH INDUCTOR TYPE SUPPLIER 2,5 × 2 × 1 max 2 MIPS2520D2R2 FDK 2,5 × 2 × 1,2 max 2 MIPSA2520D2R2 FDK 2,5 × 2 × 1 max 2.2 KSLI-252010AG2R2 Hitachi Metals 2,5 × 2 × 1,2 max 2.2 LQM2HPN2R2MJ0L Murata 3 × 3 × 1,5 max 2.2 LPS3015 2R2 Coilcraft Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 A more conservative approach is to select the inductor current rating just for the switch current limit ILIMF of the converter. Accepting larger values of ripple current allows the use of lower inductance values, but results in higher output voltage ripple, greater core losses, and lower output current capability. The total losses of the coil have a strong impact on the efficiency of the dc/dc conversion and consist of both the losses in the dc resistance (R(DC)) and the following frequency-dependent components: • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) • Additional losses in the conductor from the skin effect (current displacement at high frequencies) • Magnetic field losses of the neighboring windings (proximity effect) • Radiation losses Output Capacitor Selection The advanced fast-response voltage-mode control scheme of the TPS62560 allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At nominal load current, the device operates in PWM mode, and the RMS ripple current is calculated as: V 1 - OUT VIN 1 IRMSCOUT = VOUT ´ ´ L´f 2 3 (3) At nominal load current, the device operates in PWM mode, and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: V 1 - OUT æ ö VIN 1 DVOUT = VOUT ´ ´ç + ESR ÷ L´f è 8 ´ COUT ´ f ø (4) At light load currents, the converter operates in power-save mode, and the output voltage ripple is dependent on the output capacitor and inductor values. Larger output capacitor and inductor values minimize the voltage ripple in PFM mode and tighten dc output accuracy in PFM mode. Input Capacitor Selection An input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For most applications, a 4.7-μF to 10-μF ceramic capacitor is recommended. Because a ceramic capacitor loses up to 80% of its initial capacitance at 5 V, it is recommended that 10-μF input capacitors be used for input voltages > 4.5 V. The input capacitor can be increased without any limit for better input voltage filtering. Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on the input can induce ringing at the VIN terminal. This ringing can couple to the output and be mistaken as loop instability or could even damage the part by exceeding the maximum ratings. Table 3. List of Capacitors CAPACITANCE TYPE SIZE SUPPLIER 4.7 μF GRM188R60J475K 0603—1,6 × 0,8 × 0,8 mm Murata 10 μF GRM188R60J106M69D 0603—1,6 × 0,8 × 0,8 mm Murata Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 19 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com LAYOUT CONSIDERATIONS Figure 32. Suggested Layout for Fixed-Output-Voltage Options 20 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 TPS62560, TPS62561 TPS62562 www.ti.com SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 VOUT R2 GND C1 R1 COUT CIN VIN L G N D U Figure 33. Suggested Layout for Adjustable-Output-Voltage Version As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation and stability issues, as well as EMI problems. It is critical to provide a low-inductance, low-impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor, inductor, and output capacitor should be placed as close as possible to the IC terminals. Connect the GND terminal of the device to the thermal-pad land of the PCB and use this pad as a star point. Use a common power-GND node and a different node for the signal GND to minimize the effects of ground noise. Connect these ground nodes together to the thermal-pad land (star point) underneath the IC. Keep the common path to the GND terminal, which returns the small signal components and the high current of the output capacitors, as short as possible to avoid ground noise. The FB line should be connected directly to the output capacitor and routed away from noisy components and traces (e.g., the SW line). Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 Submit Documentation Feedback 21 TPS62560, TPS62561 TPS62562 SLVS815C – JANUARY 2008 – REVISED DECEMBER 2009 www.ti.com Changes from Original (January 2008) to Revision A • Page Changed at all levels. Revision A is a complete rewrite of this data sheet. ......................................................................... 1 Changes from Revision A (July 2008) to Revision B • Page Added TPS62562 device number. ........................................................................................................................................ 1 Changes from Revision B (March 2009) to Revision C Page • Deleted High Efficiency Step Down Converter ..................................................................................................................... 1 • Deleted "Wide" from Features bullet ..................................................................................................................................... 1 • Deleted "for Li-Ion Batteries With Extended Voltage Range" from Features ....................................................................... 1 • Deleted "Adjustable and Fixed Output-Voltage Options" from Features .............................................................................. 1 • Deleted "2.25 MHz Fixed Frequency Operation" from Features .......................................................................................... 1 • Deleted "Power Save Mode at Light Load Currents" from Features .................................................................................... 1 • Deleted "Voltage Positioning at Light Loads" from Features ................................................................................................ 1 • Deleted "Allows < 1-mm Solution Height" from Features ..................................................................................................... 1 • Added reference to TPS62260 ............................................................................................................................................. 1 • Changed Description to better reflect device capabilities and differences to TPS62260 ..................................................... 1 22 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TPS62560 TPS62561 TPS62562 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS62560DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CEY TPS62560DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CEY TPS62560DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CEY TPS62560DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CEY TPS62561DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CVO TPS62561DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CVO TPS62562DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NXT TPS62562DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NXT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS62560DRVR SON DRV 6 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS62560DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS62561DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS62561DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS62562DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS62562DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62560DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS62560DRVT SON DRV 6 250 203.0 203.0 35.0 TPS62561DDCR SOT DDC 5 3000 203.0 203.0 35.0 TPS62561DDCT SOT DDC 5 250 203.0 203.0 35.0 TPS62562DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS62562DRVT SON DRV 6 250 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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