CYPRESS CY62126ESL

CY62126ESL MoBL®
1-Mbit (64K x 16) Static RAM
Features
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (IO0 through IO15) are placed in a high impedance
state when the device is deselected (CE HIGH), the outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH) or during a write
operation (CE LOW and WE LOW).
■
Very high speed: 45 ns
■
Wide voltage range: 2.2V–3.6V and 4.5V–5.5V
■
Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 4 μA
■
Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■
Easy memory expansion with CE, and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 44-Pin TSOP II package
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A15).
Functional Description
The CY62126ESL is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the Truth Table on page 10 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
64K x 16
RAM Array
IO0–IO7
IO8–IO15
•
BHE
WE
CE
OE
BLE
A15
A14
A13
A11
Cypress Semiconductor Corporation
Document #: 001-45076 Rev. *A
A12
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 15, 2009
[+] Feedback
CY62126ESL MoBL®
Pin Configuration
44-Pin TSOP II (Top View) [1]
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
NC
A8
A9
A10
A11
NC
Product Portfolio
Power Dissipation
Product
Range
VCC Range (V) [2]
Speed
(ns)
Operating ICC, (mA)
f = 1MHz
Typ
CY62126ESL
Industrial
2.2V–3.6V and 4.5V–5.5V
45
[3]
1.3
f = fmax
Standby, ISB2
(μA)
Max
Typ [3]
Max
Typ [3]
Max
2
11
16
1
4
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6V to 4.5V.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 001-45076 Rev. *A
Page 2 of 12
[+] Feedback
CY62126ESL MoBL®
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied .............................................. 55°C to +125°C
Supply Voltage to Ground
Potential ...........................................................–0.5V to 6.0V
DC Voltage Applied to Outputs
in High-Z State [4, 5] ..........................................–0.5V to 6.0V
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Operating Range
Device
Range
Ambient
Temperature
VCC[6]
CY62126ESL
Industrial
–40°C to +85°C
2.2V–3.6V,
and
4.5V–5.5V
DC Input Voltage [4, 5] .......................................–0.5V to 6.0V
Electrical Characteristics
Over the Operating Range
45 ns
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Typ [3]
Max
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
2.7 < VCC < 3.6
IOH = –1.0 mA
2.4
4.5 < VCC < 5.5
IOH = –1.0 mA
2.4
2.2 < VCC < 2.7
IOL = 0.1 mA
0.4
2.7 < VCC < 3.6
IOL = 2.1mA
0.4
4.5 < VCC < 5.5
IOL = 2.1mA
VCC + 0.3
2.7 < VCC < 3.6
2.2
VCC + 0.3
4.5 < VCC < 5.5
2.2
VCC + 0.5
2.2 < VCC < 2.7
–0.3
0.6
2.7 < VCC < 3.6
–0.3
0.8
4.5 < VCC < 5.5
–0.5
0.8
GND < VI < VCC
–1
+1
IOZ
Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
ISB1
Automatic CE Power
CE > VCC − 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
down Current — CMOS f = fmax (Address and Data Only), f = 0 (OE and WE),
Inputs
VCC = VCC(max)
Automatic CE Power
CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V,
down Current — CMOS f = 0, VCC = VCC(max)
Inputs
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA, CMOS levels
V
0.4
1.8
Input Leakage Current
Unit
V
2.2 < VCC < 2.7
IIX
ISB2
Min
V
V
μA
+1
μA
11
16
mA
1.3
2.0
1
4
μA
1
4
μA
–1
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a minimum of 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization.
Document #: 001-45076 Rev. *A
Page 3 of 12
[+] Feedback
CY62126ESL MoBL®
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Unit
10
pF
10
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
TSOP II
Unit
28.2
°C/W
3.4
°C/W
AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
VCC
30 pF
INCLUDING
JIG AND
SCOPE
R2
GND
Rise Time = 1 V/ns
Equivalent to:
2.50V
R1
R2
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
RTH
OUTPUT
Parameters
90%
10%
90%
10%
V
3.0V
5.0V
Unit
16600
1103
1800
Ω
15400
1554
990
Ω
RTH
8000
645
639
Ω
VTH
1.2
1.75
1.77
V
Document #: 001-45076 Rev. *A
Page 4 of 12
[+] Feedback
CY62126ESL MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR [7]
Chip Deselect to Data
Retention Time
tR [8]
Operation Recovery Time
Conditions
Min
Typ [3]
Max
1.5
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
VCC = 1.5V
Unit
V
3
μA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
VDR > 1.5V
tCDR
VCC(min)
tR
CE
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.
Document #: 001-45076 Rev. *A
Page 5 of 12
[+] Feedback
CY62126ESL MoBL®
Switching Characteristics
Over the Operating Range [9]
Parameter
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
45
ns
tDOE
OE LOW to Data Valid
22
ns
tLZOE
45
OE LOW to Low Z
tHZOE
tLZCE
CE LOW to Low Z
45
[10]
OE HIGH to High Z
10
[10, 11]
tPU
CE LOW to Power Up
tPD
CE HIGH to Power Up
tDBE
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
Write Cycle
ns
18
[10]
0
BHE / BLE HIGH to High Z
ns
ns
45
ns
22
ns
5
[10, 11]
ns
ns
18
[10]
ns
ns
5
CE HIGH to High Z
tHZBE
10
[10, 11]
tHZCE
tLZBE
ns
ns
18
ns
[12]
tWC
Write Cycle Time
45
ns
tSCE
CE LOW to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tBW
BHE / BLE Pulse Width
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
tLZWE
WE LOW to High
Z [10, 11]
WE HIGH to Low Z
[10]
18
10
ns
ns
Notes
9. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-45076 Rev. *A
Page 6 of 12
[+] Feedback
CY62126ESL MoBL®
Switching Waveforms
Figure 1. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 2. Read Cycle No. 2 (OE Controlled) [14, 15]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for read cycles.
15. Address valid before or similar to CE transition LOW.
Document #: 001-45076 Rev. *A
Page 7 of 12
[+] Feedback
CY62126ESL MoBL®
Switching Waveforms
(continued)
Figure 3. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [16, 17]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA IO
tSD
NOTE 18
tHD
DATAIN
tHZOE
Figure 4. Write Cycle No. 2 (CE Controlled) [16, 17]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
tHD
DATAIN
NOTE 18
tHZOE
Notes
16. Data IO is high impedance if OE = VIH.
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
18. During this period, the IOs are in output state. Do not apply input signals.
Document #: 001-45076 Rev. *A
Page 8 of 12
[+] Feedback
CY62126ESL MoBL®
Switching Waveforms
(continued)
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) [17]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA IO
NOTE 18
tHD
DATAIN
tLZWE
tHZWE
Figure 6. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [17]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA IO
NOTE 18
tSD
tHD
DATAIN
tLZWE
Document #: 001-45076 Rev. *A
Page 9 of 12
[+] Feedback
CY62126ESL MoBL®
Truth Table
CE
WE
OE
BHE
BLE
H
X
X
X
X
X
X
X
H
L
H
L
L
L
H
L
L
H
L
Inputs/Outputs
Mode
Power
High Z
Deselect or Power Down
Standby (ISB)
H
High Z
Output Disabled
Active (ICC)
L
Data Out (IO0–IO15)
Read
Active (ICC)
H
L
Data Out (IO0–IO7);
IO8–IO15 in High Z
Read
Active (ICC)
L
L
H
Data Out (IO8–IO15);
IO0–IO7 in High Z
Read
Active (ICC)
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
L
X
H
L
Data In (IO0–IO7);
IO8–IO15 in High Z
Write
Active (ICC)
L
L
X
L
H
Data In (IO8–IO15);
IO0–IO7 in High Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
45
Ordering Code
CY62126ESL-45ZSXI
Document #: 001-45076 Rev. *A
Package
Diagram
Package Type
51-85087 44-Pin TSOP II (Pb-free)
Operating
Range
Industrial
Page 10 of 12
[+] Feedback
CY62126ESL MoBL®
Package Diagrams
Figure 7. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087-*A
Document #: 001-45076 Rev. *A
Page 11 of 12
[+] Feedback
CY62126ESL MoBL®
Document History Page
Document Title: CY62126ESL MoBL® 1-Mbit (64K x 16) Static RAM
Document Number: 001-45076
Revision
ECN
Submission
Date
Orig. of
Change
**
2610988
11/21/08
VKN/PYRS
*A
2718906
06/15/2009
VKN
Description of Change
New data sheet
Post to external web
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
Clocks & Buffers
PSoC Solutions
psoc.cypress.com
clocks.cypress.com
General
Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
Wireless
wireless.cypress.com
Precision Analog
Memories
memory.cypress.com
LCD Drive
psoc.cypress.com/lcd-drive
image.cypress.com
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
Image Sensors
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-45076 Rev. *A
Revised June 15, 2009
Page 12 of 12
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback