CY62187EV30, MoBL® 64 Mbit (4M x 16) Static RAM ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99 percent when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Features ■ Very High Speed ❐ 55 ns ■ Wide Voltage Range ❐ 2.2V to 3.7V ■ Ultra Low Standby Power ❐ Typical Standby Current: 8 μA ❐ Maximum Standby Current: 48 μA ■ Ultra Low Active Power ❐ Typical Active Current: 4.0 mA at f = 1 MHz ■ Easy Memory Expansion with CE1, CE2, and OE Features ■ Automatic Power Down when Deselected ■ CMOS for Optimum Speed and Power ■ Available in Pb-Free 48-Ball FBGA Package To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A21). If Byte High Enable (BHE) is LOW, then data from I/O pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A21). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 9 for a complete description of read and write modes. Functional Description The CY62187EV30 is a high performance CMOS static RAM organized as 4M words by 16 bits[1]. This device features advanced circuit design to provide ultra low active current. It is Logic Block Diagram 4096K × 16 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA-IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 BHE WE OE CE2 CE1 BLE Power-down Circuit Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 001-48998 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 10, 2009 [+] Feedback CY62187EV30 Pin Configuration Figure 1. 48-Ball VFBGA 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A IO 8 BHE A3 A4 CE1 IO 0 B IO 9 IO 10 A5 A6 IO 1 IO 2 C VSS IO11 A17 A7 IO3 Vcc D VCC IO 12 A21 A16 IO 4 Vss E IO 14 IO 13 A14 A15 IO 5 IO 6 F IO 15 A19 A12 A13 WE IO 7 G A18 A8 A9 A10 A11 A20 H Product Portfolio Power Dissipation Product Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62187EV30LL Min Typ[2] Max 2.2 3.0 3.7 Standby ISB2 (μA) f = fMax Typ[2] Max Typ[2] Max Typ[2] Max 55 4.0 6 45 55 8 48 70 4.0 6 35 45 8 48 Note 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 001-48998 Rev. *C Page 2 of 12 [+] Feedback CY62187EV30 DC Input Voltage [3, 4] .................... –0.3V to VCC (max) + 0.3V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Operating Range Supply Voltage to Ground Potential..........................................–0.3V to VCC(max) + 0.3V Device DC Voltage Applied to Outputs in High Z State [3, 4] ........................ –0.3V to VCC (max) + 0.3V CY62187EV30LL Range Ambient Temperature VCC[5] Industrial –40°C to +85°C 2.2V to 3.7V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage 2.2V < VCC < 2.7V IOH = –0.1 mA 2.7V < VCC < 3.7V IOH = –1.0 mA VOL Output LOW Voltage 2.2V < VCC < 2.7V IOL = 0.1 mA 2.7V < VCC < 3.7V IOL = 2.1 mA VIH Input HIGH Voltage 2.2V < VCC < 2.7V VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current f = fMax = 1/tRC Automatic CE Power-Down Current—CMOS Inputs CE1 > VCC – 0.2V or CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 3.7V ISB2 [6] 55 ns Min Typ[2] 70 ns Max 2.0 Min Typ[2] Max 2.0 2.4 Unit V 2.4 V 0.4 0.4 0.4 V 1.8 VCC + 0.3V 1.8 VCC + 0.3V V 2.7V < VCC < 3.7V 2.2 VCC + 0.3V 2.2 VCC + 0.3V V 2.2V< VCC < 2.7V –0.3 0.6 –0.3 0.6 V 2.7V < VCC < 3.7V –0.3 0.7 –0.3 0.7 V –1 +1 –1 +1 μA +1 –1 f = 1 MHz 0.4 V +1 μA 45 55 35 45 mA 4.0 6 4.0 6 mA 8 48 8 48 μA –1 VCC = VCC(max) IOUT = 0 mA CMOS levels Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 25 pF 35 pF Notes 3. VIL(min) = –2.0V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization. 6. Only chip enables (CE1 and CE2) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 001-48998 Rev. *C Page 3 of 12 [+] Feedback CY62187EV30 Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter ΘJA Description Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, 2-layer printed circuit board FBGA 59.06 Unit °C/W 14.08 °C/W Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT VCC GND R2 30 pF 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH V Table 1. AC Test Loads Parameter R1 R2 RTH VTH 2.2V < VCC < 3V 3V < VCC < 3.7V 2.2V to 3.7V 1103 1554 645 VCC/2 1.5 Unit Ω Ω Ω V V Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR [6] tCDR[7] Description VCC for Data Retention Data Retention Current Conditions Typ[2] VCC= 1.5V, CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Chip Deselect to Data Retention Time Operation Recovery Time tR[8] Min 1.5 Max Unit V 48 μA 0 ns tRC ns Figure 3. Data Retention Waveform [9] VCC VCC(min) tCDR DATA RETENTION MODE VDR > 1.5 V VCC(min) tR CE1 or BHE.BLE or CE2 Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs. 9. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 001-48998 Rev. *C Page 4 of 12 [+] Feedback CY62187EV30 Switching Characteristics Over the Operating Range [10] Parameter Description 55 ns Min 70 ns Max Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns 25 ns 55 55 Z[11] tLZOE OE LOW to LOW tHZOE OE HIGH to High Z[11, 12] tLZCE CE1 LOW and CE2 HIGH to Low Z[11] tHZCE CE1 HIGH and CE2 LOW to High Z[11, 12] tPU CE1 LOW and CE2 HIGH to Power Up tPD CE1 HIGH and CE2 LOW to Power Down tDBE BLE/BHE LOW to Data Valid tLZBE BLE/BHE LOW to Low Z [11] tHZBE BLE/BHE HIGH to HIGH Z 70 6 70 6 5 10 ns 10 20 0 ns 25 0 55 55 10 ns ns 70 ns 70 ns 10 20 ns ns 5 20 [11, 12] ns ns 25 ns Write Cycle[13] tWC Write Cycle Time 55 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 45 60 ns tAW Address Setup to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Setup to Write Start 0 0 ns tPWE WE Pulse Width 40 50 ns tBW BLE/BHE LOW to Write End 45 60 ns tSD Data Setup to Write End 25 35 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High-Z[11, 12] tLZWE WE HIGH to Low-Z[11] 0 20 10 ns 25 10 ns ns Notes 10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns, timing reference levels of VTH, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads on page 4. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 13. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 001-48998 Rev. *C Page 5 of 12 [+] Feedback CY62187EV30 Switching Waveforms Figure 4. Read Cycle 1 (Address Transition Controlled)[14, 15] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle 2 (OE Controlled)[15, 16] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tLZBE tDBE tHZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB Notes 14. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 001-48998 Rev. *C Page 6 of 12 [+] Feedback CY62187EV30 Switching Waveforms (continued) Figure 6. Write Cycle 1 (WE Controlled) [13, 17, 18, 19] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA IO tHD VALID DATA NOTE 19 tHZOE Figure 7. Write Cycle 2 (CE1 or CE2 Controlled) [13, 17, 18, 19] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA IO tHD VALID DATA NOTE 19 tHZOE Notes 17. Data I/O is high impedance if OE = VIH. 18. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 19. During this period the I/Os are in output state and input signals should not be applied. Document #: 001-48998 Rev. *C Page 7 of 12 [+] Feedback CY62187EV30 Switching Waveforms (continued) Figure 8. Write Cycle 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tHA tSA WE tPWE tHD tSD DATA IO NOTE 19 VALID DATA tLZWE tHZWE Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18,19] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA IO NOTE 19 Document #: 001-48998 Rev. *C tHD VALID DATA Page 8 of 12 [+] Feedback CY62187EV30 Truth Table CE1 WE OE BHE BLE X [20] Mode Power X X X X High Z Deselect/Power Down Standby (ISB) L X X X X [20] X High Z Deselect/Power Down Standby (ISB) X X H H High Z Deselect/Power Down Standby (ISB) L H H L L L Data Out (IO0–IO15) Read Active (ICC) L H H L H L High Z (IO8–IO15): Data Out (IO0–IO7) Read Active (ICC) L H H L L H Data Out (IO8–IO15); High Z (IO0–IO7) Read Active (ICC) L H L X L L Data In (IO0–IO15) Write Active (ICC) L H L X H L High Z (IO8–IO15); Data In (IO0–IO7) Write Active (ICC) L H L X L H Data In (IO8–IO15); High Z (IO0–IO7) Write Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) H CE2 X[20] X [20] Inputs Outputs Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 55 CY62187EV30LL-55BAXI 001-50044 48-Ball Fine Pitch Ball Grid Array (8 x 9.5 x 1.4 mm) Pb-Free Industrial 70 CY62187EV30LL-70BAXI 001-50044 48-Ball Fine Pitch Ball Grid Array (8 x 9.5 x 1.4 mm) Pb-Free Industrial Note 20. The ‘X’ (Don’t care) state for the chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 001-48998 Rev. *C Page 9 of 12 [+] Feedback CY62187EV30 Package Diagrams Figure 10. 48-Ball FBGA (8 x 9.5 x 1.4 mm) (001-50044) 001-50044 - *A Document #: 001-48998 Rev. *C Page 10 of 12 [+] Feedback CY62187EV30 Document History Page Document Title: CY62187EV30 MoBL® 64 Mbit (4M x 16) Static RAM Document Number: 001-48998 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 2595932 VKN/PYRS 10/24/08 New Data Sheet *A 2644442 VKN/PYRS 01/23/09 Updated the Package diagram on page 10 *B 2672650 VKN/PYRS 03/12/09 Extended the VCC range to 3.7V Added 55 ns speed bin and it’s related information Changed ICC (typ) from 2.5 mA to 3.5 mA at f = 1 MHz Changed ICC (max) from 4 mA to 6 mA at f = 1 MHz For 70 ns speed, changed ICC (typ) form 33 mA to 28 mA at f = fMAX For 70 ns speed, changed ICC (max) from 40 mA to 45 mA at f = fMAX For 70 ns speed, changed tPWE from 45 to 50 ns, tSD from 30 to 35 ns Modified footnote #6 Changed 48-Ball FBGA package dimensions from 8 x 9.5 x 1.6 mm to 8 x 9.5 x 1.4 mm and updated package diagram on page 10 *C 2737164 VKN/AESA 07/13/09 Converted from preliminary to final Changed ICC(typ) from 3.5 mA to 4 mA at f = 1 MHz Changed ICC(typ) from 35 mA to 45 mA and from 28 mA to 35 mA for the speeds 50 ns and 70 ns respectively at f = fmax Included VCC range in the test condition of the “Electrical Characteristics” table for the specs VOH, VOL, VIH, VIL Changed VIL(max) from 0.8V to 0.7V for VCC = 2.7V to 3.7V Changed CIN spec from 20 pF to 25 pF and COUT spec from 20 pF to 35 pF Included thermal specs for 48-FBGA Included VCC range for VTH spec in the AC test load table Changed tLZBE spec from 5 ns to 10 ns Added footnote #20 related to chip enable Document #: 001-48998 Rev. *C Page 11 of 12 [+] Feedback CY62187EV30 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at www.cypress.com/sales. Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-48998 Rev. *C Revised July 10, 2009 Page 12 of 12 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback