TI SN74ABTH32543MPZEP

SN74ABTH32543-EP
36-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS757 – AUGUST 2002
D
D
D
D
D
D
D
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree†
Member of the Texas Instruments
Widebus+ Family
D
D
D
D
D
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 5 V, TA = 25°C
High-Impedance State During Power Up
and Power Down
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
100-Pin Plastic Thin Quad Flat (PZ)
Package With 14- × 14-mm Body Using
0.5-mm Lead Pitch
description
The ’ABTH32543 is a 36-bit registered transceiver that contains two sets of D-type latches for temporary storage
of data flowing in either direction. This device can be used as two 18-bit transceivers or one 36-bit transceiver.
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each
register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and
OEBA inputs.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–55°C to 125°C
LQFP – PZ
SN74ABTH32543MPZEP
74ABTH32543MEP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ and EPIC-ΙΙB are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ABTH32543-EP
36-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS757 – AUGUST 2002
1A8
1A7
1A6
GND
1A5
1A4
1A3
1A2
1A1
1CEBA
1OEBA
1LEBA
VCC
1LEAB
1OEAB
1CEAB
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
PZ PACKAGE
(TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1A9
1A10
GND
1A11
1A12
1A13
1A14
GND
1A15
1A16
1A17
1A18
VCC
2A1
2A2
2A3
2A4
GND
2A5
2A6
2A7
2A8
GND
2A9
2A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2A11
2A12
2A13
GND
2A14
2A15
2A16
2A17
2A18
2CEBA
2OEBA
2LEBA
VCC
2LEAB
2OEAB
2CEAB
2B18
2B17
2B16
2B15
2B14
GND
2B13
2B12
2B11
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FUNCTION TABLE†
(each 18-bit section)
INPUTS
OEAB
A
OUTPUT
B
X
X
X
Z
X
H
X
Z
L
H
L
X
L
L
L
L
B0‡
L
L
L
L
H
CEAB
LEAB
H
X
H
† A-to-B data flow is shown; B-to-A flow control is the
same, except that it uses CEBA, LEBA, and
OEBA.
‡ Output level before the indicated steady-state
input conditions were established
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1B9
1B10
GND
1B11
1B12
1B13
1B14
GND
1B15
1B16
1B17
1B18
VCC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
2B8
GND
2B9
2B10
SN74ABTH32543-EP
36-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS757 – AUGUST 2002
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
90
91
89
86
85
87
C1
92
1D
84
1B1
C1
1D
To 17 Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
36
35
37
40
41
39
C1
14
1D
62
2B1
C1
1D
To 17 Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ABTH32543-EP
36-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS757 – AUGUST 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): PZ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MAX
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–24
mA
Low-level output current
48
mA
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
High-level input voltage
2
Input voltage
0
Outputs enabled
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
V
0.8
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
4
MIN
10
V
V
ns/V
µs/V
125
°C
SN74ABTH32543-EP
36-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS757 – AUGUST 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = – 3 mA
VOH
VCC = 5 V,
VCC = 4.5 V
IOH = – 3 mA
IOH = – 24 mA
VCC = 4.5 V
IOL = 48 mA
VOL
Vhys
MAX
UNIT
–1.2
V
2.5
V
3
2
0.55
100
Control inputs
II
TYP†
A or B ports
VCC = 5
5.5
5V
V,
IOZPU‡
IOZPD‡
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X
ICEX
IO§
VCC = 5.5 V, VO = 5.5 V
VCC = 5.5 V,
ICC
VCC = 5.5
5 5 V,
V IO = 0,
0
VI = VCC or GND
∆ICC¶
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Ci
Control inputs
Cio
A or B ports
±1
VI = VCC or GND
±20
Outputs high
VO = 2.5 V
Outputs high
–50
–100
µA
±50
µA
±50
µA
50
µA
–180
mA
3
Outputs low
20
Outputs disabled
mA
2
1
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
V
mV
mA
3.5
pF
9.5
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This parameter is specified by characterization.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
MIN
tw
Pulse duration, LEAB or LEBA low
tsu
Setup time
th
Hold time
3.3
Data before LEAB↑ or LEBA↑
Data before CEAB↑ or CEBA↑
POST OFFICE BOX 655303
2.6
2
Data after LEAB↑ or LEBA↑
1.1
Data after CEAB↑ or CEBA↑
1.2
• DALLAS, TEXAS 75265
MAX
UNIT
ns
ns
ns
5
SN74ABTH32543-EP
36-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS757 – AUGUST 2002
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LE
A or B
tPZH
tPZL
CE
A or B
tPHZ
tPLZ
CE
A or B
tPZH
tPZL
OE
A or B
tPHZ
tPLZ
OE
A or B
PARAMETER
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
0.5
6.3
0.5
5.9
0.8
7.9
0.8
6.9
0.8
8.3
1
8.8
0.5
7.4
1
7.9
0.5
7.6
1
8.2
0.5
6.7
0.8
7.2
UNIT
ns
ns
ns
ns
ns
ns
SN74ABTH32543-EP
36-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCBS757 – AUGUST 2002
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
Data Input
0V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
1.5 V
Input
Output
Control
1.5 V
0V
1.5 V
VOL
VOH
Output
1.5 V
tPLZ
3.5 V
1.5 V
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
1.5 V
0V
Output
Waveform 1
S1 at 7 V
(see Note B)
VOH
1.5 V
Output
1.5 V
tPZL
tPHL
tPLH
1.5 V
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
SN74ABTH32543MPZEP
OBSOLETE
LQFP
PZ
Pins Package Eco Plan (2)
Qty
100
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74ABTH32543-EP :
SN74ABTH32543
• Catalog:
• Military: SN54ABTH32543
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
• Military - QML certified for Military and Defense Applications
Addendum-Page 1
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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