16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter AD9467 Data Sheet FUNCTIONAL BLOCK DIAGRAM 75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS SFDR at 170 MHz at 250 MSPS 92 dBFS at −1 dBFS 100 dBFS at −2 dBFS 60 fs rms jitter Excellent linearity at 250 MSPS DNL = ±0.5 LSB typical INL = ±3.5 LSB typical 2 V p-p to 2.5 V p-p (default) differential full-scale input (programmable) Integrated input buffer External reference support option Clock duty cycle stabilizer Output clock available Serial port control Built-in selectable digital test pattern generation Selectable output data format LVDS outputs (ANSI-644 compatible) 1.8 V and 3.3 V supply operation AVDD1 (1.8V) AVDD2 (3.3V) AVDD3 (1.8V) CSB AD9467 SDIO BUFFER SCLK VIN+ PIPELINE ADC VIN– CLK+ CLK– CLOCK AND TIMING MANAGEMENT 16 2 LVDS OUTPUT STAGING 16 2 OR+/OR– D15+/D15– TO D0+/D0– DCO+/DCO– REF AGND XVREF DRGND Figure 1. A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. APPLICATIONS Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Communications instrumentation The internal power-down feature supported via the SPI typically consumes less than 5 mW when disabled. Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9467 is a 16-bit, monolithic, IF sampling analog-todigital converter (ADC). It is optimized for high performance over wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range. 1. 2. The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances. Rev. D SPIVDD DRVDD (1.8V TO 3.3V) (1.8V) 3. 4. 5. 6. IF optimization capability used to improve SFDR. Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers. Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture. Packaged in a Pb-free, 72-lead LFCSP package. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths. Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 09029-001 FEATURES AD9467 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Equivalent Circuits ......................................................................... 11 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 12 General Description ......................................................................... 1 Theory of Operation ...................................................................... 19 Functional Block Diagram .............................................................. 1 Analog Input Considerations ................................................... 19 Product Highlights ........................................................................... 1 Clock Input Considerations ...................................................... 22 Revision History ............................................................................... 2 Serial Port Interface (SPI) .............................................................. 26 Specifications..................................................................................... 3 Hardware Interface ..................................................................... 26 AC Specifications.......................................................................... 4 Memory Map .................................................................................. 28 Digital Specifications ................................................................... 6 Reading the Memory Map Table .............................................. 28 Switching Specifications .............................................................. 7 Reserved Locations .................................................................... 28 Absolute Maximum Ratings ............................................................ 8 Default Values ............................................................................. 28 Thermal Impedance ..................................................................... 8 Logic Levels ................................................................................. 28 ESD Caution .................................................................................. 8 Outline Dimensions ....................................................................... 32 Pin Configuration and Function Descriptions ............................. 9 Ordering Guide .......................................................................... 32 REVISION HISTORY 2/13—Rev. C to Rev. D Changes to Figure 1 .......................................................................... 1 Changes to Figure 2 .......................................................................... 7 Changes to VIN+, VIN− Parameter Rating, Table 5 ................... 8 Changes to Figure 51, Figure 52, and Figure 53 ......................... 20 Changes to Figure 54 and Figure 56............................................. 21 Changes to Digital Outputs and Timing Section ....................... 24 Deleted Addr. (Hex) 17 Row, Table 13......................................... 29 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 9/11—Rev. B to Rev. C Changes to Figure 44 and Figure 45............................................. 17 2/11—Rev. 0 to Rev. A Changes to Features Section ............................................................1 Added Figure 24 and Figure 25; Renumbered Sequentially ..... 14 Changes to Differential Configurations Section and Figure 54 .......................................................................................... 21 Added Figure 55 to Figure 57 ....................................................... 21 Changes to Figure 65 and Figure 66 ............................................ 24 Changes to Addr. (Hex) 15, Bits[2:0], Addr. (Hex) 10, Bits[7:0], and Addr. (Hex) 10, Default Notes Column ............................... 29 Changes to Addr. (Hex) 36, Default Value (Hex) Column and Addr. (Hex) 107, Default Value (Hex) Column ......................... 30 10/10—Revision 0: Initial Version 3/11—Rev. A to Rev. B Change Parameter Name to Full Power Bandwidth, Table 1...... 3 Changes to Switching Specifications, Table 4 ............................... 7 Change to VIN+, VIN− Parameter, Table 5 .................................. 8 Deleted Figure 43 ............................................................................ 17 Added New Figure 43..................................................................... 17 Rev. D | Page 2 of 32 Data Sheet AD9467 SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 1. AD9467BCPZ-200 Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error ANALOG INPUTS Differential Input Voltage Range (Internal VREF = 1 V to 1.25 V) Common-Mode Voltage Differential Input Resistance Differential Input Capacitance Full Power Bandwidth XVREF INPUT Input Voltage Input Capacitance POWER SUPPLY AVDD1 AVDD2 AVDD3 DRVDD IAVDD1 IAVDD2 IAVDD3 IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation 1 2 Temp Full Full Full Full Full Min 16 −150 −3.5 −0.8 −9.5 Full Full Full Full Full Full Full Full Full Full Full Full Full Max Guaranteed 0 +150 −0.2 +2.5 ±0.4 +0.7 ±5 +9.5 AD9467BCPZ-250 Min 16 −150 −3.5 −0.6 −11.8 ±0.020 ±0.011 2 25°C 25°C 25°C 25°C Full Full Typ 2.5 2.3 530 3.5 900 1 Max Guaranteed 0 +150 −0.1 +2.5 ±0.5 +1.3 ±3.5 +9.5 ±0.023 ±0.036 2.5 2 1.25 1 3 1.75 3.0 1.7 1.7 485 49 21 35 1.14 Typ 2.5 2.15 530 3.5 900 1.85 3.6 1.9 1.9 580 61 27 41 1.37 90 1.75 3.0 1.7 1.7 514 49 27 36 1.2 1.8 3.3 1.8 1.8 567 55 31 40 1.33 4.4 LSB %FSR LSB LSB %FSR/°C %FSR/°C 2.5 V p-p V Ω pF MHz 1.25 V pF 3 1.8 3.3 1.8 1.8 536 55 24 38 1.26 4.4 Unit Bits 1.85 3.6 1.9 1.9 618 61 35 43 1.45 90 V V V V mA mA mA mA W mW See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Rev. D | Page 3 of 32 AD9467 Data Sheet AC SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 2. Parameter 1 ANALOG INPUT FULL SCALE SIGNAL-TO-NOISE RATIO (SNR) fIN = 5 MHz fIN = 97 MHz fIN = 97 MHz fIN = 140 MHz fIN = 170 MHz fIN = 170 MHz fIN = 210 MHz fIN = 300 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 5 MHz fIN = 97 MHz fIN = 97 MHz fIN = 140 MHz fIN = 170 MHz fIN = 170 MHz fIN = 210 MHz fIN = 300 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 5 MHz fIN = 97 MHz fIN = 97 MHz fIN = 140 MHz fIN = 170 MHz fIN = 170 MHz fIN = 210 MHz fIN = 300 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) (INCLUDING SECOND AND THIRD HARMONIC DISTORTION) 2 fIN = 5 MHz fIN = 97 MHz fIN = 97 MHz fIN = 140 MHz fIN = 170 MHz fIN = 170 MHz fIN = 210 MHz fIN = 300 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) (INCLUDING SECOND AND THIRD HARMONIC DISTORTION)2 fIN = 5 MHz @ −2 dB Full Scale fIN = 97 MHz @ −2 dB Full Scale fIN = 140 MHz @ −2 dB Full Scale fIN = 170 MHz @ −2 dB Full Scale fIN = 210 MHz @ −2 dB Full Scale fIN = 300 MHz @ −2 dB Full Scale Temp 25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C Full 25°C 25°C Min 2.5 75.1 73.8 74.7 73.1 Full Full Full Full Full Full AD9467BCPZ-250 Typ Max 2/2.5 74.7/76.4 74.5/76.1 74.7 72.3 74.4/76.0 74.3/75.8 73.9/75.5 73.5/74.7 74.0/75.5 73.3/74.6 74.6/76.3 74.5/76.2 74.6/76.3 74.4/76.0 74.3/75.9 74.1/75.6 86 83 Min 2.5 74.6/76.4 74.5/76.2 74.3/76.0 74.2/75.8 25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C Full 25°C 25°C AD9467BCPZ-200 Typ Max 2/2.5 74.4 71.8 74.4/76.0 74.2/75.8 73.9/75.3 73.3/74.3 73.9/75.4 73.1/74.4 12.1/12.4 12.1/12.4 12.1/12.4 12.1/12.3 12.1/12.3 12.0/12.3 12.1/12.3 12.0/12.3 12.0/12.2 11.9/12.0 12.0/12.2 11.9/12.1 95/95 95/95 98/97 95/93 Unit V p-p dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits Bits Bits Bits 93/88 92/86 93/92 93/90 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 100/96 100/98 98/96 96/93 94/93 90/89 100/100 97/97 100/95 100/100 93/93 90/90 dBFS dBFS dBFS dBFS dBFS dBFS 94/93 95/90 Rev. D | Page 4 of 32 84 84 94/95 93/92 Data Sheet Parameter 1 WORST OTHER (EXCLUDING SECOND AND THIRD HARMONIC DISTORTION)2 fIN = 5 MHz fIN = 97 MHz fIN = 97 MHz fIN = 140 MHz fIN = 170 MHz fIN = 170 MHz fIN = 210 MHz fIN = 300 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS @ 2.5 V p-p FS fIN1 = 70 MHz, fIN2 = 72 MHz fIN1 = 170 MHz, fIN2 = 172 MHz 1 2 AD9467 Temp 25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C Min 86 83 AD9467BCPZ-200 Typ Max Min 96/98 97/97 AD9467BCPZ-250 Typ Max 96/97 95/95 97/95 97/95 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 95 93 97 91 dBFS dBFS 97/96 98/98 98/97 97/93 Unit 90 87 97/95 97/93 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. See the SFDR Optimization—Buffer Current Adjustment section for optimum settings. Rev. D | Page 5 of 32 AD9467 Data Sheet DIGITAL SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 3. AD9467BCPZ-200 Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (SCLK, CSB, SDIO) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO) 3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D0+ to D15+, D0− to D15−, DCO+, DCO−, OR+, OR−) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 3 Temp Min Full Full 25°C 25°C 250 Full Full 25°C 25°C 1.2 Typ Max AD9467BCPZ-250 Min CMOS/LVDS/LVPECL Max 0.8 20 2.5 mV p-p V kΩ pF 0.8 20 2.5 3.6 0.3 1.2 30 0.5 3.6 0.3 30 0.5 1.7/3.1 1.7/3.1 0.3 0.3 LVDS 247 1.125 V V kΩ pF V V LVDS 545 1.375 Offset binary Unit CMOS/LVDS/LVPECL 250 Full Full Full Full Typ 247 1.125 545 1.375 mV V Offset binary See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This is specified for LVDS and LVPECL only. This depends on if SPIVDD is tied to a 1.8 V or 3.3 V supply. Rev. D | Page 6 of 32 Data Sheet AD9467 SWITCHING SPECIFICATIONS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted. Table 4. Parameter 1 CLOCK 2 Clock Rate Clock Pulse Width High (tCH) Clock Pulse Width Low (tCL) OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) DCO to Data Delay (tSKEW) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time 1 2 3 Temp Min Full Full Full 50 25°C 25°C 25°C 25°C Full Full Full AD9467BCPZ-200 Typ Max Min 200 50 250 2.5 2.5 2 2 3 200 200 3 3 200 200 3 Unit MSPS ns ns 100 16 100 16 ns ps ps ns ps ms Clock cycles 1.2 60 1 1.2 60 1 ns fs rms Clock cycles −200 +200 25°C 25°C 25°C AD9467BCPZ-250 Typ Max −200 +200 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Can be adjusted via the SPI interface. Measurements were made using a part soldered to FR-4 material. Timing Diagrams N–1 N+4 tA N+5 N N+3 VIN± N+1 tCH tCL N+2 1/fs CLK+ CLK– tCPD DCO+ DCO– tSKEW tPD D15–/D14– (MSB) D15 D14 N – 16 N – 16 N – 15 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 10 D1 D0 N – 16 N – 16 N – 15 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 10 D1–/D0– (LSB) D1+/D0+ (LSB) Figure 2. 16-Bit Output Data Timing Rev. D | Page 7 of 32 09029-002 D15+/D14+ (MSB) .. . AD9467 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Electrical AVDD1, AVDD3 AVDD2, SPIVDD DRVDD AGND AVDD2, SPIVDD AVDD1, AVDD3 AVDD2, SPIVDD Digital Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−) CLK+, CLK− VIN+, VIN− XVREF SCLK, CSB, SDIO Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating AGND AGND DRGND DRGND AVDD1, AVDD3 DRVDD DRVDD DRGND −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +3.9 V AGND AGND AGND AGND −0.3 V to AVDD1 + 0.2 V −0.3 V to +3.6 V −0.3 V to AVDD1 + 0.2 V −0.3 V to SPIVDD + 0.2 V THERMAL IMPEDANCE −2.0 V to +2.0 V −2.0 V to +3.9 V −0.3 V to DRVDD + 0.2 V −40°C to +85°C 150°C Table 6. Air Flow Velocity (m/sec) 0.0 1.0 2.5 θJA1, 2 15.7°C/W 13.7°C/W 12.3°C/W θJB1, 3, 4 7.5°C/W N/A N/A Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per JEDEC JESD51-8 (still air). 4 N/A = not applicable. 5 Per MIL-STD 883, Method 1012.1. 1 2 ESD CAUTION 300°C −65°C to +150°C Rev. D | Page 8 of 32 θJC1, 5 0.5° N/A N/A Unit °C/W °C/W °C/W Data Sheet AD9467 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD1 AVDD1 AVDD1 AVDD2 AVDD2 VIN– VIN+ AVDD2 AVDD2 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 XVREF AVDD1 AVDD1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9467 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 AVDD1 AVDD1 AVDD1 SPIVDD CSB SCLK SDIO DNC AVDD1 AGND AVDD3 AGND AVDD3 AGND OR+ OR– DRGND DRVDD NOTES 1. DNC = DO NOT CONNECT. 2. EXPOSED THERMAL PAD MUST BE CONNECTED TO AGND. 09029-003 D1–/D0– D1+/D0+ D3–/D2– D3+/D2+ D5–/D4– D5+/D4+ D7–/D6– D7+/D6+ DCO– DCO+ D9–/D8– D9+/D8+ D11–/D10– D11+/D10+ D13–/D12– D13+/D12+ D15–/D14– D15+/D14+ 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AVDD1 AVDD1 AVDD1 AVDD1 CLK+ CLK– AVDD1 AVDD1 AVDD1 AGND AVDD1 AVDD1 AVDD1 AGND AVDD1 AGND DRGND DRVDD Figure 3. Pin Configuration, Top View Table 7. Pin Function Descriptions Pin No. 0 10, 14, 16, 41, 43, 45 1, 2, 3, 4, 7, 8, 9, 11, 12, 13, 15, 46, 52, 53, 54, 55, 56, 58, 59, 60, 61, 62, 63, 70, 71, 72 64, 65, 68, 69 42, 44 51 17, 38 18, 37 67 66 6 5 19 20 21 22 23 24 25 26 29 30 31 32 33 34 35 Mnemonic EPAD AGND AVDD1 Description Exposed Paddle. The exposed paddle must be connected to AGND. Analog Ground. 1.8 V Analog Supply. AVDD2 AVDD3 SPIVDD DRGND DRVDD VIN− VIN+ CLK− CLK+ D1−/D0− D1+/D0+ D3−/D2− D3+/D2+ D5−/D4− D5+/D4+ D7−/D6− D7+/D6+ D9−/D8− D9+/D8+ D11−/D10− D11+/D10+ D13−/D12− D13+/D12+ D15−/D14− 3.3 V Analog Supply. 1.8 V Analog Supply. 1.8 V or 3.3 V SPI Supply Digital Output Driver Ground. 1.8 V Digital Output Driver Supply. Analog Input Complement. Analog Input True. Clock Input Complement. Clock Input True. D1 and D0 (LSB) Digital Output Complement. D1 and D0 (LSB) Digital Output True. D3 and D2 Digital Output Complement. D3 and D2 Digital Output True. D5 and D4 Digital Output Complement. D5 and D4 Digital Output True. D7 and D6 Digital Output Complement. D7 and D6 Digital Output True. D9 and D8 Digital Output Complement. D9 and D8 Digital Output True. D11 and D10 Digital Output Complement. D11 and D10 Digital Output True. D13 and D12 Digital Output Complement. D13 and D12 Digital Output True. D15 (MSB) and D14 Digital Output Complement. Rev. D | Page 9 of 32 AD9467 Pin No. 36 27 28 39 40 47 48 49 50 57 Data Sheet Mnemonic D15+/D14+ DCO− DCO+ OR− OR+ DNC SDIO SCLK CSB XVREF Description D15 (MSB) and D14 Digital Output True. Data Clock Digital Output Complement. Data Clock Digital Output True. Out-of-Range Digital Output Complement. Out-of-Range Digital Output True. Do Not Connect (Leave Pin Floating). Serial Data Input/Output. Serial Clock. Chip Select Bar. External VREF Option. Rev. D | Page 10 of 32 Data Sheet AD9467 EQUIVALENT CIRCUITS AVDD2 VIN+ AVDD2 BUF 265Ω 345Ω SCLK, SDIO AND CSB VCML 2.15V/2.30V BUF AVDD2 30kΩ 265Ω VIN– 09029-004 09029-008 BUF Figure 7. Equivalent SCLK, SDIO, and CSB Input Circuit Figure 4. Equivalent Analog Input Circuit AVDD1 SPIVDD 10kΩ 10kΩ 0.8V 10kΩ CLK+ 10kΩ CLK– 09029-005 09029-011 SDIO Figure 8. Equivalent SDIO Output Circuit Figure 5. Equivalent Clock Input Circuit DRVDD V V Dx+ V DRGND XVREF 09029-007 V 1kΩ 3pF 09029-109 Dx– Figure 9. Equivalent External VREF Input Circuit (When Enabled) Figure 6. Equivalent Digital Output Circuit Rev. D | Page 11 of 32 AD9467 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default SPI settings, unless otherwise noted, buffer current optimized for best SFDR performance. 0 0 AIN = –1.0dBFS SNR = 76.5dBFS ENOB = 12.4 BITS SFDR = 95.4dBFS –60 –80 –80 –100 –120 –120 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 –140 0 100 Figure 10. Single-Tone FFT with fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-200 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 Figure 13. Single-Tone FFT with fIN = 170.3 MHz, 2.5 V p-p FS, AD9467-200 0 0 AIN = –1.0dBFS SNR = 76.2dBFS ENOB = 12.3 BITS SFDR = 92.0dBFS AMPLITUDE (dBFS) –40 –60 –80 –40 –60 –80 –100 –120 –120 09029-111 –100 –140 0 10 20 30 40 50 60 70 FREQUENCY (MHz) AIN = –1.0dBFS SNR = 75.5dBFS ENOB = 12.1 BITS SFDR = 90.0dBFS –20 80 90 09029-114 –20 –140 100 0 Figure 11. Single-Tone FFT with fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-200 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 Figure 14. Single-Tone FFT with fIN = 210.3 MHz, 2.5 V p-p FS, AD9467-200 0 0 AIN = –1.0dBFS SNR = 75.9dBFS ENOB = 12.3 BITS SFDR = 95.2dBFS –20 AIN = –1.0dBFS SNR = 74.7dBFS ENOB = 12.0 BITS SFDR = 86.5dBFS –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –40 –60 –80 –100 –120 09029-112 –120 –140 0 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 09029-115 AMPLITUDE (dBFS) –60 –100 0 AMPLITUDE (dBFS) –40 09029-113 AMPLITUDE (dBFS) –40 –140 AIN = –1.0dBFS SNR = 75.8dBFS ENOB = 12.3 BITS SFDR = 94.1dBFS –20 09029-110 AMPLITUDE (dBFS) –20 –140 100 0 Figure 12. Single-Tone FFT with fIN = 140.3 MHz, 2.5 V p-p FS, AD9467-200 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 Figure 15. Single-Tone FFT with fIN = 290.3 MHz, 2.5 V p-p FS, AD9467-200 Rev. D | Page 12 of 32 Data Sheet AD9467 0 0 AIN = –1.0dBFS SNR = 76.4dBFS ENOB = 12.4 BITS SFDR = 100.0dBFS –60 –80 –80 –100 –120 –120 20 40 60 80 FREQUENCY (MHz) 100 –140 0 120 Figure 16. Single-Tone FFT with fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-250 20 40 60 80 FREQUENCY (MHz) 100 120 Figure 19. Single-Tone FFT with fIN = 170.3 MHz, 2.5 V p-p FS, AD9467-250 0 0 AIN = –1.0dBFS SNR = 75.9dBFS ENOB = 12.3 BITS SFDR = 94.8dBFS AMPLITUDE (dBFS) –40 –60 –80 –40 –60 –80 –100 –120 –120 09029-117 –100 –140 0 20 40 AIN = –1.0dBFS SNR = 75.5dBFS ENOB = 12.1 BITS SFDR = 90.8dBFS –20 60 80 FREQUENCY (MHz) 100 09029-120 –20 –140 0 120 Figure 17. Single-Tone FFT with fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-250 20 40 60 80 FREQUENCY (MHz) 100 120 Figure 20. Single-Tone FFT with fIN = 210.3 MHz, 2.5 V p-p FS, AD9467-250 0 0 AIN = –1.0dBFS SNR = 76.0dBFS ENOB = 12.2 BITS SFDR = 93.6dBFS –20 AMPLITUDE (dBFS) –40 –60 –80 –40 –60 –80 –100 –120 –120 09029-118 –100 –140 0 20 40 AIN = –1.0dBFS SNR = 74.2dBFS ENOB = 12.0 BITS SFDR = 91.0dBFS –20 60 80 FREQUENCY (MHz) 100 09029-121 AMPLITUDE (dBFS) –60 –100 0 AMPLITUDE (dBFS) –40 09029-119 AMPLITUDE (dBFS) –40 –140 AIN = –1.0dBFS SNR = 75.8dBFS ENOB = 12.2 BITS SFDR = 94.1dBFS –20 09029-116 AMPLITUDE (dBFS) –20 –140 0 120 Figure 18. Single-Tone FFT with fIN = 140.3 MHz, 2.5 V p-p FS, AD9467-250 20 40 60 80 FREQUENCY (MHz) 100 120 Figure 21. Single-Tone FFT with fIN = 300.3 MHz, 2.5 V p-p FS, AD9467-250 Rev. D | Page 13 of 32 AD9467 Data Sheet 78 110 77 105 100 SNR 96 100 76 94 75 90 74 85 SFDR (dBFS) 95 SFDR (dBFS) SFDR SNR (dBFS) fIN = 4.3MHz fIN = 97.3MHz fIN = 170.3MHz fIN = 300.3MHz 98 92 90 88 86 73 80 84 75 200 70 220 80 160 SAMPLE RATE (MSPS) 110 77 105 190 200 210 220 230 240 250 Figure 25. SFDR vs. fSAMPLE, 2.5 V p-p FS, AD9467-250 78 110 77 105 100 76 90 74 85 73 SNR (dBFS) SFDR SFDR (dBFS) 95 75 72 220 225 230 240 235 245 90 74 75 72 70 250 71 09029-125 215 95 75 SAMPLE RATE (MSPS) 80 75 70 0 50 100 150 200 250 300 ANALOG INPUT FREQUENCY (MHz) Figure 23. SNR/SFDR vs. fSAMPLE, fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-250 Figure 26. SNR/SFDR vs. fIN, 2.0/2.5 V p-p FS, AD9467-200 105 fIN = 4.3MHz fIN = 97.3MHz fIN = 170.3MHz fIN = 290.3MHz 100 85 SNR = 2.0V p-p FS SNR = 2.5V p-p FS SFDR = 2.0V p-p FS SFDR = 2.5V p-p FS 73 80 71 210 100 76 SNR SNR (dBFS) 180 SAMPLE RATE (MSPS) Figure 22. SNR/SFDR vs. fSAMPLE, fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-200 78 170 78 110 77 105 100 SNR (dBFS) 90 95 75 90 74 85 SNR = 2.0V p-p FS SNR = 2.5V p-p FS SFDR = 2.0V p-p FS SFDR = 2.5V p-p FS 73 85 80 72 80 100 120 140 160 180 200 220 SAMPLE RATE (MSPS) 75 70 71 09029-224 SFDR (dBFS) 76 95 09029-225 180 SFDR (dBFS) 160 09029-126 140 0 50 100 150 200 250 300 ANALOG INPUT FREQUENCY (MHz) Figure 24. SFDR vs. fSAMPLE, 2.5 V p-p FS, AD9467-200 Figure 27. SNR/SFDR vs. fIN, 2.0/2.5 V p-p FS, AD9467-250 Rev. D | Page 14 of 32 SFDR (dBFS) 120 09029-123 71 100 82 09029-127 72 Data Sheet AD9467 0 0 AIN1 AND AIN2 = –7dBFS SFDR = 94.6dBFS IMD2 = 94.6dBFS IMD3 = 95.9dBFS –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 10 20 30 40 50 60 70 FREQUENCY (MHz) 80 90 100 –140 0 Figure 28. Two-Tone FFT with fIN1 = 70 MHz and fIN2 = 72 MHz, 2.5 V p-p FS, AD9467-200 20 40 60 80 FREQUENCY (MHz) 120 Figure 31. Two-Tone FFT with fIN1 = 170 MHz and fIN2 = 172 MHz, 2.5 V p-p FS, AD9467-250 120 0 AIN1 AND AIN2 = –7dBFS SFDR = 92.7dBFS IMD2 = 98.2dBFS IMD3 = 92.7dBFS –20 100 SNR/SFDR (dB) –40 –60 –80 80 60 SNR FS SFDR FS SFDR dBc SNR dBc 40 –100 20 –120 –1 ANALOG INPUT LEVEL (dBFS) 09029-132 –3 –5 –7 –9 –11 –13 –15 –17 0 –19 100 –21 90 –23 80 –25 40 50 60 70 FREQUENCY (MHz) –35 30 –45 20 –55 10 –65 0 09029-129 –140 Figure 32. SNR/SFDR vs. Analog Input Level, fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 29. Two-Tone FFT with fIN1 = 170 MHz and fIN2 = 172 MHz, 2.5 V p-p FS, AD9467-200 120 0 AIN1 AND AIN2 = –7dBFS SFDR = 96.7dBFS IMD2 = 103.2dBFS IMD3 = 96.7dBFS –20 100 SNR/SFDR (dB) –40 –60 –80 80 60 SFDR FS SFDR dBc SNR FS SNR dBc 40 –100 20 Figure 30. Two-Tone FFT with fIN1 = 70 MHz and fIN2 = 72 MHz, 2.5 V p-p FS, AD9467-250 –1 –3 –5 09029-133 ANALOG INPUT LEVEL (dBFS) –7 –9 –13 –15 –17 –19 0 –21 120 –23 100 –25 60 80 FREQUENCY (MHz) –35 40 –45 20 –55 0 –65 –140 –11 –120 09029-130 AMPLITUDE (dBFS) 100 09029-131 0 09029-128 –140 AMPLITUDE (dBFS) AIN1 AND AIN2 = –7dBFS SFDR = 91.3dBFS IMD2 = 96.3dBFS IMD3 = 91.3dBFS –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 Figure 33. SNR/SFDR vs. Analog Input Level, fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-250 Rev. D | Page 15 of 32 AD9467 Data Sheet 100 0.8 SFDR 0.6 DNL ERROR (LSB) SNR/SFDR (dBFS) 95 90 85 80 0.4 0.2 0 –0.2 –0.4 SINAD –0.6 09029-137 75 60000 54000 48000 42000 36000 30000 24000 18000 12000 TEMPERATURE (°C) 09029-134 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 70 6000 –0.8 CODE Figure 34. SINAD/SFDR vs. Temperature, fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 37. DNL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-200 8 100 SFDR 6 95 INL ERROR (LSB) 85 80 2 0 –2 –4 SINAD 75 60000 50000 40000 30000 10000 TEMPERATURE (°C) –8 09029-135 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 70 09029-138 –6 20000 SNR/SFDR (dBFS) 4 90 CODE Figure 35. SINAD/SFDR vs. Temperature, fIN = 97.3 MHz, 2.5 V p-p FS, AD9467-250 Figure 38. INL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-250 0.8 2.25 0.6 1.50 0.4 DNL ERROR (LSB) 3.00 0.75 0 0.75 –1.50 –2.25 0.2 0 –0.2 –0.4 CODE 60000 54000 48000 42000 36000 30000 24000 18000 6000 –0.8 12000 09029-136 60000 54000 48000 42000 36000 30000 24000 18000 12000 –3.75 09029-139 –0.6 –3.00 6000 INL ERROR (LSB) 3.75 CODE Figure 36. INL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-200 Figure 39. DNL, fIN = 4.3 MHz, 2.5 V p-p FS, AD9467-250 Rev. D | Page 16 of 32 Data Sheet AD9467 100 0 SFDR –1 90 SNR –3 AMPLITUDE (dB) SNR/SFDR (dBFS/dBc) –2 80 70 60 50 DEFAULT CMV –3dB = 2.24GHz –4 –5 –6 –7 40 –8 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 10M 100M Figure 40. SNR/SFDR vs. Analog Input Common-Mode Voltage, AIN = 100 MHz, 2.5 V p-p FS, AD9467-250 140,000 SFDR 3.427LSB rms 90 120,000 80 SNR 100,000 NUMBER OF HITS 70 60 50 DEFAULT CMV 80,000 60,000 40,000 40 20,000 09029-141 30 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 0 2.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) N – 17 N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 SNR/SFDR (dBFS/dBc) 10G Figure 43. Converter AC Bandwidth AD9467-250 100 20 1.6 1G FREQUENCY (Hz) ANALOG INPUT COMMON-MODE VOLTAGE (V) 09029-143 1.6 –9 –10 1M CODE 09029-144 20 1.5 09029-140 30 Figure 44. Input-Referred Noise Histogram, 2.5 V p-p FS, AD9467-200 Figure 41. SNR/SFDR vs. Analog Input Common-Mode Voltage, AIN = 100 MHz, 2.5 V p-p FS, AD9467-200 0 140,000 –10 120,000 –20 100,000 60,000 –50 40,000 –60 20,000 –70 0 50 100 150 200 250 300 FREQUENCY (MHz) Figure 42. Common-Mode Rejection Ratio (CMRR), AD9467-250 0 CODE 09029-145 –40 80,000 N – 17 N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 NUMBER OF HITS –30 09029-142 CMRR (dB) 3.385LSB rms Figure 45. Input-Referred Noise Histogram, 2.5 V p-p FS, AD9467-250 Rev. D | Page 17 of 32 AD9467 Data Sheet 105 –55 –60 100 –65 95 AVDD1 –75 90 4MHz 97MHz 140MHz 170MHz 210MHz 290MHz 85 –80 DRVDD –90 75 ANALOG INPUT FREQUENCY (MHz) 09029-146 80 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 –85 Figure 46. Power Supply Rejection (PSR), AD9467-250 0 95 85 4MHz 97MHz 140MHz 170MHz 210MHz 290MHz 70 0 50 100 150 200 250 BUFFER CURRENT PERCENTAGE (%) 300 09029-247 SFDR (dBFS) 90 75 100 150 200 250 BUFFER CURRENT PERCENTAGE (%) 300 Figure 48. SFDR Performance vs. Buffer Current Percentage Over Analog Input Frequency, AD9467-250 100 80 50 09029-248 SFDR (dBFS) PSRR (dB) AVDD2 –70 Figure 47. SFDR Performance vs. Buffer Current Percentage Over Analog Input Frequency, AD9467-200 Rev. D | Page 18 of 32 Data Sheet AD9467 THEORY OF OPERATION Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. ANALOG INPUT CONSIDERATIONS The analog input to the AD9467 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a singleended signal. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the default case of the AD9467, the largest input span available is 2.5 V p-p. For other input full-scale options, see the Full-Scale and Reference Options section. SFDR Optimization—Buffer Current Adjustment Using Register 36 and Register 107, the buffer currents can be changed as a percentage to optimize the SFDR over various input frequencies and bandwidths of interest. As the input buffer currents are set, this does change the amount of current required by AVDD2. However, the current consumption is small in comparison to the overall currents required by this supply. The current specifications listed in Table 1 incorporate this variation. For a complete list of buffer current settings, see Table 13 for more details. The following buffer current settings reflect the performance that can be achieved using the input networks as described in Figure 51 and Figure 52. These curves describe the percentages used to obtain data sheet typical specifications for both the 250 MSPS and 200 MSPS parts. For example, when using IFs from 150 MHz to 250 MHz, 160% is actually the average of the entire buffer current. Therefore, both Register 36 and Register 107 need to be set to 160%. AD9467BCPZ-250 buffer current settings: • • • In either case, a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, the AN-935 Application Note, and the Analog Dialogue article “TransformerCoupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Rev. D | Page 19 of 32 DC to 150 MHz at 80% (default setting) 150 MHz to 250 MHz at 160% 250 MHz and higher at 210% 100 80% 160% 210% 98 96 94 92 90 88 86 84 82 80 0 50 100 150 200 250 ANALOG INPUT FREQUENCY (MHz) Figure 49. Buffer Current Sweeps, 2.5 V p-p, AD9467-250 300 09029-147 The input buffer provides a linear high input impedance (for ease of drive) and reduces the kick-back from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. SFDR (dBFS) The AD9467 architecture consists of an input-buffered pipelined ADC that consists of a 3-bit first stage, a 4-bit second stage, followed by four 3-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. AD9467 Data Sheet Differential Input Configurations There are several ways to drive the AD9467, either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 51 and Figure 52) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9467. Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed (see Figure 51, Figure 52, and Figure 53) Using the ADL5562 or ADL5201 differential drivers to drive the AD9467 provides an excellent and flexible gain option to interface to the ADC (see Figure 54 and Figure 56) for both baseband and high IF applications. Using an amplifier also provides better isolation from the preceding stages as well as better pass-band flatness. Performance plots of these amplifiers can also be seen in Figure 55 and Figure 57. When using any dc-coupled amplifier, the user has the option to disconnect the input common-mode voltage buffer from the analog inputs. This allows the common-mode output pin of the amplifier to set this voltage between the interface of the two devices. Otherwise, use an ac coupling capacitor in series on each of the analog input as shown in Figure 54 for IF applications that do not require dc coupling. See the Memory Map section for more details. DC to 150 MHz at 80% (default setting) 150 MHz to 250 MHz at 100% 250 MHz and higher at 160% 100 80% 100% 160% 98 96 92 90 88 86 84 80 0 50 100 150 200 250 300 ANALOG INPUT FREQUENCY (MHz) 09029-148 82 Figure 50. Buffer Current Sweeps, 2.5 V p-p, AD9467-200 Note that for sample rates less than 150 MSPS and analog inputs less than 100 MHz, it is recommended to set the buffer current to 0%. Depending on the input network design and frequency band of interest, the optimum buffer current settings may be slightly different than the input network recommendations shown in Figure 53 and Figure 54. 3.3V SMA 10nH 0.1µF ADT1-1WT 0.1µF ADT1-1WT 33Ω INPUT Z = 50Ω 0.1µF 0.1µF 0.1µF 33Ω AIN+ 24Ω 4.7pF 33Ω AD9467 530Ω 24Ω 0.1µF 33Ω 0.1µF 1.8V AIN– 16 3.5pF ADC INTERNAL INPUT Z NOTES 1. ALL CONNECTIONS AND POWER SUPPLY DECOUPLING NOT SHOWN. Figure 51. Differential Transformer-Coupled Configuration for Baseband Applications up to 150 MHz 3.3V SMA 10nH 0.1µF 0.1µF ADT1-1WT ADT1-1WT 15Ω INPUT Z = 50Ω 0.1µF 0.1µF 0.1µF 33Ω AIN+ 20Ω 1.8pF 33Ω 15Ω 0.1µF AD9467 530Ω 20Ω 0.1µF 1.8V AIN– 16 3.5pF ADC INTERNAL INPUT Z NOTES 1. ALL CONNECTIONS AND POWER SUPPLY DECOUPLING NOT SHOWN. 09029-041 SFDR (dBFS) 94 Figure 52. Differential Transformer-Coupled Configuration for IF Applications from 150 MHz to 300 MHz C1 0.1μF ANALOG IN 1 2 8 7 3 6 4 R5 15Ω R3 50Ω R1 33Ω R2 33Ω 5 ANAREN BD0205F5050A00 C2 0.1μF R7 15Ω C6 8.2pF 3.3V 1.8V AIN+ C3 0.1μF R6 15Ω C5 8.2pF R4 50Ω 16 AD9467 AIN– R8 15Ω NOTES 1. ALL CONNECTIONS AND POWER SUPPLY DECOUPLING NOT SHOWN. 09029-151 • • • 09029-040 AD9467BCPZ-200 buffer current settings: Figure 53. Wideband Balun-Coupled Configuration for IF Applications Up Greater Than 100 MHz Rev. D | Page 20 of 32 Data Sheet AD9467 3.3V 3.3V 15Ω 0.1µF 1:1 RATIO AC 40Ω 220nH 750Ω ADL5562 50Ω 0.1µF 15Ω 0.1µF 1.8V 20Ω 16 AD9467 5pF 0.1µF 20Ω 220nH NOTES 1. ALL CONNECTIONS AND POWER SUPPLY DECOUPLING NOT SHOWN. Figure 54. Wideband Differential Amplifier Input Configuration Using the ADL5562 0 AIN = –1dBFS SNR = 73.8dBFS SFDR = 91.1dBFS IF = 100MHz fS = 250MSPS –15 AMPLITUDE (dB) –30 –45 –60 –75 –90 *23 5 4 6 –105 09029-255 –120 –135 0 15 30 45 60 75 FREQUENCY (MHz) 90 105 120 Figure 55. Single-Tone FFT Performance Plot Using the ADL5562 Amplifier, Gain = 6 dB, and the AD9467-250 5V 5V 3.3V 1µH 1:3 0.1µF RATIO 0.1µF 75Ω AD5201 50Ω 14pF AD9467 16 75Ω 0.1µF 0.1µF 1µH 33Ω 47nH DIGITAL INTERFACE 5V NOTES 1. ALL CONNECTIONS AND POWER SUPPLY DECOUPLING NOT SHOWN. 09029-256 AC 0.1µF 1.8V 33Ω 47nH Figure 56. Wideband Differential VGA Input Configuration Using the ADL5201 0 AIN = –1dBFS SNR = 69.2dBFS SFDR = 88.8dBFS IF = 100MHz fS = 250MSPS –15 AMPLITUDE (dB) –30 –45 –60 –75 3 –90 2 * 5 6 –105 4 09029-257 –120 –135 0 15 30 60 45 75 FREQUENCY (MHz) 90 105 120 Figure 57. Single-Tone FFT Performance Plot Using the ADL5201 VGA, Gain = 20 dB, and the AD9467-250 Rev. D | Page 21 of 32 09029-254 40Ω AD9467 Data Sheet CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations For optimum performance, the AD9467 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9467 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9467. Figure 58 shows a preferred method for clocking the AD9467. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-toback Schottky diodes across the secondary transformer limit clock excursions into the AD9467 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9467, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. MINI-CIRCUITS® CLOCK INPUT 50Ω SNR = 20 × log 10(2 × π × fA × tJ) ADC 0.1µF CLK– 09029-056 SCHOTTKY DIODES: HSM2812 Figure 58. Transformer-Coupled Differential Clock Another option is to ac-couple a differential PECL or LVDS signal to the sample clock input pins, as shown in Figure 59 and Figure 60. The AD9510/AD9511/AD9512/AD9513/AD9514/ AD9515/AD9516/AD9517/AD9520/AD9522/AD9523/AD9524 family of clock drivers offers excellent jitter performance. 0.1µF CLOCK INPUT CLOCK INPUT 150Ω CLK+ 100Ω PECL DRIVER CLK– 240Ω 50Ω1 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9467. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. ADC 0.1µF CLK In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 61). 240Ω 130 09029-057 50Ω1 0.1µF CLK 0.1µF High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by CLK+ 100Ω 0.1µF Clock Jitter Considerations RESISTORS ARE OPTIONAL. Figure 59. Differential PECL Sample Clock 0.1µF 0.1µF 150Ω CLK+ LVDS DRIVER 100Ω 0.1µF CLK ADC RESISTORS ARE OPTIONAL. 100 16 BITS 90 14 BITS 80 12 BITS 70 10 BITS CLK– 60 50Ω1 09029-058 50Ω1 0.1µF CLK CLOCK INPUT 110 SNR (dB) CLOCK INPUT RMS CLOCK JITTER REQUIREMENT 120 Figure 60. Differential LVDS Sample Clock 8 BITS 50 40 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 30 1 10 100 ANALOG INPUT FREQUENCY (MHz) Figure 61. Ideal SNR vs. Input Frequency and Jitter Rev. D | Page 22 of 32 1000 09029-061 ADT1-1WT, 1:1 Z 0.1µF XFMR 0.1µF Any changes to the sampling frequency require several clock cycles to allow the internal timing to acquire and lock at the new sampling rate. Data Sheet AD9467 Power Supplies As shown in Figure 62, the power dissipated by the AD9467 is proportional to its sample rate. The output power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. To achieve the best dynamic performance of the AD9467, it is recommended that each power supply pin be decoupled as closely to the package as possible with 0.1 µF, X7R or X5R type decoupling capacitors. For optimum performance, all supplies should be at typical values or slightly higher to accommodate elevated temperature drifts, which depend on the application. 0.6 1.2 0.5 1.1 0.4 1.0 0.9 0.3 TOTAL POWER IAVDD1 IAVDD2 IDRVDD 0.2 Full-Scale and Reference Options POWER (W) CURRENT (mA) Power Dissipation and Power-Down Mode 0.8 0.7 0.1 09029-157 0.6 0 100 110 120 130 140 150 160 170 180 190 200 210 220 SAMPLE RATE (MSPS) 1.20 0.5 1.18 0.4 1.16 0.3 1.14 TOTAL POWER IAVDD1 IAVDD2 IDRVDD 0.2 1.12 1.10 0.1 0 210 215 220 225 230 235 240 245 250 1.08 SAMPLE RATE (MSPS) The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve gain matching when using multiple ADCs. The internal reference can be disabled via the SPI, allowing the use of an external reference. See the Memory Map section for more details. The external reference is loaded by the input of an internal buffer amplifier having 3 pF of capacitance to ground. There is also a 1 kΩ internal resistor in series with the input of that buffer. The external reference must be limited to a nominal 1.25 V for an input full-scale swing of 2.5 V p-p. Additional capacitance may be necessary to keep this pin quiet depending on the external reference used. POWER (W) 0.6 09029-158 CURRENT (mA) Figure 62. Supply Current vs. fSAMPLE for fIN = 5 MHz, AD9467-200 The analog inputs support both an input full scale of 2.5 V p-p (default) and 2.0 V p-p differentially. Choosing one full-scale input range over the other presents some trade-offs to the user. Using an input full scale of 2.5 V p-p yields the best SNR performance. If system trade-offs require improved SFDR performance, then a 2.0 V p-p input full scale should be used. However, in this mode, SNR degrades by roughly 2 dB. Other input full-scale ranges are available for use between 2.0 V p-p and 2.5 V p-p. See Register 18 in Table 13 and the Memory Map section for details. Figure 63. Supply Current vs. fSAMPLE for fIN = 5 MHz, AD9467-250 When not using the XVREF pin, it must be tied to ground directly or through a 0.1 µF decoupling capacitor. However, keep this pin quiet regardless. Digital Outputs and Timing By asserting the power-down option via the SPI register map (0x08[1:0]), the AD9467 is placed into power-down mode. In this state, the ADC typically dissipates 5 mW. During power-down, the LVDS output drivers are placed in a high impedance state. In power-down mode, low power dissipation is achieved by shutting down the internal reference, reference buffer, digital output, and biasing networks. The device requires approximately 100 ms to restore full operation. See the Memory Map section for more details on using these features. The AD9467 differential outputs conform to the ANSI-644 LVDS standard on default power-up. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.0 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 300 mV swing at the receiver. The AD9467 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be no longer than 18 inches and that the differential output traces be kept close together and at equal lengths. An example of the DCO and data with proper trace length and position is shown in Figure 64. Rev. D | Page 23 of 32 AD9467 Data Sheet 400 CLOCK 300 200 VOLTAGE (mV) 1 DCO 2 100 0 –100 –200 3 –300 DATA 5.0ns/DIV A CH2 20.0GS/s IT 25.0pt/pt 10.0V 09029-159 –400 CH1 500mV Ω CH2 500mV Ω CH3 500mV Ω –2 Figure 64. Output Timing Example in LVDS Mode (Default), AD9467-250 400 300 40 35 30 25 20 15 10 5 0 –40 0 –20 20 0 TIME (ps) –100 40 60 Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 18-Inch Trace Lengths on Standard FR-4, AD9467-250 –200 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. To change the output data format to twos complement or Gray code, see the Memory Map section. –300 –400 –2 TIE JITTER HISTOGRAM (Hits) 2 50 100 –1 0 TIME (ns) 1 2 14 Table 8. Digital Output Coding 12 Code 65,536 32,768 32,767 0 10 8 6 4 –10 0 10 TIME (ps) 20 30 40 09029-160 2 0 –20 1 09029-161 VOLTAGE (mV) 200 0 TIME (ns) 45 TIE JITTER HISTOGRAM (Hits) An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of six inches on standard FR-4 material is shown in Figure 65. It is the responsibility of the user to determine if the waveforms meet the timing budget of the design. –1 (VIN+) − (VIN−), Input Span = 2.5 V p-p (V) +1.25 0.00 −0.000038 −1.25 Digital Output Offset Binary (D15:D0) 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 An output clock is provided to assist in capturing data from the AD9467. Data is clocked out of the AD9467 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. See the timing diagram shown in Figure 2 for more information. Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with 6-Inch Trace Lengths on Standard FR-4, AD9467-250 Rev. D | Page 24 of 32 Data Sheet AD9467 There are eight digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 10 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns may not adhere to the data format select option. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value must be a specific value instead of all 1s (see Table 9 for the initial values). The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 – 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 9 for the initial values) and the AD9467 inverts the bit stream with relation to the ITU standard. Table 9. PN Sequence Sequence PN 9 Sequence, Short PN 23 Sequence, Long Initial Value 0xFFFF 0x7FFF Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. Overrange (OR) Output Pins The OR+ and OR− output pins indicate when an applied analog input is above or below the input full scale of the converter. If the analog input is in an overrange condition, the OR bit goes high, coinciding with output data hitting above or below fullscale. The delay between the time the part actually overranges and the OR bit going high is the pipeline latency of the part. SPI Pins: SCLK, SDIO, CSB For normal SPI operation, these pins should be tied to AGND through a 100 kΩ resistor on each pin. These pins are both 1.8 V and 3.3 V tolerant. However, the SDIO output logic level is dependent on the bias of the SPIVDD pin. For 3.3 V output logic, tie SPIVDD to 3.3 V (AVDD2). For 1.8 V output logic, tie SPIVDD to 1.8 V (AVDD1). The CSB pin should be tied to AVDD1 for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. First Three Output Samples (MSB First) 0x87BE, 0xAE64, 0x929D 0x7E00, 0x807C, 0x801F Table 10. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1 2 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Checkerboard PN sequence long 2 PN sequence short2 One-/zero-word toggle Digital Output Word 1 N/A 1 1000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1010 1010 1010 1010 N/A1 N/A1 1111 1111 1111 1111 Digital Output Word 2 N/A1 Same Same Same 0101 0101 0101 0101 N/A1 N/A1 0000 0000 0000 0000 N/A = not applicable. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths to verify data capture to the receiver. Rev. D | Page 25 of 32 Subject to Data Format Select N/A1 Yes Yes Yes No Yes Yes No AD9467 Data Sheet SERIAL PORT INTERFACE (SPI) The AD9467 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided down into fields, as detailed in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. In addition to the operation modes, the SPI port configuration influences how the AD9467 operates. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change from an input to an output at the appropriate point in the serial frame. There are three pins that define the SPI: SCLK, SDIO, and CSB (see Table 11). The SCLK pin is used to synchronize the read and write data presented to the ADC. The SDIO pin is a dualpurpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Table 11. Serial Port Pins HARDWARE INTERFACE Pin SCLK The pins described in Table 11 compose the physical interface between the programming device of the user and the serial port of the AD9467. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 68 and Table 12. During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without requiring additional instructions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction. 1.80 1.79 1.78 1.77 1.76 1.75 1.74 1.73 1.72 0 10 20 30 40 50 60 70 80 90 NUMBER OF SDIO PINS CONNECTED TOGETHER 100 09029-074 CSB If multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Assuming the same load for each AD9467, Figure 67 shows the number of SDIO pins that can be connected together and the resulting VOH level. VOH (V) SDIO Function Serial clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin. The typical role for this pin is an input or output, depending on the instruction sent and the relative position in the timing frame. Chip select bar (active low). This control gates the read and write cycles. Figure 67. SDIO Pin Loading This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers, providing the user with an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note). Rev. D | Page 26 of 32 Data Sheet AD9467 tDS tS tCLK tHIGH tDH tH tLOW CSB DON’T CARE R/W SDIO DON’T CARE W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 09029-072 SCLK DON’T CARE Figure 68. Serial Timing Details Table 12. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO Timing (Minimum, ns) 5 2 40 5 2 16 16 10 tDIS_SDIO 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 68) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 68) Rev. D | Page 27 of 32 AD9467 Data Sheet MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table (see Table 13) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x107). Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES When the AD9467 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 13, where an X refers to an undefined feature. The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. The (MSB) Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x2C, the analog input register, has a default value of 0x00, meaning Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 0, or 0000 0000 in binary. This setting is the default for an ac-coupled analog input condition. By writing a 1 to Bit 2 of this address, the internal input common-mode buffer is disabled allowing a dc-coupled input for which the input common mode voltage can be set externally. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. LOGIC LEVELS An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Table 13. Memory Map Register 1 Addr. (MSB) (Hex) Parameter Name Bit 7 Chip Configuration Register 00 chip_port_config X 01 chip_id 02 chip_grade Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 LSB first 1 = on 0 = off (default) Soft reset 1 = on 0 = off (default) 1 1 X X X 8-Bit Chip ID Bits[7:0] (AD9467 = 0x50, default) X Device Index and Transfer Register FF device_update X Child ID Bits[6:4] (identify device variants of chip ID) 001 = 200 MSPS 010 = 250 MSPS X X X Default Value (Hex) 0x18 Read only X X X X Read only X X X SW transfer 1 = on 0 = off (default) 0x00 Rev. D | Page 28 of 32 Default Notes/ Comments The nibbles should be mirrored so that LSB- or MSB-first mode is set correctly regardless of shift mode. Default is unique chip ID, different for each device. This is a readonly register. Child ID used to differentiate graded devices. Synchronously transfers data from the master shift register to the slave. Data Sheet AD9467 Addr. (Hex) Parameter Name ADC Functions 08 modes (MSB) Bit 7 Bit 6 Bit 5 X X 0D test_io X X 0F adc_input XVREF 1 = on 0 = off (default) X 10 offset 14 output_mode X 0 15 output_adjust X X 16 output_phase X 18 vref DCO output invert 1 = on 0 = off (default) X Internal powerdown mode 00 = chip run (default) 01 = full powerdown Output test mode—see Table 10 in the Reset PN Reset PN Digital Outputs and Timing section short gen long 0000 = off (default) 1 = on gen 0001 = midscale short 0 = off 1 = on 0010 = +FS short (default) 0 = off 0011 = −FS short (default) 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle Analog X X X X X disconnect 1 = on 0 = off (default) 8-bit digital offset adjustment 0111 1111 = 127 0111 1110 = 126 … 0000 0010 = 2 0000 0001 = 1 0000 0000 = 0 1111 1111 = -1 1111 1110 = -2 … 1000 0001 = -126 1000 0000 = -127 Data format Output Digital 1 X select invert output 1 = on disable 00 = offset 0 = off binary (default) 1 = on (default) 0 = off 01 = twos (default) complement 10 = Gray code Coarse Output current drive adjust X X LVDS 001 = 3.0 mA (default) adjust 010 = 2.79 mA 0= 011 = 2.57 mA 3.0 mA 100 = 2.35 mA (default) 101 = 2.14 mA 1= 110 = 1.93 mA 1.71 mA 111 = 1.71 mA X X X X X X X X X Bit 4 X Bit 3 X X Bit 2 Bit 1 (LSB) Bit 0 X Input full-scale range adjust 0000 = 2.0 V p-p 0110 = 2.1 V p-p 0111 = 2.2 V p-p 1000 = 2.3 V p-p 1001 = 2.4 V p-p 1010 = 2.5 V p-p (default) Rev. D | Page 29 of 32 Default Value (Hex) Default Notes/ Comments 0x00 Determines various generic modes of chip operation. 0x00 When this register is set, the test data is placed on the output pins in place of normal data. 0x00 Analog input functions. 0x00 Bipolar, twos complement digital offset adjustment in LSBs. 0x08 Configures the outputs and the format of the data. 0x00 Determines LVDS or other output properties. 0x00 Determines digital clock output phase. 0x0A AD9467 Addr. (Hex) 2C Parameter Name analog_input 36 Buffer Current Select 1 107 Buffer Current Select 2 1 Data Sheet (MSB) Bit 7 X Bit 6 X Bit 5 X Bit 4 X Bit 3 X 110101 = +530% 110100 = +520% … 001000 = +80% (default) … 000010 = +20% 000001 = +10% 000000 = nominal, 0% 111111 = −10% 111110 = −20% … 110111 = −90% 110110 = −100% 110101 = +530% 110100 = +520% … 001000 = +80% (default) … 000010 = +20% 000001 = +10% 000000 = nominal, 0% 111111 = −10% 111110 = −20% … 110111 = −90% 110110 = −100% X = undefined feature, don’t write. Rev. D | Page 30 of 32 Bit 2 Input coupling mode 0 = ac coupling (default) 1 = dc coupling Bit 1 X (LSB) Bit 0 X Default Value (Hex) 0x00 1 0 0x22 X X 0x20 Default Notes/ Comments Determines the input coupling mode. Data Sheet AD9467 Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations When connecting power to the AD9467, it is recommended that three separate supplies be used: one for analog AVDD1 and AVDD3 (1.8 V), one for analog AVDD2 (3.3 V), and one for digital output drivers DRVDD (1.8 V). If only one 1.8 V supply is available, it should be routed to AVDD1 and AVDD3 first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts, with minimal trace lengths. It is required that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9467. An exposed continuous copper plane on the PCB should be connected to the AD9467 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. A single PC board ground plane should be sufficient when using the AD9467. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections, optimum performance can be easily achieved. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 69 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). 09029-073 SILKSCREEN PARTITION PIN 1 INDICATOR Figure 69. Typical PCB Layout Rev. D | Page 31 of 32 AD9467 Data Sheet OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 55 54 72 1 PIN 1 INDICATOR PIN 1 INDICATOR 9.85 9.75 SQ 9.65 0.50 BSC 0.50 0.40 0.30 18 37 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN 8.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 06-25-2012-C 1.00 0.85 0.80 19 36 TOP VIEW 12° MAX 8.60 8.50 SQ 8.40 EXPOSED PAD Figure 70. 72-Lead Lead Frame Chip Scale Package, Exposed Pad [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-5) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9467BCPZ-200 AD9467BCPZRL7-200 AD9467BCPZ-250 AD9467BCPZRL7-250 AD9467-200EBZ AD9467-250EBZ AD9467-FMC-250EBZ 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ AD9467-200 Evaluation Board AD9467-250 Evaluation Board AD9467-250 Native FMC Card Z = RoHS Compliant Part. ©2010–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09029-0-2/13(D) Rev. D | Page 32 of 32 Package Option CP-72-5 CP-72-5 CP-72-5 CP-72-5