NCV7321 Stand Alone LIN Transceiver Description Features • General • • • • http://onsemi.com 8 1 SOIC−8 CASE 751 PIN ASSIGNMENT RxD 1 8 INH EN 2 7 VBB WAKE 3 6 LIN TxD 4 5 GNI NCV7321 The NCV7321 is a fully featured local interconnect network (LIN) transceiver designed to interface between a LIN protocol controller and the physical bus. The transceiver is implemented in I3T technology enabling both high−voltage analog circuitry and digital functionality to co−exist on the same chip. The NCV7321 LIN device is a member of the in−vehicle networking (IVN) transceiver family. It is designed to work in harsh automotive environment and is qualified following the TS16949 flow. The LIN bus is designed to communicate low rate data from control devices such as door locks, mirrors, car seats, and sunroofs at the lowest possible cost. The bus is designed to eliminate as much wiring as possible and is implemented using a single wire in each node. Each node has a slave MCU−state machine that recognizes and translates the instructions specific to that function. The main attraction of the LIN bus is that all the functions are not time critical and usually relate to passenger comfort. SOIC−8 Green package (Pb−Free) (Top View) PC20040918.3 LIN−Bus Transceiver ♦ LIN Compliant to Specification Revision 2.0 and 2.1 (Backwards ORDERING INFORMATION Compatible to Version 1.3) and J2602 See detailed ordering and shipping information in the package ♦ Bus Voltage $45 V dimensions section on page 11 of this data sheet. ♦ Transmission Rate 1 kbps to 20 kbps ♦ Sleep Mode: LIN Transceiver Disabled, the Protection Consumption from VBB is Minimized, INH Switch ♦ Thermal Shutdown is Off ♦ Indefinite Short−Circuit Protection on Pins LIN and ♦ Standby Mode: transition mode reached either after WAKE Towards Supply and Ground power−up or after a wakeup event, INH switch is on ♦ Load Dump Protection (45 V) ♦ Wake−up Bringing the Component from Sleep ♦ Bus Pins Protected Against Transients in an Mode into Standby Mode is Possible either by LIN Automotive Environment Command or a Digital Signal on WAKE Pin (e.g. EMI Compatibility External Switch) ♦ Integrated Slope Control • These are Pb−Free Devices Modes ♦ ♦ Normal Mode: LIN Transceiver Enabled, Communication via the LIN Bus is Possible, INH Switch is On © Semiconductor Components Industries, LLC, 2010 June, 2010 − Rev. 8 1 Publication Order Number: NCV7321/D NCV7321 KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES Symbol VBB Parameter Nominal Battery Operating Voltage (Note 1) Min Typ Max Unit 5 12 27 V Load Dump Protection 45 IBB_SLP Supply Current in Sleep Mode 20 A VLIN LIN Bus Voltage −45 45 V VWAKE Operating DC Voltage on WAKE Pin 0 VBB V −35 45 V Maximum Rating Voltage on WAKE Pin VINH Operating DC Voltage on INH Pin 0 VBB V V_Dig_IO Operating DC Voltage on Digital IO Pins (EN, RxD, TxD) 0 5.5 V TJ Junction Thermal Shutdown Temperature Tamb Operating Ambient Temperature −40 +125 °C VESD Electrostatic Discharge Voltage (all pins) Human Body Model (Note 2) −4 +4 kV Version NCV7321D11; no filter on LIN Electrostatic Discharge Voltage (LIN) System Human Body Model (Note 3) −13 +13 kV 165 °C 1. Below 5 V on VBB in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time specifications as required by SAE J2602. It is ensured by the battery monitoring circuit. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor conform to MIL STD 883 method 3015.7. 3. Equivalent to discharging a 150 pF capacitor through a 330 resistor. System HBM levels are verified by an external test−house. BLOCK DIAGRAM INH VBB POR VBB State & Wake−up Control WAKE EN Thermal shutdown Osc COMP RxD + − TxD time−out Filter LIN Slope Control NCV7321 PD20070503.2 GND Figure 1. Block Diagram http://onsemi.com 2 NCV7321 TYPICAL APPLICATION bat ECU VBAT LIN WAKE LIN 6 WAKE 3 7 NCV7321 INH 8 5 3.3/5V 1 RxD 4 TxD 2 EN GND GND VCC Microcontroller VBB GND PD20070503.1 KL30 LIN− BUS KL31 Figure 2. Typical Application Diagram for a Master Node Table 2. PIN DESCRIPTION Pin Name Description 1 RxD Receive Data Output; Low in Dominant State; Open−Drain Output 2 EN Enable Input, Transceiver in Normal Operation Mode when High, Pulldown Resistor to GND 3 WAKE High Voltage Digital Input Pin to Apply Local Wakeup, Sensitive to Falling Edge, Pullup Current Source to VBB 4 TxD Transmit Data Input, Low for Dominant State, Pulldown to GND (Switchable Strength for Wakeup Source Recognition) 5 GND Ground 6 LIN LIN Bus Output/Input 7 VBB Battery Supply Input 8 INH Inhibit Output, Switch Between INH and VBB can be Used to Control External Regulator or Pullup Resistor on LIN Bus Table 3. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Typ Max Unit VBB Voltage on Pin VBB −0.3 +45 V VLIN LIN Bus Voltage −45 +45 V VWAKE DC Voltage on WAKE Pin −35 +45 V VINH DC Voltage on INH Pin −0.3 VBB + 0.3 V V_Dig_IO DC Input Voltage on Pins (EN, RxD, TxD −0.3 +45 V TJ Maximum Junction Temperature −40 +150 °C VESD HBM (All Pins) (Note 4) −4 +4 kV CDM (All Pins) (Note 5) −750 +750 V Version NCV7321D10: HBM (LIN, INH, VBB, WAKE) (Note 6) System HBM (LIN, VBB, WAKE) (Note 7) −5 −5 +5 +5 kV kV Version NCV7321D11: HBM (LIN, INH, VBB, WAKE) (Note 6) System HBM (VBB, WAKE) (Note 8) System HBM (LIN) (Note 8) −8 −7 −13 +8 +7 +13 kV kV kV Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor conform to MIL STD 883 method 3015.7. 5. Charged device model test according to ESD STM5.3.1−1999. 6. Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor referenced to GND. 7. Equivalent to discharging a 150 pF capacitor through a 330 resistor. 220 nF filter on LIN pin. System HBM levels are verified by an external test−house. 8. Equivalent to discharging a 150 pF capacitor through a 330 resistor. No filter on LIN pin. System HBM levels are verified by an external test−house. http://onsemi.com 3 NCV7321 FUNCTIONAL DESCRIPTION Overall Functional Description The junction temperature is monitored via a thermal shutdown circuit that switches the LIN transmitter off when temperature exceeds the TSD trigger level. The NCV7321 has four operating states (unpowered mode, standby mode, normal mode and sleep mode) that are determined by the supply voltage VBB, input signals EN and WAKE and activity on the LIN bus. LIN is a serial communication protocol that efficiently supports the control of mechatronic nodes in distributed automotive applications. The domain is class−A multiplex buses with a single master node and a set of slave nodes. The NCV7321 contains the LIN transmitter, LIN receiver, power−on−reset (POR) circuits and thermal shutdown (TSD). The LIN transmitter is optimized for the maximum specified transmission speed of 20 kB with EMC performance due to reduced slew rate of the LIN output. OPERATING STATES Standby mode Normal mode − LIN Transceiver: OFF − LIN Term: 30 k − INH Pin = High − RxD: Low After a Wake−up/ Floating Otherwise − TxD: Wake−up Source Flag EN = High for t > T_enable − LIN Transceiver: ON − LIN Term: 30 k − INH Pin: High − RxD: Received LIN Data − TxD: Weak Pulldown Transmitter Input LIN Wake−Up or Local Wake−Up VBB Above Reset Level EN = Low for t > T_disable EN = High for t > T_enable Sleep Mode Unpowered (VBB Below Reset Level) − LIN Transceiver: OFF − LIN Term: Floating − INH Pin: Floating − RxD: Floating − TxD: Weak Pulldown − LIN Transceiver: OFF − LIN Term: Current Source − INH Pin: Floating − RxD: Floating − TxD: Weak Pulldown PD20080606.2 Figure 3. State Diagram Unpowered Mode high−impedant and the pulldown applied on pin TxD remains weak. • After a wakeup event is recognized while the chip was in the sleep mode. Pin RxD is pulled low while pin TxD signals the type of wakeup leading to the standby mode – its pullup remains weak for LIN wakeup and it is switched to strong pulldown for the case of local wakeup (i.e. wakeup via Pin WAKE). While in the standby mode, the configuration of Pins RxD and TxD remains unchanged, regardless the activity on WAKE and LIN Pins – i.e. if additional wakeups occur during the standby mode, they have no influence on the chip configuration. As long as VBB remains below its power−on−reset level, the chip is kept in a safe unpowered state. LIN transmitter is inactive, both LIN and INH pins are left floating and only a weak pulldown is connected on pin TxD. Pin RxD remains floating. The unpowered state will be entered from any other state when VBB falls below its power−on−reset level. Standby Mode Standby mode is a low−power mode, where LIN transceiver remains inactive while INH pin is driven high to activate an external voltage regulator – see Figure 2. Depending on the transition which led to the standby mode, pins RxD and TxD are configured differently during this mode. A 30 k resistor in series with a reverse−protection diode is internally connected between LIN and VBB Pins. Standby mode is entered in one of the following ways: • After the voltage level at VBB pin rises above its power−on−reset level. In this case, RxD Pin remains Normal Mode In normal mode, the full functionality of the LIN transceiver is available. Data according the state of TxD input are sent to the LIN bus while pin RxD reflects the logical symbol received on the LIN bus – high−impedant for recessive and Low for dominant. A 30 k resistor in series http://onsemi.com 4 NCV7321 standby mode pin settings and the signals required to control the chip in the normal mode (e.g. strong pull−down on TxD after local wakeup vs. High logical level on TxD required to send a recessive symbol on LIN). with a reverse−protection diode is internally connected between LIN and VBB pins. To avoid that, due to a failure of the application (e.g. software error), the LIN bus is permanently driven dominant and thus blocking all subsequent communication, signal on pin TxD passes through a timer, which releases the bus in case TxD remains low for longer than T_TxD_timeout. The transmission can continue once the TxD returns to High logical level. In case the junction temperature increases above the thermal shutdown threshold, e.g. due to a short of the LIN wiring to the battery, the transmitter is disabled and releases LIN bus to recessive. Once the junction temperature decreases back below the thermal shutdown release level, the transmission can be enabled again – however, to avoid thermal oscillations, first a High logical level on TxD must be encountered before the transmitter is enabled. As required by SAE J2602, the transceiver must behave safely below its operating range – it shall either continue to transmit correctly (according its specification) or remain silent (transmit a recessive state regardless of the TxD signal). A battery monitoring circuit in NCV7321 de−activates the transmitter in the normal mode if the VBB level drops below MONL_VBB. Transmission is enabled again when VBB reaches MONH_VBB. The internal logic remains in the normal mode and the reception from the LIN line is still possible even if the battery monitor disables the transmission. Although the specifications of the monitoring and power−on−reset levels are overlapping, it’s ensured by the implementation that the monitoring level never falls below the power−on−reset level. Normal mode can be entered from either standby or sleep mode when EN Pin is High for longer than T_enable. When the transition is made from standby mode, TxD pulldown is set to weak and RxD is put high−impedant immediately after EN becomes High (before the expiration of T_enable filtering time). This excludes signal conflicts between the WAKE VBB Sleep Mode Sleep mode provides extremely low current consumption. The LIN transceiver is inactive and the battery consumption is minimized. Pin INH is put to high−impedant state to disable the external regulator and, in case of a master node, the LIN termination – see Figure 2. Only a weak pullup current source is internally connected between LIN and VBB Pins, in order to minimize current consumption even in case of LIN short to GND. Sleep mode can be entered from normal mode by assigning Low logical level to pin EN for longer than T_disable. The sleepmode can be entered even if a permanent short occurs either on LIN or WAKE Pin. If a wakeup event occurs during the transition between normal and sleep mode (during the T_disable filtering time), it will be regarded as valid wakeup and the chip will enter standby mode with the appropriate setting of Pins RxD and TxD. Wake−up Two types of wakeup events are recognized by NCV7321: • Local wakeup – when a high−to−low transition on pin WAKE is encountered and WAKE pin remains Low at least during T_WAKE – see Figure 4. • Remote (or LIN) wakeup – when LIN bus is externally driven dominant during longer than T_LIN_wake and a rising edge on LIN occurs afterwards – see Figure 5. Wakeup events can be exclusively detected in sleep mode or during the transition from normal mode to sleep mode. Due to timing tolerances, valid wakeup events beginning shortly before normal−to−sleep mode transition can be also sometimes regarded as valid wakeups. Local wakeup recognized T_WAKE V_WAKE_th Sleep Mode Stand−by Mode PD20070503.4 Figure 4. Local Wakeup Detection http://onsemi.com 5 t NCV7321 LIN Detection of Remote Wake−Up VBB LIN recessive level T_LIN_wake 60% Vbb T_enable 40% VBB Sleep Mode LIN dominant level Stand−by Mode t PD20070504.2 Figure 5. Remote (LIN) Wakeup Detection ELECTRICAL CHARACTERISTICS Definitions All voltages are referenced to GND (Pin 5). Positive currents flow into the IC. Table 4. DC CHARACTERISTICS (VBB = 5 V to 27 V; TJ = −40°C to +150°C; unless otherwise specified. Typical values are given at V(VBB) = 12 V and TJ = 25°C, unless specified otherwise.) DC CHARACTERISTICS − SUPPLY Symbol Parameter Conditions Min Typ Max Unit 1.6 mA 8 mA VBB IBB_ON_rec VBB Consumption Normal Mode; LIN recessive VLIN = V(VBB) = VINH = VWAKE IBB_ON_dom VBB Consumption Normal Mode; LIN dominant V(VBB) = VINH = VWAKE IBB_STB VBB Consumption Standby Mode VLIN = V(VBB) = VINH = VWAKE 350 A IBB_SLP VBB Consumption Sleep Mode VLIN = V(VBB) = VINH = VWAKE 30 A IBB_SLP_18V VBB Consumption Sleep Mode, VBB < 18 V VLIN = V(VBB) = VINH = VWAKE 20 A IBB_SLP_12V VBB Consumption Sleep Mode, VBB = 12 V, TJ < 85°C VLIN = V(VBB) = VINH = VWAKE 10 A VLIN_dom_LoSu p LIN Dominant Output Voltage TXD = Low; VBB = 7.3 V 1.2 V VLIN_dom_HiSup LIN Dominant Output Voltage TXD = Low; VBB = 18 V 2.0 V VLIN_REC LIN Recessive Output Voltage TXD = HighH; ILIN = 0 mA ILIN_lim Short Circuit Current Limitation VLIN = VBB_max Rslave Internal Pullup Resistance ILIN_off_dom LIN output current, bus in dominant state Normal Mode, Driver Off; VBB = 12 V −1 ILIN_off_dom_slp LIN Output Current, Bus in Dominant State Sleep Mode, Driver Off; VBB = 12 V −20 LIN TRANSMITTER V VBB − V (Note 9) 40 20 9. V is the forward diode voltage. Typically (over the complete temperature) V = 1 V. http://onsemi.com 6 33 200 mA 47 k mA −15 −2 A NCV7321 Table 4. DC CHARACTERISTICS (VBB = 5 V to 27 V; TJ = −40°C to +150°C; unless otherwise specified. Typical values are given at V(VBB) = 12 V and TJ = 25°C, unless specified otherwise.) DC CHARACTERISTICS − SUPPLY Symbol Parameter Conditions Min Typ Max Unit 1 A 1 mA 5 A 0.4 VBB LIN TRANSMITTER ILIN_off_rec LIN Output Current, Bus in Recessive State Driver Off; VBB < 18 V; VBB < VLIN < 18 V ILIN_no_GND Communication not Affected VBB = GND = 12 V; 0 < VLIN < 18 V ILIN_no_VBB LIN Bus Remains Operational VBB = GND = 0 V; 0 < VLIN < 18 V −1 LIN RECEIVER Vbus_dom Bus Voltage for Dominant State Vbus_rec Bus Voltage for Recessive State Vrec_dom Receiver Threshold LIN Bus Recessive − Dominant 0.4 0.6 VBB Vrec_rec Receiver Threshold LIN Bus Dominant − Recessive 0.4 0.6 VBB Vrec_cnt Receiver Centre Voltage (Vbus_dom + Vbus_rec)/2 0.475 0.525 VBB Vrec_hys Receiver Hysteresis (Vbus_rec − Vbus_dom) 0.05 0.175 VBB Conditions Min Max Unit 0.6 VBB DC CHARACTERISTICS − I/Os Symbol Parameter Typ PIN EN Vil_EN Low Level Input Voltage −0.3 0.8 V Vih_EN High Level Input Voltage 2.0 5.5 V Rpd_EN Pulldown Resistance to Ground (Note 9) 150 350 650 k PIN INH Delta_VH High Level Voltage Drop IINH = 15 mA, INH Active 0.05 0.35 0.75 V I_leak Leakage Current Sleep Mode; VINH = 0 V −1 0 1 A Iol_RxD Low Level Output Current VRxD = 0.4 V, normal mode, VLIN = 0 V 1.5 Ioh_RxD High Level Output Current VRxD = 5 V, Normal Mode, VLIN = V(VBB) −5 PIN RxD mA 0 5 A PINS TxD Vil_TxD Low Level Input Voltage −0.3 0.8 V Vih_TxD High Level Input Voltage 2.0 5.5 V Rpd_TxD Pulldown Resistor on TxD Pin, Corresponding to “Weak Pulldown” 650 k Normal Mode or Sleep Mode or Standby Mode after Powerup or Standby Mode after LIN Wakeup 9. V is the forward diode voltage. Typically (over the complete temperature) V = 1 V. http://onsemi.com 7 150 350 NCV7321 Table 4. DC CHARACTERISTICS (VBB = 5 V to 27 V; TJ = −40°C to +150°C; unless otherwise specified. Typical values are given at V(VBB) = 12 V and TJ = 25°C, unless specified otherwise.) DC CHARACTERISTICS − I/Os Symbol Parameter Conditions Min Typ Max Unit PINS TxD Ipd_RxD_Strong Pulldown Current on TxD Pin Corresponding to “Strong Pulldown” Standby Mode after Local Wakeup 1.5 mA PIN WAKE V_wake_th WAKE Threshold Voltage VBB − 3.3 I_wake_pullup Pullup Current on Pin WAKE VWAKE = 0 V −30 I_wake_leak Leakage of Pin WAKE VWAKE = V(VBB) −5 VBB − 1.1 V −15 −1 A 0 5 A DC CHARACTERISTICS – POWER−ON−RESET, BATTERY MONITORING AND THERMAL SHUTDOWN Symbol Parameter Conditions Min. Typ. Max. Unit POR AND VBB MONITOR PORH_VBB Power−on Reset High Level on VBB VBB Rising 2 4.5 V PORL_VBB Power−on Reset Low Level on VBB VBB Falling 1.7 4 V MONH_VBB Battery Monitoring High Level VBB Rising 4.5 V MONL_VBB Battery Monitoring Low Level VBB Falling TJ Junction Temperature Temperature Rising TJ_hyst Thermal Shutdown Hysteresis 3 V TSD 165 9 9. V is the forward diode voltage. Typically (over the complete temperature) V = 1 V. http://onsemi.com 8 °C 18 °C NCV7321 Table 5. AC CHARACTERISTICS VBB = 5 V to 27 V; TJ = −40°C to +150°C; unless otherwise specified. For the transmitter parameters, the following bus loads are considered: L1 = 1 k / 1 nF; L2 = 660 / 6.8 nF; L3 = 500 / 10 nF Symbol Parameter Conditions Min Typ Max Unit LIN TRANSMITTER D1 Duty Cycle 1 = tBUS_REC(max) / (2 x TBit) THREC(min) = 0.744 x VBB THDOM(min) = 0.581 x VBB TBIT = 50 s V(VBB) = 7 V to 18 V 0.396 0.5 D2 Duty Cycle 2 = tBUS_REC(min) / (2 x TBit) THREC(max) = 0.422 x VBB THDOM(max) = 0.284 x VBB TBIT = 50 s V(VBB) = 7.6 V to 18 V 0.5 0.581 D3 Duty Cycle 3 = tBUS_REC(max) / (2 x TBit) THREC(min) = 0.778 x VBB THDOM(min) = 0.616 x VBB TBIT = 96 s V(VBB) = 7 V to 18 V 0.417 0.5 D4 Duty Cycle 4 = tBUS_REC(min) / (2 x TBit) THREC(max) = 0.389 x VBB THDOM(max) = 0.251 x VBB TBIT = 96 s V(VBB) = 7.6 V to 18 V 0.5 0.590 T_fall LIN Falling Edge Normal Mode; VBB = 12 V 22.5 s T_rise LIN Rising Edge Normal Mode; VBB = 12 V 22.5 s T_sym LIN Slope Symmetry Normal Mode; VBB = 12 V 4 s −4 0 LIN Receiver Trec_prop_down Propagation Delay of Receiver Falling Edge 0.1 6 s Trec_prop_up Propagation Delay of Receiver Rising Edge 0.1 6 s Trec_sym Propagation Delay Symmetry Trec_prop_down − Trec_prop_up −2 2 s 150 s 50 s MODE TRANSITIONS AND TIMEOUTS T_LIN_wake Duration of LIN Dominant for Detection of wake−up via LIN bus Sleep Mode 30 T_WAKE Duration of Low level on WAKE Pin for local wakeup detection Sleep Mode 7 T_enable Duration of High Level on EN Pin for Transition to Normal Mode Version NCV7321D10 2 5 10 s Version NCV7321D11 2 7.5 18.5 s Duration of Low Level on EN Pin for Transition to Sleep Mode Version NCV7321D10 2 5 10 s Version NCV7321D11 2 7.5 18.5 s TxD Dominant Time−Out Normal Mode, TxD = low, Guarantees Baudrate as Low as 1 kbps 15 50 ms T_disable T_TxD_timeout http://onsemi.com 9 90 NCV7321 TxD t BIT t BIT 50% t tBUS_dom(max) LIN tBUS_rec(min) THRec(max) THDom(max) Thresholds of receiving node 1 THRec(min) THDom(min) Thresholds of receiving node 2 t tBUS_dom(min) tBUS_rec(max) PC20080606.3 Figure 6. LIN Transmitter Duty Cycle LIN 100% 60% 60% 40% 40% 0% T_fall T_rise t PC20060428.1 Figure 7. LIN Transmitter Rising and Falling Times LIN VBB 60% VBB 40% VBB t RxD trec_prop_down trec_prop_up 50% t Figure 8. LIN Receiver Timing http://onsemi.com 10 PC20060428.3 NCV7321 DEVICE ORDERING INFORMATION Part Number NCV7321D10G NCV7321D10R2G NCV7321D11G NCV7321D11R2G Description Temperature Range Package Type Stand−alone LIN Transceiver Improved Stand−alone LIN Transceiver Shipping† 96 Tube / Tray −40°C − 125°C SOIC−8 (Pb−Free) 3000 / Tape & Reel 96 Tube / Tray 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 11 NCV7321 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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