19-5340; Rev 3; 7/10 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM The DS32B35/DS32C35 accurate real-time clocks (RTC) are clock/calendars that include an integrated temperature-compensated crystal oscillator (TCXO), crystal, and a bank of nonvolatile memory (FRAM) in a single package. The nonvolatile memory is available in two densities: 2048 x 8 and 8192 x 8 bits. The integration of the crystal resonator enhances the long-term accuracy of the devices as well as reduces the piece part count in a manufacturing line. The devices operate as a slave device on an I2C serial interface, and are available in both commercial and industrial temperature ranges in a 300-mil, 20-pin SO package. The clock/date provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The DS32B35/DS32C35 include a bank of nonvolatile memory that does not require a backup energy source to maintain memory contents. In addition, there are no read or write cycle limitations. The memory array can be accessed at maximum cycle rates for the life of the product with no wear-out mechanisms. Other device features include two time-of-day alarms, a selectable output that provides either an interrupt or programmable square wave, and a calibrated 32.768kHz square-wave output. A reset input/output pin provides a power-on reset for other devices. Additionally, the reset pin is monitored as a pushbutton input for generating a reset externally. A precision temperature-compensated voltage reference and comparator circuit monitor the status of VCC to detect power failures, to provide a reset output, and to automatically switch to the backup supply for the RTC/TCXO when necessary. Additionally, the RST pin is monitored as a pushbutton input for generating a reset externally. Applications Servers Utility Power Meters Telematics GPS Features ♦ Integrated 32.768kHz Crystal ♦ Fast (400kHz) I2C Interface ♦ RTC Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap Year Compensation Valid Up to 2100 ♦ RTC Accuracy ±2ppm from 0°C to +40°C ♦ RTC Accuracy ±3.5ppm from -40°C to 0°C and +40°C to +85°C ♦ Nonvolatile Memory with 10 Years of Guaranteed Backup Time and Write Protection ♦ Two Available Densities of Nonvolatile Memory 2048 Bytes (DS32B35) 8192 Bytes (DS32C35) ♦ No Cycle Limitations on Memory ♦ Power-Switching Circuit Selects Between Main Power and Battery Backup for the RTC ♦ Programmable Square Wave with Frequency of 32.768kHz, 8.192kHz, 4.096kHz, or 1Hz ♦ Two Time-of-Day Alarms ♦ Reset Output/Pushbutton Reset (Debounced) Input ♦ Programmable Output Provides Interrupt or Square Wave ♦ Calibrated 32.768kHz Open-Drain Output ♦ Temp Sensor with ±3°C Accuracy ♦ 3.3V Operating Voltage ♦ Commercial and Industrial Temperature Ranges ♦ 300-mil, 20-Pin SO Package ♦ Underwriters Laboratories (UL) Recognized Ordering Information PART DS32B35-33# DS32B35-33IND# DS32C35-33# DS32C35-33IND# TEMP RANGE PIN-PACKAGE 0°C to +70°C 20 SO -40°C to +85°C 20 SO 0°C to +70°C 20 SO -40°C to +85°C 20 SO #Denotes a RoHS-compliant device that may include lead that is exempt under RoHS requirements. The lead finish is JESD97 category e3, and is compatible with both lead-based and leadfree soldering processes. A "#" anywhere on the top mark denotes a RoHS-compliant device. Typical Operating Circuit, Pin Configuration, and Selector Guide appear at end of data sheet. ______________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. DS32B35/DS32C35 General Description DS32B35/DS32C35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground......-0.3V to +5.0V Operating Temperature Range ..........................-40°C to +85°C Junction Temperature ......................................................+125°C Storage Temperature Range ...............................-40°C to +85°C Junction-to-Ambient Thermal Resistance (θJA) (Note 1)....55°C/W Note 1: Junction-to-Case Thermal Resistance (θJC) (Note 1) ......24°C/W Lead Temperature (soldering, 10s) .................................+260°C Soldering Temperature (reflow, 2x max)..........................+260°C (See the Handling, PC Board Layout, and Assembly section.) Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC 2.70 3.3 3.63 V Battery Voltage VBAT (Note 4) 2.3 3.0 3.6 V Input High Voltage VIH (Note 5) 0.7 x VCC VCC + 0.3 V Input Low Voltage VIL -0.3 +0.3 x VCC V MAX UNITS ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP Accessing RTC 260 Accessing FRAM memory 260 Active Supply Current ICCA VCC = 3.63V, SCL = 400kHz (Note 6) Standby Supply Current ICCS VCC = 3.63V, SCL = 0kHz, 32kHz on, SQW off (Note 6) 110 μA Temperature Conversion Current ITC VCC = 3.65V, SCL = 0kHz, 32kHz on, SQW off 575 μA Power-Fail Voltage VPF 2.70 V Logic 0 Output 32kHz, INT/SQW, SDA VOL I OL = 3mA 0.4 V Logic 0 Output RST VOL I OL = 1mA 0.4 V -1 +1 μA -1 +1 μA -200 +10 Output Leakage Current 32kHz, INT/SQW, SDA ILEAK Input Leakage SCL ILI RST I/O Leakage I OL WP Input Resistance 2 RIN 2.45 Output high impedance RST high impedance (Note 7) 2.575 μA μA VIN = VIL(MAX) 50 k VIN = VIH(MIN) 1 M _____________________________________________________________________ Accurate I2C RTC with Integrated TCXO/Crystal/FRAM DS32B35/DS32C35 ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.7V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER VBAT Leakage Current (VCC Active) Output Frequency Frequency Stability vs. Temperature SYMBOL CONDITIONS MIN IBATLKG f OUT f/f OUT VCC = 3.3V or VBAT = 3.3V VCC = 3.3V or VBAT = 3.3V Frequency Sensitivity per LSB Temperature Sensor Accuracy Temp Temperature Conversion Time tCONV UNITS 25 100 nA 32.768 kHz -3.5 +3.5 0°C to +40°C -2 +2 -3.5 f/V f/LSB MAX -40°C to 0°C -40°C to +85°C Frequency Stability vs. Voltage TYP +3.5 1 Specified at: -40°C 0.7 +25°C 0.1 +70°C 0.4 +85°C 0.8 VCC = 3.3V or VBAT = 3.3V ppm -3 ppm/V ppm +3 °C 125 200 ms TYP MAX UNITS 70 μA 3.0 μA 575 μA 100 nA ELECTRICAL CHARACTERISTICS (VCC = 0V, VBAT = 2.3V to 3.6V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN IBATA EOSC = 0, BBSQW = 0, SCL = 400kHz (Note 5) Timekeeping Battery Current IBATT EOSC = 0, BBSQW = 0, EN32kHz = 1, VBAT = 3.6V SCL = SDA = 0V or SCL = SDA = VBAT (Note 6) Temperature Conversion Current IBATTC EOSC = 0, BBSQW = 0, SCL = SDA = 0V or SCL = SDA = VBAT Data-Retention Current (RTC/TCXO Registers) IBATDR EOSC = 1, SCL = SDA = 0V, +25°C Active Battery Current VBAT = 3.6V VBAT = 3.6V 0.84 _____________________________________________________________________ 3 DS32B35/DS32C35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL SCL Clock Frequency f SCL Bus Free Time Between STOP and START Conditions tBUF Hold Time (Repeated) START Condition (Note 8) tHD:STA Low Period of SCL Clock tLOW High Period of SCL Clock tHIGH Data Hold Time (Notes 9, 10) tHD:DAT Data Setup Time (Note 11) t SU:DAT Setup Time for Repeated START Condition t SU:STA Rise Time of Both SDA and SCL Signals (Note 12) tR Fall Time of Both SDA and SCL Signals (Note 12) tF Setup Time for STOP Condition t SU:STO Capacitive Load for Each Bus Line (Note 12) CB I/O Capacitance INT/SQW, 32kHz, SCL, SDA CI/O Pushbutton Debounce PBDB Reset Active Time tRST Oscillator Stop Flag (OSF) Delay t OSF FRAM Data Retention tDR 4 CONDITIONS Fast mode Standard mode MIN 0 100 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 0 Standard mode 0 Fast mode 100 Standard mode 250 Fast mode 0.6 Standard mode 4.7 Standard mode Fast mode Standard mode MAX 400 Fast mode Fast mode TYP 100 μs μs μs 0.9 Standard mode 4.0 μs 300 1000 300 300 10 18 (See the Pushbutton Reset Timing diagram) 250 (Note 13) _____________________________________________________________________ 10 ns ns μs 400 Outputs = high impedance μs ns 20 + 0.1CB 0.6 kHz μs 20 + 0.1CB Fast mode UNITS pF pF ms 250 ms 100 ms Years Accurate I2C RTC with Integrated TCXO/Crystal/FRAM (TA = -40°C to +85°C, Note 2, see the Power-Switch Timing diagram.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC Fall Time; VPF(MAX) to VPF(MIN) t VCCF 300 μs VCC Rise Time; V PF(MIN) to VPF(MAX) t VCCR 0 μs Recovery at Power-Up tREC (Note 14) 300 ms WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data. Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Limits at -40°C are guaranteed by design and not production tested. All voltages are referenced to ground. To minimize current drain on VBAT when the internal supply is switched to VBAT, the VIH minimum must be higher than VBAT - 0.6V. Otherwise, there is significant current drain due to the input stage at the SCL and SDA pins. The pullup resistor voltage on the 32kHz and INT/SQW pins can be up to 5.5V maximum regardless of the voltage on VCC. Current is the averaged input current, which includes the temperature conversion current. The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. CB—total capacitance of one bus line in pF. The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤ VCC ≤ VCC(MAX) and 2.0V ≤ VBAT ≤ 3.6V. This delay applies only if the oscillator is enabled and running. If the EOSC bit is a 1, tREC is bypassed and RST immediately goes high. The state of RST does not affect the I2C interface, RTC, TCXO, or FRAM operation. _____________________________________________________________________ 5 DS32B35/DS32C35 POWER-SWITCH CHARACTERISTICS Accurate I2C RTC with Integrated TCXO/Crystal/FRAM DS32B35/DS32C35 Pushbutton Reset Timing RST PBDB tRST Power-Switch Timing VCC VPF(MAX) VPF VPF VPF(MIN) tVCCF tVCCR tREC RST 6 _____________________________________________________________________ Accurate I2C RTC with Integrated TCXO/Crystal/FRAM 125 1.2 DS32x35 toc01 150 RST ACTIVE 1.1 IBAT (μA) ICCS (μA) VCC = 0V, BSY = 0, SDA = SCL = VBAT OR VCC 1.0 100 75 DS32x35 toc02 SUPPLY CURRENT vs. SUPPLY VOLTAGE STANDBY SUPPLY CURRENT vs. SUPPLY VOLTAGE EN32kHz = 1 0.9 EN32kHz = 0 0.8 50 0.7 BSY = 0, SDA = SCL = VCC 0 2.5 3.0 3.5 4.0 4.5 5.0 0.6 3.3 4.3 5.3 VCC (V) VBAT (V) SUPPLY CURRENT vs. TEMPERATURE FREQUENCY DEVIATION vs. TEMPERATURE vs. AGING VALUE DS32x35 toc03 1.0 VCC = 0V, EN32kHz = 1, BSY = 0, SDA = SCL = VBAT OR GND 0.9 IBAT (μA) 2.3 5.5 0.8 0.7 60 50 FREQUENCY DEVIATION (ppm) 2.0 -128 DS32x35 toc04 25 40 -33 30 20 0 10 0 -10 32 -20 -30 127 -40 0.6 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _____________________________________________________________________ 7 DS32B35/DS32C35 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) Accurate I2C RTC with Integrated TCXO/Crystal/FRAM DS32B35/DS32C35 Block Diagram VCC DS32B35/DS32C35 X1 CONTROL LOGIC/ DIVIDER X2 WP SCL RST OSCILLATOR AND CAPACITOR ARRAY PUSHBUTTON RESET; SQUARE-WAVE BUFFER; INT/SQW CONTROL N 32kHz FRAM N VCC VBAT POWER CONTROL TEMPERATURE SENSOR CONTROL AND STATUS REGISTERS GND N CLOCK AND CALENDAR REGISTERS SCL I2C INTERFACE AND ADDRESS REGISTER DECODE SDA 8 INT/SQW USER BUFFER (7 BYTES) _____________________________________________________________________ Accurate I2C RTC with Integrated TCXO/Crystal/FRAM PIN NAME FUNCTION 1 WP Write Protect. When WP is high, the entire FRAM memory array is write protected. When WP is low, all addresses can be written. This pin is internally pulled down. 2, 7–14 N.C. No Connection. Must be connected to ground. 3 32kHz 4 VCC 32kHz Output. This open-drain pin requires an external pullup resistor. When enabled, the output operates on either power supply. It can be left open if not used. DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1μF to 1.0μF capacitor. INT/SQW Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor connected to VCC or another supply of 5.5V or less. It can be left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is determined by the RS2 and RS1 bits. When INTCN is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled. 6 RST Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the VPF specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the open-drain pulldown transistor is shut off, and the internal pullup resistor pulls the RST pin to VCC. The activelow, open-drain output is combined with a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has an internal 50k nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the EOSC bit is 1, tREC is bypassed and RST immediately goes high. 15, 19 GND Ground. Must be connected together to ground. 16 VBAT Backup Power-Supply Input. When using the device with the VBAT input as the primary power source, this pin should be decoupled using a 0.1μF to 1.0μF low-leakage capacitor. When using the device with the VBAT input as the backup power source, the capacitor is not required. If VBAT is not used, connect to ground. The devices are UL recognized to ensure against reverse charging when used with a primary lithium battery. Go to www.maxim-ic.com/qa/info/ul. 17 SDA Serial Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin requires an external pullup resistor. 18, 20 SCL Serial Clock Input. These pins are the clock input for the I2C serial interface and are used to synchronize data movement on the serial interface. 5 Detailed Description The DS32B35/DS32C35 accurate RTCs are clock/calendars that include an integrated TCXO, crystal, and a bank of nonvolatile memory (FRAM) in a single package. The nonvolatile memory is available in two sizes: 2048 x 8 or 8192 x 8 bits. The integration of the crystal resonator enhances the long-term accuracy of the device as well as reduces the piece part count in a manufacturing line. The devices are available in both commercial and industrial temperature ranges and is offered in a 300-mil, 20-pin SO package. The DS32B35/DS32C35 include a bank of nonvolatile memory that do not require a backup energy source to maintain the memory contents. In addition, there are no read or write cycle limitations. The memory array can be accessed at maximum cycle rates for the life of the product with no wear-out mechanisms. A precision temperature-compensated reference and comparator circuit monitors the status of VCC and automatically switches to the backup supply when necessary. Other device features include two time-of-day alarms, a selectable output that provides either an interrupt or programmable square wave, and a calibrated 32.768kHz square-wave output. A reset input/output pin provides a power-on reset. Additionally, the reset pin is monitored as a pushbutton input for generating a reset externally. The devices are accessed through an I2C serial interface. _____________________________________________________________________ 9 DS32B35/DS32C35 Pin Description DS32B35/DS32C35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Operation The Block Diagram shows the main elements of the DS32B35/DS32C35. The nine blocks can be grouped into six functional groups: TCXO, power control, pushbutton function, RTC, I2C interface, and FRAM. Their operations are described separately in the following sections. 32kHz TCXO The temperature sensor, oscillator, and control logic form the TCXO. The controller reads the output of the on-chip temperature sensor and uses a lookup table to determine the capacitance required, adds the aging correction in the AGE register, and then sets the capacitance selection registers. New values, including changes to the AGE register, are loaded only when a change in the temperature value occurs, or when a user-initiated temperature conversion is completed. The temperature is read on initial application of VCC and once every 64 seconds afterwards while the device is powered by either VCC or VBAT. Power Control This function is provided by a temperature-compensated voltage reference and a comparator circuit that monitors the VCC level. When VCC is greater than VPF, the part is powered by VCC. When VCC is less than VPF but greater than VBAT, the RTC is powered by VCC. If VCC is less than VPF and is less than VBAT, the device is powered by VBAT. See Table 1. The RTC can be accessed when the device is powered by either VCC or VBAT. The FRAM is only accessible when the device is powered by VCC. The FRAM must not be accessed when VCC < VCC(MIN). Table 1. Device Operation SUPPLY CONDITION POWERED BY FRAM RTC ACCESS* ACCESS VCC < VPF, VCC < VBAT VBAT No Yes VCC < VPF, VCC > VBAT VCC No Yes VCC > VPF, VCC < VBAT VCC Yes Yes VCC > VPF, VCC > VBAT VCC Yes Yes *Read/write access is not inhibited by the device, but must not be done to avoid FRAM data errors. To preserve the battery, the first time VBAT is applied to the device, the oscillator will not start up until V CC exceeds VPF, or until a valid I2C address is written to the part. Typical oscillator startup time is less than one second. Approximately 2 seconds after VCC is applied, or a valid I2C address is written, the device makes a temperature measurement and applies the calculated 10 correction to the oscillator. Once the oscillator is running, it continues to run as long as a valid power source is available (VCC or VBAT), and the device continues to measure the temperature and correct the oscillator frequency every 64 seconds. On the first application of power (VCC) or when a valid I2C address is written to the part (VBAT), the time and date registers are reset to 01/01/00 01 00:00:00 (MM/DD/YY DOW HH:MM:SS). Pushbutton Reset Function The device provides for a pushbutton switch to be connected to the RST output pin. When the device is not in a reset cycle, it continuously monitors the RST signal for a low going edge. If an edge transition is detected, the device debounces the switch by pulling RST low. After the internal timer has expired (PBDB), the device continues to monitor the RST line. If the line is still low, the device continuously monitors the line looking for a rising edge. Upon detecting release, the device forces the RST pin low and holds it low for tRST. RST is also used to indicate a power-fail condition. When VCC is lower than VPF, an internal power-fail signal is generated, which forces the RST pin low. When VCC returns to a level above VPF, the RST pin is held low for tREC to allow the power supply to stabilize. If the oscillator is not running (see the Power Control section) when VCC is applied, tREC is bypassed and RST immediately goes high. The state of RST does not affect the operation of the TCXO, I2C interface, FRAM, or RTC functions. Real-Time Clock With the clock source from the TCXO, the RTC provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. The clock provides two programmable time-of-day alarms and a programmable square-wave output. The INT/SQW pin either generates an interrupt due to alarm condition or outputs a square-wave signal and the selection is controlled by the bit INTCN. I2C Interface The FRAM I2C interface is accessible whenever VCC is at a valid level. The RTC I2C interface is accessible whenever either VCC or VBAT is at a valid level. If a microcontroller connected to the device resets because of a loss of VCC or other event, it is possible that the microcontroller and the RTC I2C communications could become unsynchronized, e.g., the microcontroller resets while reading data from the RTC. When the microcon- ____________________________________________________________________ Accurate I2C RTC with Integrated TCXO/Crystal/FRAM time information is read from these secondary registers, while the clock continues to run. This eliminates the need to reread the registers in case the main registers update during a read. FRAM The time and calendar information is obtained by reading the appropriate register bytes. Table 3 illustrates the RTC registers. The time and calendar data are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. The device can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic-high being PM. In the 24-hour mode, bit 5 is the 20-hour bit (20 to 23 hours). The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. The day-of-week register increments at midnight. Values that correspond to the day of week are userdefined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. The serial FRAM memory is logically organized as a 2048 x 8 or 8192 x 8 memory array and is accessed using the I2C interface. Functional operation of the FRAM is similar to serial EEPROMs with the major difference being its superior performance on writes. The memory is read or written at the speed of the I2C interface. It is not necessary to poll the device for a ready condition during writes. Due to the different memory densities, the I2C addressing technique is different for each version of the device. See the I2C Serial Data Bus section for details. Table 2. Memory Slave Address DEVICE SLAVE ADDRESS DS32B35 1010 A10A9A8R DS32C35 1010 000R R = Read/write select bit Warning: The FRAM does not inhibit reads or writes when VCC is below the minimum operating voltage. FRAM reads are destructive, that is, when a read is performed, the device internally writes the memory back to the original value. The FRAM must not be read or written when VCC is below the minimum operating voltage; otherwise, the memory cells may not be fully programmed, and the data may not be retained. RTC Address Map Table 3 shows the RTC address map for the timekeeping registers. During a multibyte access, when the address pointer reaches the end of the register space, it wraps around to location 00h. On an I2C START or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The Clock and Calendar When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any START and when the register pointer rolls over to zero. The time information is read from these secondary registers while the clock continues to run. This eliminates the need to reread the registers in case the main registers update during a read. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge from the device. Once the countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within 1 second. The 1Hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer, provided that the oscillator is already running. ____________________________________________________________________ 11 DS32B35/DS32C35 troller resets, the RTC I2C interface may be placed into a known state by toggling SCL until SDA is observed to be at a high level. At that point the microcontroller should pull SDA low while SCL is high, generating a START condition. DS32B35/DS32C35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Table 3. RTC Register Map ADDRESS BIT 7 (MSB) 00h 0 10 Seconds 01h 0 10 Minutes BIT 6 02h 0 12/24 03h 0 0 04h 0 0 05h Century 0 06h BIT 5 AM/PM 20 Hour BIT 4 BIT 3 RANGE Seconds Seconds 00–59 Minutes Minutes 00–59 Hour Hours 1–12 + AM/PM 00–23 10 Hour 0 0 BIT 1 0 Day 1–7 Date Day Date 01–31 Month Month/ Century 01–12 + Century 00–99 10 Date 0 10 Month BIT 0 (LSB) FUNCTION BIT 2 Year Year 07h A1M1 10 Year 10 Seconds Seconds Alarm 1 Seconds 00–59 08h A1M2 10 Minutes Minutes Alarm 1 Minutes 00–59 09h A1M3 12/24 Hour Alarm 1 Hours 1–12 + AM/PM 00–23 0Ah A1M4 DY/DT Day Alarm 1 Day 1–7 0Bh A2M2 0Ch A2M3 12/24 0Dh A2M4 DY/DT 0Eh EOSC BBSQW CONV RS2 RS1 INTCN A2IE 0Fh OSF 0 0 0 EN32kHz BSY A2F 10h Sign Data Data Data Data Data AM/PM 20 Hour 10 Hour 10 Date 10 Minutes AM/PM 20 Hour Date Alarm 1 Date 1–31 Minutes Alarm 2 Minutes 00–59 Hour Alarm 2 Hours 1–12 + AM/PM 00–23 10 Hour 10 Date Day Alarm 2 Day 1–7 Date Alarm 2 Date 1–31 A1IE Control — A1F Control/Status — Data Data Aging Offset — 11h Sign Data Data Data Data Data Data Data MSB of Temp — 12h Data Data 0 0 0 0 0 0 LSB of Temp — Note: Unless otherwise specified, the registers’ state is not defined when power is first applied. Bits indicated as 0 can be written to a 1 or 0, but always read back as 0. 12 ____________________________________________________________________ Accurate I2C RTC with Integrated TCXO/Crystal/FRAM possible settings. Configurations not listed in the table will result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the alarm is the result of a match with date of the month. If DY/DT is written to logic 1, the alarm is the result of a match with day of the week. When the RTC register values match alarm register settings, the corresponding Alarm Flag (“A1F”) or (“A2F”) bit is set to logic 1. If the corresponding alarm interrupt enable (“A1IE”) or (“A2IE”) is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition will activate the INT/SQW signal. The DS32B35/DS32C35 contain two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the alarm enable and INTCN bits of the Control register) to activate the INT/SQW output on an alarm match condition. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Table 4). When all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers match the corresponding values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 4 shows the Table 4. Alarm Mask Bits DY/DT ALARM 1 REGISTER MASK BITS (BIT 7) A1M4 A1M3 A1M2 A1M1 ALARM RATE X 1 1 1 1 Alarm once per second. X 1 1 1 0 Alarm when seconds match. X 1 1 0 0 Alarm when minutes and seconds match. X 1 0 0 0 Alarm when hours, minutes, and seconds match. 0 0 0 0 0 Alarm when date, hours, minutes, and seconds match. 1 0 0 0 0 Alarm when day, hours, minutes, and seconds match. DY/DT ALARM 2 REGISTER MASK BITS (BIT 7) ALARM RATE A2M4 A2M3 A2M2 X 1 1 1 Alarm once per minute (00 seconds of every minute). X 1 1 0 Alarm when minutes match. X 1 0 0 Alarm when hours and minutes match. 0 0 0 0 Alarm when date, hours, and minutes match. 1 0 0 0 Alarm when day, hours, and minutes match. ____________________________________________________________________ 13 DS32B35/DS32C35 Alarms DS32B35/DS32C35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Control Register (0Eh) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE Special-Purpose Registers Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. Table 5 shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (8.192kHz) when power is first applied. Bit 2: Interrupt Control (INTCN). This bit controls the INT/SQW signal. When the INTCN bit is set to logic 0, a square wave is output on the INT/SQW pin. When the INTCN bit is set to logic 1, then a match between the timekeeping registers and either of the alarm registers activates the INT/SQW output (if the alarm is also enabled). The corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to logic 1 when power is first applied. Control Register (0Eh) Bit 7: Enable Oscillator (EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped when the device switches to VBAT. This bit is clear (logic 0) when power is first applied. When the device is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit. Bit 6: Battery-Backed Square-Wave Enable (BBSQW). When set to logic 1 with INTCN = 0 and VCC < VPF, this bit enables the square wave. When BBSQW is logic 0, the INT/SQW pin goes high impedance when VCC < VPF. This bit is disabled (logic 0) when power is first applied. Bit 5: Convert Temperature (CONV). When the device is in idle state, setting this bit to 1 forces the temperature sensor to convert the temperature into digital code and execute the TCXO algorithm to update the capacitance load for the oscillator. This can only happen when a conversion is not already in progress. The user should check the status bit BSY before forcing the controller to start a new TCXO execution. A user-initiated temperature conversion does not affect the internal 64second update cycle. Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate the INT/SQW signal. The A1IE bit is disabled (logic 0) when power is first applied. Table 5. Interrupt/Square-Wave Output 14 INT/SQW OUTPUT INTCN A2IE A1IE 0 1Hz 0 X X 1 1.024kHz 0 X X 1 0 4.096kHz 0 X X 1 1 8.192kHz 0 X X 1 X X A1F 1 0 1 1 X X A2F 1 1 0 1 X X A2F + A1F 1 1 1 INTCN RS2 RS1 0 0 0 0 0 0 ____________________________________________________________________ Accurate I2C RTC with Integrated TCXO/Crystal/FRAM BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OSF 0 0 0 EN32kHz BSY A2F A1F Status Register (0Fh) Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltages present on both VCC and VBAT are insufficient to support oscillation. 3) The EOSC bit is turned off in battery-backed mode. 4) External influences on the crystal (i.e., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. Bit 3: Enable 32kHz Output (EN32kHz). This bit controls the status of the 32kHz pin. When set to logic 1, the 32kHz pin is enabled and outputs a 32.768kHz square-wave signal. When set to logic 0, the 32kHz pin goes to a high-impedance state. The initial power-up state of this bit is logic 1, and a 32.768kHz square-wave signal appears at the 32kHz pin after a VCC is applied to the device. Bit 2: Busy (BSY). This bit indicates the device is busy executing TCXO functions. It goes to logic 1 when the conversion signal to the temperature sensor is asserted and then is cleared when the device is in the 1-minute idle state. When active, the BSY signal prevents the CONV signal from aborting the execution of the TCXO algorithm and starting a new execution of TCXO function. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If the A2IE bit is logic 1 and the INTCN bit is set to logic 1, the INT/SQW pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is logic 1 and the INTCN bit is set to logic 1, the INT/SQW pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Aging Offset Register (10h) The Aging Offset register provides an 8-bit code to add to the codes in the capacitance array registers. The code is encoded in two’s complement. One LSB represents one small capacitor to be switched in or out of the capacitance array at the crystal pins. The change in ppm per LSB is different at different temperatures. The frequency vs. temperature curve is distorted by the values used in this register. At +23°C, one LSB typically provides approximately 0.1ppm change in frequency. Aging Offset (10h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Sign Data Data Data Data Data Data Data ____________________________________________________________________ 15 DS32B35/DS32C35 Status Register (0Fh) DS32B35/DS32C35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Temperature Register (Upper Byte) (11h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Sign Data Data Data Data Data Data Data Temperature Register (Lower Byte) (12h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Data Data 0 0 0 0 0 0 Temperature Registers (11h–12h) Temperature is represented as a 10-bit code with a resolution of +0.25°C and is accessible at location 11h and 12h. The temperature is encoded in two’s complement format. The upper 8 bits are at location 11h, and the lower 2 bits are in the upper nibble at location 12h. Upon power reset, the registers are set to a default temperature of 0°C and the controller starts a temperature conversion. New temperature readings are stored in this register. FRAM Address Map During a multibyte access, the address pointer wraps around to location 00h when it reaches the end of the register space. DS32B35 FRAM Register Map ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RANGE 000h D7 D6 D5 D4 D3 D2 D1 D0 00–FF : : : : : : : : : : 7FFh D7 D6 D5 D4 D3 D2 D1 D0 00–FF Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. DS32C35 FRAM Register Map ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RANGE 000h D7 D6 D5 D4 D3 D2 D1 D0 00–FF : : : : : : : : : : 1FFFh D7 D6 D5 D4 D3 D2 D1 D0 00–FF Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. 16 ____________________________________________________________________ Accurate I2C RTC with Integrated TCXO/Crystal/FRAM DS32B35/DS32C35 SDA tBUF tSP tHD:STA tLOW tR tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START tSU:STO REPEATED START tHD:DAT Figure 1. Data Transfer on I2C Serial Bus SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 1 2 3–7 8 ACK 9 ACK START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED STOP CONDITION OR REPEATED START CONDITION Figure 2. I2C Data Transfer Overview I2C Serial Data Bus The DS32B35/DS32C35 support a bidirectional I2C bus and data transmission protocol (Figure 1). A device that sends data onto the bus is defined as a transmitter, and a device receiving data is defined as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The device operates as a slave on the I2C bus. Connections to the bus are made through the SCL input and open-drain SDA I/O lines. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS32B35/DS32C35 work in both modes. The following bus protocol has been defined (Figure 2): • Data transfer can be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. ____________________________________________________________________ 17 DS32B35/DS32C35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. Stop data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 18 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most significant bit (MSB) first. The DS32B35/DS32C35 can operate in the following two modes: 1) Slave receiver mode (DS32B35/DS32C35 write mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (see Figures 3, 5, and 7). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains one of the 7-bit device addresses. The slave address is 1101000 for the RTC. For the DS32B35 FRAM, the first four bits are 1010, and the next three bits select one of eight blocks of data (see Table 2). For the DS32C35 FRAM, the first seven bits are 1010000. Each slave address is followed by the direction bit (R/W), which is zero for a write. After receiving and decoding the slave address byte, the device outputs an acknowledge on the SDA line. After the device acknowledges the slave address and write bit, the master transmits a register address to the device. For the DS32C35, the master transmits two bytes for the register address information. This sets the register pointer on the device. After setting the register address, the master then transmits zero or more bytes of data with the device acknowledging each byte received. The master generates a STOP condition to terminate the data write. ____________________________________________________________________ Accurate I2C RTC with Integrated TCXO/Crystal/FRAM <SLAVE ADDRESS> <R/W> S 1101000 0 A <WORD ADDRESS (n)> XXXXXXXX blocks of data (see Table 2). Each slave address is followed by the direction bit (R/W), which is one for a read. After receiving and decoding the slave address byte, the device outputs an acknowledge on the SDA line. The device then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The device must receive a "not acknowledge" to end a read. The register pointer can be set prior to a data read by initiating a slave receiver mode sequence, with no data bytes transmitted after the register address data. <DATA (n)> A XXXXXXXX S - START SLAVE TO MASTER A - ACKNOWLEDGE P - STOP R/W - READ/WRITE OR DIRECTION BIT ADDRESS = D0h <DATA (n + 1)> A XXXXXXXX <DATA (n + X) A ... XXXXXXXX A P A P A P MASTER TO SLAVE DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) Figure 3. Data Write—RTC Slave Receiver Mode <SLAVE ADDRESS> <R/W> S 1101000 1 A <DATA (n)> XXXXXXXX <DATA (n + 1)> A S - START MASTER TO SLAVE A - ACKNOWLEDGE P - STOP A - NOT ACKNOWLEDGE R/W - READ/WRITE OR DIRECTION BIT ADDRESS = D1h XXXXXXXX <DATA (n + 2)> A XXXXXXXX <DATA (n + X)> A ... XXXXXXXX SLAVE TO MASTER DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL. Figure 4. Data Read—RTC Slave Transmitter Mode <SLAVE ADDRESS> <R/W> <WORD ADDRESS (n)> S 1010A 10 A 9 A 8 S - START A - ACKNOWLEDGE P - STOP R/W - READ/WRITE BIT 0 A A 7A 6A 5A 4A 3A 2A 1A 0 MASTER TO SLAVE <DATA (n + 1) A XXXXXXXX <DATA (n + 2)> A XXXXXXXX <DATA (n + X)> A ... XXXXXXXX SLAVE TO MASTER DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) Figure 5. Data Write—DS32B35 FRAM Slave Receiver Mode ____________________________________________________________________ 19 DS32B35/DS32C35 2) Slave transmitter mode (DS32B35/DS32C35 read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. The device transmits serial data on SDA while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (see Figure 4). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains one of the 7-bit device addresses. The slave address is 1101000 for the RTC. For the DS32B35 FRAM, the first four bits are 1010, and the next three bits select one of eight DS32B35/DS32C35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM <SLAVE ADDRESS> <R/W> S 1010A 10 A 9 A 8 1 A <DATA (n)> <DATA (n + 1)> XXXXXXXX A S - START MASTER TO SLAVE A - ACKNOWLEDGE P - STOP A - NOT ACKNOWLEDGE R/W - READ/WRITE OR DIRECTION BIT ADDRESS = D1h <DATA (n + 2)> XXXXXXXX A XXXXXXXX <DATA (n + X)> A ... XXXXXXXX A P SLAVE TO MASTER DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL. Figure 6. Data Read—DS32B35 FRAM Slave Transmitter Mode <SLAVE ADDRESS> <R/W> S 1010000 0 A S - START A - ACKNOWLEDGE P - STOP R/W - READ/WRITE BIT <WORD ADDRESS> XXXA 12 A 11 A 10 A 9 A 8 A MASTER TO SLAVE <DATA (n)> A 7A 6A 5A 4A 2A 1A 0 A XXXXXXXX <DATA (n + 1)> A ... XXXXXXXX A P A P SLAVE TO MASTER DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) Figure 7. Data Write—DS32C35 FRAM Slave Receiver Mode <SLAVE ADDRESS> <R/W> S 1010000 1 A <DATA (n)> XXXXXXXX S - START MASTER TO SLAVE A - ACKNOWLEDGE P - STOP A - NOT ACKNOWLEDGE R/W - READ/WRITE OR DIRECTION BIT ADDRESS = D1h <DATA (n + 1)> A <DATA (n + 2)> XXXXXXXX A XXXXXXXX <DATA (n + X)> A ... XXXXXXXX SLAVE TO MASTER DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL. Figure 8. Data Read—DS32C35 FRAM Slave Transmitter Mode Handling, PCB Layout, and Assembly The DS32B35/DS32C35 package contains a quartz tuning-fork crystal. Pick-and-place equipment can be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connection) pins must be connected to ground. 20 Moisture-sensitive packages are shipped from the factory dry packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications and reflow profiles. Exposure to reflow is limited to 2x maximum. ____________________________________________________________________ Accurate I2C RTC with Integrated TCXO/Crystal/FRAM VCC VCC RPU = tR/CB VCC RPU RPU SCL SCL CPU SDA WP RST N.C. N.C. N.C. N.C. N.C. PUSHBUTTON RESET VCC INT/SQW 32kHz VBAT DS32B35/ DS32C35 GND N.C. N.C. N.C. N.C. GND Pin Configuration Selector Guide PART TOP VIEW WP 1 DS32B35-33# 2k x 8 DS32B35 2k x 8 DS32B35 8k x 8 DS32C35 N.C. 2 19 GND 32kHz 3 18 SCL DS32C35-33# VCC 4 17 SDA RST 6 DS32B35/ DS32C35 TOP† MARK 20 SCL DS32B35-33IND# INT/SQW 5 FRAM DENSITY 16 VBAT 15 GND N.C. 7 14 N.C. N.C. 8 13 N.C. N.C. 9 12 N.C. N.C. 10 11 N.C. SO Chip Information SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS DS32C35-33IND# 8k x 8 DS32C35 #Denotes a RoHS-compliant device that may include lead that is exempt under RoHS requirements. The lead finish is JESD97 category e3, and is compatible with both lead-based and leadfree soldering processes. A "#" anywhere on the top mark denotes a RoHS-compliant device. †An “N” anywhere on the top mark denotes an industrial grade device. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 20 SO W20#H2 21-0042 90-0108 ____________________________________________________________________ 21 DS32B35/DS32C35 Typical Operating Circuit DS32B35/DS32C35 Accurate I2C RTC with Integrated TCXO/Crystal/FRAM Revision History REVISION NUMBER REVISION DATE 0 12/06 DESCRIPTION Initial release — Changed data sheet title/references to DS32x35 with DS32B35/DS32C35 1 2 3 1/08 4/08 7/10 PAGES CHANGED 1–21 Added text to the General Description section about the clock/date operation 1 In Table 3, changed 04h range from 00–31 to 01–31 12 Updated the RTC descriptions in the General Description and Detailed Description sections 1, 9 In the Power-Switch Characteristics table, changed tREC max from 2ms to 200ms; added RST state information to Note 13 3 In the Typical Operating Characteristics section, replaced TOCs 1 to 4 7 Changed Table 1 column headings; added information about the POR state of the time and date registers to the end of the Power Control section 10 In the Handling, PCB Layout, and Assembly section, added a limit to the number of passes through reflow 20 In the Absolute Maximum Ratings section, added the theta-JA and theta-JC thermal resistances (changed from 73°C/W and 23°C/W to 55°C/W and 24°C/W), added Note 1, and changed the soldering temperature to +260°C; changed the VBAT pin function description in the Pin Description table; changed the 10-hour bit to 20-hour bit in the Clock and Calendar section and Table 3; updated the BBSQW bit description in the Control Register (0Eh) section; amended the VBAT capacitor representation in the Typical Operating Circuit; added the land pattern no. to the Package Information table 2–5, 9, 11, 12, 14, 21 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Maxim Integrated Products, Inc.