IDT 1337CSRI

DATASHEET
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
General Description
Features
The IDT1337 device is a low power serial real-time clock
(RTC) device with two programmable time-of-day alarms
and a programmable square-wave output. Address and
data are transferred serially through an I2C bus. The device
provides seconds, minutes, hours, day, date, month, and
year information. The date at the end of the month is
automatically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates in
either the 24-hour or 12-hour format with AM/PM indicator.
• Real-Time Clock (RTC) counts seconds, minutes, hours,
day, date, month, and year with leap-year compensation
valid up to 2100
• Packaged in 8-pin MSOP, 8-pin SOIC, or 16-pin SOIC
(surface-mount package with an integrated crystal)
•
•
•
•
Applications
•
•
•
•
•
•
Telecommunication (Routers, Switches, Servers)
I2C Serial interface (Normal and Fast modes)
Two time-of-day alarms
Oscillator Stop Flag
Programmable square-wave output defaults to 32 kHz on
power-up
• Operating voltage of 1.8 to 5.5 V
• Industrial temperature range (-40 to +85°C)
Handhelds (GPS, POS terminals, MP3 players)
Set-Top Box, Digital Recording,
Office (Fax/Printers, Copiers)
Medical (Glucometer, Medicine Dispensers)
Other (Thermostats, Vending Machines, Modems, Utility
Meters, Digital Photo Frame devices)
Block Diagram
VCC
Crystal inside package
for 16-pin SOIC ONLY
X1
1 Hz/4.096 kHz/
8.192 kHz/32.768 kHz
32.768 kHz
Oscillator and
Divider
MUX/
Buffer
SQW/INTB
INTA
X2
Clock,
Calendar
Counter
Control
Logic
SCL
SDA
I2 C
Interface
1 Byte
Control
7 Bytes
Buffer
Alarm
Registers
GND
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
1
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
Pin Assignment (8-pin MSOP/SOIC)
X1
1
8
VCC
X2
2
7
SQW/INTB
INTA
3
6
SCL
GND
4
5
SDA
IDT1337
Pin Assignment (16-pin SOIC)
SCL
1
16
SDA
SQW/INTB
2
15
GND
VCC
3
14
INTA
NC
4
13
NC
NC
5
12
NC
NC
6
11
NC
NC
7
10
NC
NC
8
9
NC
IDT1337C
Pin Descriptions
Pin
Number
MSOP SOIC
Pin
Name
Pin Description/Function
1
—
X1
2
—
X2
Connections for standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 7 pF. An
external 32.768 kHz oscillator can also drive the IDT1337. In this configuration, the X1 pin
is connected to the external oscillator signal and the X2 pin is left floating.
3
14
INTA
Interrupt output. When enabled, INTA is asserted low when the time/day/date matches the
values set in the alarm registers. This pin is an open-drain output and requires an external
pull-up resistor (10 kΩ typical).
4
15
GND
Connect to ground. DC power is provided to the device on these pins.
5
16
SDA
Serial data input/output. SDA is the input/output pin for the I2C serial interface. The SDA pin
is an open-drain output and requires an external pull-up resistor (2 kΩ typical).
6
1
SCL
Serial clock input. SCL is used to synchronize data movement on the serial interface. The
SCL pin is an open-drain output and requires an external pull-up resistor (2 kΩ typical).
Square-Wave/Interrupt output. Programmable square-wave or interrupt output signal. The
SQW/INT pin is an open-drain output and requires an external pull-up resistor (10 kΩ
SQW/INTB
typical). This pin can also function as an additional interrupt pin under certain conditions
(see page 6 for details).
7
2
8
3
VCC
—
4 - 13
NC
Primary power supply. DC power is applied to this pin.
No connect. These pins are unused and must be connected to ground.
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
2
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
Typical Operating Circuit
VCC
VCC
2k
2k
CRYSTAL
VCC
X1
VCC
X2
SCL
CPU
SDA
10k
10k
SQW/INTB
IDT1337
INTA
GND
Detailed Description
Effective Load Capacitance
Communications to and from the IDT1337 occur serially
over an I2C bus. The IDT1337 operates as a slave device on
the serial bus. Access is obtained by implementing a START
condition and providing a device identification code,
followed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed. The device
is fully accessible through the I2C interface whenever VCC
is between 5.5 V and 1.8 V. I2C operation is not guaranteed
when VCC is below 1.8 V. The IDT1337 maintains the time
and date when VCC is as low as 1.3 V.
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommended load capacitance of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
The following sections discuss in detail the Oscillator block,
Clock/Calendar Register Block and Serial I2C block.
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout are important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design for these oscillators, losses caused by
parasitic currents can have a significant impact on the
overall oscillator performance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
In the above figure, X1 and X2 are the crystal pins of our
device. Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitance. Cex1 and Cex2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
The key parameters when selecting a 32 kHz crystal to work
with IDT1337 RTC are:
• Recommended Load Capacitance
• Crystal Effective Series Resistance (ESR)
• Frequency Tolerance
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
3
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
Note: IDT1337CSRI integrates a standard 32.768 kHz
crystal in the package and contributes an additional
frequency error of 10ppm at nominal VCC (+3.3 V) and
TA=+25°C.
ESR (Effective Series Resistance)
PCB Layout
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
Frequency Tolerance
The frequency tolerance for 32 KHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1337
typically have a frequency tolerance of +/-20ppm at +25°C.
1337
Specifications for a typical 32 kHz crystal used with our
device are shown in the table below.
Parameter
Symbol
Nominal Freq.
fO
Series Resistance
ESR
Load Capacitance
CL
Min
Typ
PCB Assembly, Soldering and Cleaning
Max Units
32.768
Board-assembly production process and assembly quality
can affect the performance of the 32 KHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
kHz
50
7
kΩ
pF
PCB Design Consideration
• Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
• Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
• Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
• The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
• To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
4
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
Address Map
Table 2 (Timekeeper Registers) shows the address map for the IDT1337 registers. During a multibyte access, when the
address pointer reaches the end of the register space (0Fh), it wraps around to location 00h. On an I2C START, STOP, or
address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read
the registers in case of an update of the main registers during a read.
Table 1. Timekeeper Registers
Address
Bit 7
Bit 6
Bit 5
00h
0
10 seconds
01h
0
10 minutes
02h
0
12/24
03h
0
0
04h
0
0
05h
Century
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Range
Seconds
Seconds
00 - 59
Minutes
Minutes
00 - 59
Hour
Hours
1 - 12 +
AM/PM
00 - 23
Day
1-7
Date
Date
01 - 31
Month
Month/Century
01 - 12 +
Century
Year
Year
00 - 99
AM/PM
06h
10 hour
10 hour
0
0
0
Day
10 date
0
10 month
10 year
07h
A1M1
10 seconds
Seconds
Alarm 1
Seconds
00 - 59
08h
A1M2
10 minutes
Minutes
Alarm 1
Minutes
00 - 59
09h
A1M3
12/24
Hour
Alarm 1 Hours
1 - 12 +
AM/PM
00 - 23
0Ah
A1M4
DY/DT
Day,
Alarm 1 Day
1-7
Date
Alarm 1 Date
1 - 31
0Bh
A2M2
Minutes
Alarm 2
Minutes
00 - 59
0Ch
A2M3
12/24
Hour
Alarm 2 Hours
1 - 12 +
AM/PM
00 - 23
0Dh
A2M4
DY/DT
Day,
Alarm 2 Day
1-7
Date
Alarm 2 Date
1 - 31
0Eh
EOSC
0
0
RS2
RS1
INTCN
A2IE
A1IE
Control
0Fh
OSF
0
0
0
0
0
A2F
A1F
Status
AM/PM
10 hour
10 hour
10 date
10 minutes
AM/PM
10 hour
10 hour
10 date
Note: Unless otherwise specified, the state of the registers are not defined when power is first applied or when VCC falls below the VCCT
min
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
5
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Clock and Calendar
Alarms
The time and calendar information is obtained by reading
the appropriate register bytes. The RTC registers are
illustrated in Table 1. The time and calendar are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) format.
The IDT1337 contains two time of day/date alarms. Alarm 1
can be set by writing to registers 07h to 0Ah. Alarm 2 can be
set by writing to registers 0Bh to 0Dh. The alarms can be
programmed (by the INTCN bits of the Control Register) to
operate in two different modes—each alarm can drive its
own separate interrupt output or both alarms can drive a
common interrupt output. Bit 7 of each of the
time-of-day/date alarm registers are mask bits (Table 1).
When all of the mask bits for each alarm are logic 0, an
alarm only occurs when the values in the timekeeping
registers 00h–06h match the values stored in the
time-of-day/date alarm registers. The alarms can also be
programmed to repeat every second, minute, hour, day, or
date. Table 2 (Alarm Mask Bits table) shows the possible
settings. Configurations not listed in the table result in
illogical operation
The day-of-week register increments at midnight. Values
that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries result in
undefined operation.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any start or stop and when the register
pointer rolls over to zero.
The DY/DT bits (bit 6 of the alarm day/date registers) control
whether the alarm value stored in bits 0 to 5 of that register
reflects the day of the week or the date of the month. If
DY/DT is written to a logic 0, the alarm is the result of a
match with date of the month. If DY/DT is written to a logic
1, the alarm is the result of a match with day of the week.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur on the acknowledge
pulse from the device. To avoid rollover issues, once the
countdown chain is reset, the remaining time and date
registers must be written within 1 second. The 1Hz
square-wave output, if enable, transitions high 500ms after
the seconds data transfer, provided the oscillator is already
running.
When the RTC register values match alarm register
settings, the corresponding Alarm Flag (‘A1F’ or ‘A2F’) bit is
set to logic 1. If the corresponding Alarm Interrupt Enable
(‘A1IE’ or ‘A2IE’) is also set to logic 1, the alarm condition
activates one of the interrupt output (INTA or SQW/INTB)
signals. The match is tested on the once-per-second update
of the time and date registers.
The IDT1337 can be run in either 12-hour or 24-hour mode.
Bit 6 of the hours register is defined as the 12- or 24-hour
mode-select bit. When high, the 12-hour mode is selected.
In the 12-hour mode, bit 5 is the AM/PM bit with logic high
being PM. In the 24-hour mode, bit 5 is the second 10-hour
bit (20–23 hours). All hours values, including the alarms,
must be reinitialized whenever the 12/24-hour mode bit is
changed. The century bit (bit 7 of the month register) is
toggled when the years register overflows from 99–00.
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
6
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
Table 2. Alarm Mask Bits
DY/DT
Alarm 1 Register Mask Bits (Bit 7)
Alarm Rate
A1M4
A1M3
A1M2
A1M1
X
1
1
1
1
Alarm once per second.
X
1
1
1
0
Alarm when seconds match.
X
1
1
0
0
Alarm when minutes and seconds match.
X
1
0
0
0
Alarm when hours, minutes, and seconds match.
0
0
0
0
0
Alarm when date, hours, minutes, and seconds match.
1
0
0
0
0
Alarm when day, hours, minutes, and seconds match.
DY/DT
Alarm 2 Register Mask Bits (Bit 7)
Alarm Rate
A2M4
A2M3
A2M2
X
1
1
1
Alarm once per minute (00 seconds of every minute).
X
1
1
0
Alarm when minutes match.
X
1
0
0
Alarm when hours and minutes match.
0
0
0
0
Alarm when date, hours, and minutes match.
1
0
0
0
Alarm when day, hours, and minutes match.
Special-Purpose Registers
The IDT1337 has two additional registers (control and status) that control the RTC, alarms, and square-wave output.
Control Register (0Eh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EOSC
0
0
RS2
RS1
INTCN
A2IE
A1IE
Bit 7: Enable Oscillator (EOSC). This active-low bit when set to logic 0 starts the oscillator. When this bit is set to
a logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the
square wave has been enabled. Table 3 shows the square-wave frequencies that can be selected with the RS bits.
These bits are both set to logic 1 (32 kHz) when power is first applied.
Table 3. SQW/INT Output
INTCN
RS2
RS1
SQW/INTB Output
A2IE
0
0
0
1 Hz
X
0
0
1
4.096 kHz
X
0
1
0
8.192 kHz
X
0
1
1
32.768 kHz
X
1
X
X
A2F
1
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
7
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers
activate the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the
alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to
logic 0, a square wave is output on the SQW/INTB pin. This bit is set to logic 0 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the
status register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is
set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status
register to assert INTA. When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The A1IE
bit is disabled (logic 0) when power is first applied.
Status Register (0Fh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSF
0
0
0
0
0
A2F
A1F
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped
for some period of time and may be used to judge the validity of the clock and calendar data. This bit is is set to logic
1 anytime the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC is insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers.
This flag can be used to generate an interrupt on either INTA or SQW/INTB depending on the status of the INTCN
bit in the control register. If the INTCN bit is set to logic 0 and A2F is at logic 1 (and A2IE bit is also logic 1), the INTA
pin goes low. If the INTCN bit is set to logic 1 and A2F is logic 1 (and A2IE bit is also logic 1), the SQW/INTB pin
goes low. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1
leaves the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If
the A1IE bit is also a logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
8
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
I2C Serial Data Bus
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
The IDT1337 supports the I2C bus protocol. A device that
sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls
the message is called a master. The devices that are
controlled by the master are referred to as slaves. A master
device that generates the serial clock (SCL), controls the
bus access, and generates the START and STOP conditions
must control the bus. The IDT1337 operates as a slave on
the I2C bus. Within the bus specifications, a standard mode
(100 kHz maximum clock rate) and a fast mode (400 kHz
maximum clock rate) are defined. The IDT1337 works in
both modes. Connections to the bus are made via the
open-drain I/O lines SDA and SCL.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
The following bus protocol has been defined (see the “Data
Transfer on I2C Serial Bus” figure):
• Data transfer may be initiated only when the bus is not
busy.
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data valid: The state of the data line represents valid data
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The data on
the line must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions are
not limited, and are determined by the master device. The
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
9
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Data Transfer on I2C Serial Bus
bit (see the “Data Write–Slave Receiver Mode” figure). The
slave address byte is the first byte received after the START
condition is generated by the master. The slave address
byte contains the 7-bit IDT1337 address, which is 1101000,
followed by the direction bit (R/W), which is 0 for a write.
After receiving and decoding the slave address byte the
device outputs an acknowledge on the SDA line. After the
IDT1337 acknowledges the slave address + write bit, the
master transmits a register address to the IDT1337. This
sets the register pointer on the IDT1337. The master may
then transmit zero or more bytes of data, with the IDT1337
acknowledging each byte received. The address pointer
increments after each data byte is transferred. The master
generates a STOP condition to terminate the data write.
Depending upon the state of the R/W bit, two types of data
transfer are possible:
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted by
the master. The slave then returns an acknowledge bit,
followed by the slave transmitting a number of data bytes.
The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received
byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition
or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the bus is not released. Data is transferred with the
most significant bit (MSB) first.
2) Slave Transmitter Mode (Read Mode): The first byte is
received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the IDT1337 while the serial clock is input on SCL.
START and STOP conditions are recognized as the
beginning and end of a serial transfer (see the “Data
Read–Slave Transmitter Mode” figure). The slave address
byte is the first byte received after the START condition is
generated by the master. The slave address byte contains
the 7-bit IDT1337 address, which is 1101000, followed by
the direction bit (R/W), which is 1 for a read. After receiving
and decoding the slave address byte the slave outputs an
acknowledge on the SDA line. The IDT1337 then begins to
transmit data starting with the register address pointed to by
the register pointer. If the register pointer is not written to
The IDT1337 can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and
clock are received through SDA and SCL. After each byte is
received an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
10
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
before the initiation of a read mode the first address that is
read is the last one stored in the register pointer. The
IDT1337 must receive a “not acknowledge” to end a read.
Data Write – Slave Receiver Mode
Data Read (from current Pointer location) – Slave Transmitter Mode
Data Read (Write Pointer, then Read) – Slave Receive and Transmit
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
11
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Handling, PCB Layout, and Assembly
The IDT1337 package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should
be taken to ensure that excessive shocks are avioded. Ultarsonic cleaning equipment should be avioded to prevent damage
to the crystal.
Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line.
All NC (no connect) pins must be connected to ground.
Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must
be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device
(MSD) classifications.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT1337. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Voltage Range (on any pin relative to ground)
-0.3 V to +6.0 V
Storage Temperature
-55 to +125° C
Soldering Temperature
260° C
Ambient Operating Temperature
-40 to +85°C
Recommended DC Operating Conditions
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
VCC
Full operation
1.8
3.3
5.5
V
VCCT
Timekeeping
1.3
1.8
V
-40
+85
°C
0.7VCC
VCC + 0.3
V
VCC Supply Voltage
Ambient Operating Temperature
TA
Logic 1
VIH
SCL, SDA
INTA, SQW/INTB
Logic 0
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
5.5
-0.3
VIL
12
+0.3VCC
IDT1337
V
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
DC Electrical Characteristics
Unless stated otherwise, VCC = 1.8 V to 5.5 V, Ambient Temperature -40 to +85° C, Note 1
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Leakage
ILI
Note 2
-1
+1
µA
I/O Leakage
ILO
Note 3
-1
+1
µA
Logic 0 Output
VOL = 0.4 V
IOL
Note 3
3
mA
Active Supply Current
ICCA
Note 4
150
µA
Standby Current
ICCS
Notes 5, 6
1.5
µA
Typ.
Max.
Units
425
600
nA
100
nA
DC Electrical Characteristics
Unless stated otherwise, VCC = 1.3 V to 1.8 V, Ambient Temperature -40 to +85° C, Note 1
Parameter
Symbol
Conditions
Timekeeper Current (Oscillator
Enabled)
ICCTOSC Notes 5, 7, 8, 9
Data-Retention Current (Oscillator
Disabled)
ICCTDDR Notes 5, 9
Min.
AC Electrical Characteristics
Unless stated otherwise, VCC = 1.8 V to 5.5 V, Ambient Temperature -40 to +85° C, Note 1
Parameter
SCL Clock Frequency
Symbol
fSCL
Conditions
Fast Mode
Standard Mode
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START
Condition, Note 10
Low Period of SCL Clock
High Period of SCL Clock
tBUF
tHD:STA
tLOW
tHIGH
Setup Time for a Repeated START
Condition
tSU:STA
Data Hold Time, Notes 11, 12
tHD:DAT
Data Setup Time, Note 13
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
tSU:DAT
Min.
Max. Units
100
400
0
100
Fast Mode
1.3
Standard Mode
4.7
Fast Mode
0.6
Standard Mode
4.0
Fast Mode
1.3
Standard Mode
4.7
Fast Mode
0.6
Standard Mode
4.0
Fast Mode
0.6
Standard Mode
4.7
Fast Mode
0
Standard Mode
0
Fast Mode
100
Standard Mode
250
13
Typ.
kHz
µs
µs
µs
µs
µs
0.9
µs
ns
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
Parameter
RTC
Symbol
Rise Time of Both SDA and SCL
Signals, Note 14
tR
Fall Time of Both SDA and SCL Signals,
Note 14
tF
Setup Time for STOP Condition
tSU:STO
Capacitive Load for Each Bus Line,
Note 14
CB
I/O Capacitance (SDA, SCL)
CI/O
Conditions
Min.
Typ.
Max. Units
Fast Mode
20 + 0.1CB
300
Standard Mode
20 + 0.1CB
1000
Fast Mode
20 + 0.1CB
300
Standard Mode
20 + 0.1CB
300
Fast Mode
0.6
Standard Mode
4.0
ns
ns
µs
400
pF
Note 15
10
pF
32.768 kHz Clock Accuracy with
External Crystal
TA=25°C
VCC=3.3 V
±10
ppm
32.768 kHz Clock Accuracy with
Internal Crystal
TA=25°C
VCC=3.3 V
(crystal accuracy
±20ppm)
±30
ppm
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: SCL only.
Note 3: SDA, INTA, and SQW/INTB.
Note 4: ICCA—SCL clocking at maximum frequency = 400 kHz, VIL = 0.0V, VIH = VCC.
Note 5: Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6: SQW enabled.
Note 7: Specified with the SQW function disabled by setting INTCN = 1.
Note 8: Using recommended crystal on X1 and X2.
Note 9: The device is fully accessible when 1.8 < VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC <
1.8 V.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) +
tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released.
Note 14: CB—total capacitance of one bus line in pF.
Note 15: Guaranteed by design. Not production tested.
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
14
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
Timing Diagram
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
15
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Typical Operating Characteristics
Icc vs Vcc
IccA vs Vcc
900
10
800
8
600
Icc (uA)
Icc (nA)
700
INTCN=1
INTCN=0
500
6
ICCA
4
400
2
300
200
0
1.3
2.3
3.3
4.3
5.3
1.3
2.3
3.3
Vcc (V)
5.3
Oscillator Frequency vs Vcc
(as measured on one IDT1337C sample)
Icc vs Temperature
32768.4
800
700
Frequency (Hz)
32768.38
600
Icc (nA)
4.3
Vcc (V)
INTCN=1
500
INTCN=0
400
32768.36
32768.34
Freq
32768.32
300
32768.3
200
-40
-20
0
20
40
60
1.3
80
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
2.3
3.3
4.3
5.3
Vcc(V)
Temperature (C)
16
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
Thermal Characteristics for 8SOIC
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Thermal Resistance Junction to
Ambient
θ JA
Still air
150
° C/W
θ JA
1 m/s air flow
140
° C/W
θ JA
3 m/s air flow
120
° C/W
Thermal Resistance Junction to Case
θ JC
40
° C/W
Thermal Characteristics for 8MSOP
Parameter
Symbol
Thermal Resistance Junction to
Ambient
θJA
Thermal Resistance Junction to Case
θJC
Conditions
Min.
Still air
Typ.
Max. Units
95
° C/W
48
° C/W
Thermal Characteristics for 16SOIC
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
Symbol
Conditions
Min.
Typ.
Max. Units
θJA
Still air
120
° C/W
θJA
1 m/s air flow
115
° C/W
θJA
3 m/s air flow
105
° C/W
58
° C/W
θJC
17
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Marking Diagram (8 SOIC)
Marking Diagram (8 MSOP)
8
37GI
YWW$
5
IDT1337
DCGI
#YYWW$
Marking Diagram (16 SOIC)
16
1
9
4
IDT
1337CSRI
#YYWW**$
1
8
Notes:
1. # = product stepping.
2. $ = assembler code.
3. ** = sequential code number for traceability.
4. YYWW is the last two digits of the year and week that the part was assembled.
5. “G” denotes RoHS compliant package.
6. “I” denotes industrial grade.
7. Bottom marking: country of origin if not USA.
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
18
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
8
Symbol
E
Min
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Inches
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
B
SEATING
PLANE
L
.10 (.004)
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
C
19
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Package Outline and Package Dimensions (8-pin MSOP, 3.00 mm Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
8
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
IN D E X
AREA
1
2
D
Min
Max
-1.10
0
0.15
0.79
0.97
0.22
0.38
0.08
0.23
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 Basic
0.40
0.80
0°
8°
0.10
Inches*
Min
Max
-0.043
0
0.006
0.031
0.038
0.008
0.015
0.003
0.009
0.118 BASIC
0.193 BASIC
0.118 BASIC
0.0256 Basic
0.016
0.032
0°
8°
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
-C e
b
S E A T IN G
P LA N E
L
aaa
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
C
20
IDT1337
REV J 111009
IDT1337
REA LTIME CLOCK WITH SERIAL INTERFACE
RTC
Package Outline and Package Dimensions (16-pin SOIC, 300 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
16
Symbol
E1
A
A1
A2
b
c
D
E
E1
e
L
α
aaa
E
INDEX
AREA
1 2
D
A
2
Min
Inches*
Max
-2.65
0.10
-2.05
2.55
0.33
0.51
0.18
0.32
10.10
10.50
10.00
10.65
7.40
7.60
1.27 Basic
0.40
1.27
0°
8°
0.10
Min
Max
-0.104
0.0040
-0.081
0.100
0.013
0.020
0.007
0.013
0.397
0.413
0.394
0.419
0.291
0.299
0.050 Basic
0.016
0.050
0°
8°
0.004
*For reference only. Controlling dimensions in mm.
A
A
1
c
- Ce
b
SEATING
PLANE
L
aaa
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
1337DVGI
1337DVGI8
1337CSRI
1337CSRI8
1337DCGI
1337DCGI8
see page 18
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
8-pin MSOP
8-pin MSOP
16-pin SOIC
16-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
C
C
C
C
C
C
The 1337C packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the
integrated crystal (as designated with a “C” before the two-letter package code) may include lead that is exempt under RoHS
requirements. The lead finish is JESD91 category e3.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
21
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Revision History
Rev.
Originator
Date
A
S. Sharma
06/26/07
New device. Preliminary release.
B
J. Sarma
10/31/07
Added 8-pin SOIC package and ordering info.
C
J. Sarma
01/16/08
Updates to Pin Descriptions, load capacitance, Timekeeper Registers table, and
Recommended DC Operating Conditions table.
D
J. Sarma
03/03/08
Added top-side device markings.
E
J. Sarma
03/18/08
Revised top-side markings.
F
J. Sarma
03/28/08
Added new note to Part Ordering information pertaining to RoHS compliance and Pb-free
devices.
G
J. Sarma
05/19/08
Changed the part number for the RoHS compliant 16pin SOIC package with Xtals for
IDT1337CSOGI to IDT1337CSRI
H
J. Sarma
12/02/08
Updated Block diagram, Pin descriptions, Typical Operating Circuit diagram, Detailed
Description section, Typical Operating Characteristics graphs.
11/10/09
Added “Handling, PCB Layout, and Assembly” section.
J
Description of Change
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
22
IDT1337
REV J 111009
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
IDT™ REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
24
IDT1337
REV J 111009