TI UCC5696PN

SLVS406B – JUNE 2002 – REVISED JUNE 2003
FEATURES
D Meets Ultra2 (SPI-2 LVD SCSI), Ultra3, Ultra
D
D
D
D
DESCRIPTION
The UCC5696 is a 27-line LVD only SCSI
programmable terminator. The nominal settings
on power up are compliant to SPI-2 through SPI-4.
The programmable settings are used for SPI-5.
The UCC5696 uses the I2C to program the
differential impedance and the differential bias
current.
The
differential
impedance
is
programmed in 5-Ω increments from 55 Ω to
130 Ω using 4 bits (16 steps). The differential bias
current is programmed in 50 µA from 0.7 mA to
1.45 mA using 4 bits (16 steps). The UCC5696
has the SPI-3 mode change delay, the typical
value is 200 ms.
160 (SPI-3), Ultra320 (SPI-4), and Ultra640
(SPI-5) Standards
2.7-V to 5.25-V Termpwr Operation
Differential Fail-Safe Bias
I2C Bus Adjustable Impedance and
Differential Bias Current
80-Pin Low Profile Quad Flat Pack Package
(QFP)
APPLICATION DIAGRAM
Termpower
8
UCC5696
L1+ 1
PVDD
1
L1+
L1– 2
2
L1–
7
TERMPWR
TERMPWR 7
CONTROL LINES (9)
4.7 µ F
50 ICBD
UCC5696
PVDD 8
L9+ 30
30 L9+
L9– 29
29 L9–
DIFSENS 15
I2 CBUS
15
20 kΩ
4.7µ F
DIFSENS
ICBD 50
I2 CBUS
20 kΩ
51 ICBC
ICBC 51
DIFFB
16
16
0.1 µF
49 ICAD0
I2 C Address
DIFFB
0.1 µF
L10+ 32
32 L10+
L10– 31
31 L10–
ICAD0 49
I2 C Address
DATA (9)
LOW BYTE 0–7
+ PARITY LINES
43 ICAD6
52
Termpower
ICAD6 43
L18+ 61
61 L18+
L18– 62
62 L18–
L19+ 63
63 L19+
DISCNCT
DISCNCT 52
L19– 64
64 L19–
DATA (9)
HIGH BYTE 8–15
+ PARITY LINES
10 REG
4.7µ F
GND
54
REG 10
4.7 µ F
L27+ 79
79 L27+
L27– 80
80 L27–
GND
54
UDG–01093
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
! "#$ ! %#&'" ( $)
(#" ! " !%$"" ! %$ *$ $! $+! ! #$ !
! (( , -) (#" %"$!!. ($! $"$!!'- "'#($
$! . '' %$ $!)
www.ti.com
1
SLVS406B – JUNE 2002 – REVISED JUNE 2003
DESCRIPTION (CONTINUED)
The UCC5696 can not be used for single-ended or HVD SCSI, the termination lines will open when it detects
either single-ended or HVD devices on the SCSI bus.
ORDERING INFORMATION
L19+
L18–
L18+
L27–
L27+
L26–
L26+
L25–
L25+
L24–
L24+
L23–
L23+
L22–
L22+
L21–
L21+
L20–
L20+
L19–
PN PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
L5–
L5+
L6–
L6+
L7–
L7+
L8–
L8+
L9–
L9+
L10–
L10+
L11–
L11+
L12–
L12+
L13–
L13+
L14–
L14+
L1+
L1–
L2+
L2–
N/C
N/C
TERMPWR
PVDD
N/C
REG
N/C
SE
LVD
HVD
DIFSENS
DIFFB
L3–
L3+
L4–
L4+
NOTE: N/C No connect
AVAILABLE OPTIONS
Disconnect
Status
Packaged Devices
TA
0°C to 70°C
Regular
UCC5696PN
LQFP
† LQFP (PN) package is available taped and reeled. Add R suffix to device
type (e.g. UCC5696PNR) to order quantities of 1000 devices per reel.
2
www.ti.com
L17–
L17+
L16–
L16+
N/C
N/C
GND
N/C
DISCNT
ICBC
ICBD
ICAD0
ICAD1
ICAD2
ICAD3
ICAD4
ICAD5
ICAD6
L15+
L15–
SLVS406B – JUNE 2002 – REVISED JUNE 2003
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)†
Parameter
UCC5696
UNIT
TERMPWR voltage
6
V
Signal line voltage
0 to 6
V
1
W
Operating junction temperature, TJ
–55 to 150
°C
Storage temperature, Tstg
–65 to 150
°C
Package power dissipation
°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage are with respect to ground. Currents are positive into, negative out of the specified terminal.
Lead temperature (soldering, 10 sec.), Tsol
300
RECOMMENDED OPERATING CONDITIONS
TERMPWR voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 5.25 V
ELECTRICAL CHARACTERISTICS
TA = 0°C to 70°C, TERMPWR = 2.7 V to 5.25 V, (unless otherwise specified, the measurements are specified at the
default impedance and bias current)
TERMPWR supply current
PARAMETER
TERMPWR supply current
TEST CONDITION
MIN
TYP
MAX
(No load)
65
Disabled terminator
2.5
TERMPWR voltage
2.7
UNITS
mA
5.25
V
MAX
UNITS
regulator
PARAMETER
TEST CONDITION
1.25-V regulator
LVD mode,
0.5 V ≤ VCM ≤ 2.0 V, all lines loaded
1.3-V regulator
Differential sense,
–5 mA ≤ IDIFSENS ≤ 50 µA
1.25-V regulator source current
LVD mode,
1.25-V regulator sink current
LVD mode,
VREG = 0 V
VREG = 3.3 V
1.3-V regulator source current
Differential sense,
1.3-V regulator sink current
Differential sense,
NOTES: 1.
2.
3.
4.
VDIFSENS = 0 V
VDIFSENS = 2.75 V
MIN
TYP
1.15
1.25
1.35
V
1.2
1.3
1.4
V
–250
–300
mA
250
300
mA
–5
–15
mA
50
200
µA
At powerup or after the device comes out of disconnect mode.
For SPI-2, SPI-3 and SPI-4.
Ensured by design and engineering test, but not production tested.
Current is the absolute value of current as some addresses are pulled high, while others are pulled low.
www.ti.com
3
SLVS406B – JUNE 2002 – REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS
TA = 0°C to 70°C, TERMPWR = 2.7 V to 5.25 V, (unless otherwise specified, the measurements are specified at the
default impedance and bias current)
differential termination (default)
PARAMETER
Differential impedance (1)
TEST CONDITION
Default
100
Steps 5, 10, 20, 40 Ω, 14% overall accuracy
Differential impedance steps
MIN
TYP
105
55
Differential bias voltage (2)
55 Ω
47.5
55
62.5
130 Ω
112
130
147
Default
Over the impedance adjustment range
Default I2C settings
Default
Differential bias ccurrent
rrent (1)
110
Steps 0.05, 0.1, 0.2, 0.4 mA, 14% overall accuracy
0.7 mA
1.45 mA
Output leakage
Disabled,
Output capacitance (3)
Single ended measurement to ground
UNITS
Ω
130
The difference between all lines at any step
Common mode impedance (1)
MAX
Ω
10
100
300
75
400
100
125
1
1.1
0.70
Ω
mV
1.45
0.6
0.7
0.8
1.25
1.45
1.65
TERMPWR 0 V < 5.25 V
mA
400
nA
3
pF
disconnect and diff sense input
PARAMETER
TEST CONDITION
DISCNT threshold
MIN
TYP
0.8
Input current DISCNT
10
Input current, ICBC, ICBD
Input current, ICAD0–6 (4)
–1
MAX
UNITS
2.0
V
30
µA
1
µA
30
µA
–1
1
µA
DIFF B single ended to LVD threshold
0.5
0.7
V
DIFF B LVD to HPD threshold
1.9
2.4
V
Input current DIFF B
10
0 V ≤ VDIFFB ≤ 2.75 V
time delay/filter
PARAMETER
TEST CONDITION
Mode change delay (2)
MIN
100
TYP
190
MAX
310
UNITS
ms
status line output characteristics
PARAMETER
Source current
Sink current
NOTES: 1.
2.
3.
4.
4
TEST CONDITION
VLOAD = 2.4 V
VLOAD = 0.4 V
MIN
MAX
UNITS
–4
–6
mA
2
5
mA
At powerup or after the device comes out of disconnect mode.
For SPI-2, SPI-3 and SPI-4.
Ensured by design and engineering test, but not production tested.
Current is the absolute value of current as some addresses are pulled high, while others are pulled low.
www.ti.com
TYP
SLVS406B – JUNE 2002 – REVISED JUNE 2003
Terminal Functions
TERMINAL
NAME
FUNCTION
NO.
I/O
DIFSENS
15
O
The SCSI bus DIFF SENSE line detects what types of devices are connected to the SCSI bus.
DISCNT
52
I
The disconnect pin shuts down the terminator when it is not at the end of the bus. The disconnect pin low enables the terminator.
DIFFB
16
I
Senses the bus mode, a 50-Hz filter is required, 0.1 µF to ground and 20 kΩ to the SCSI bus DIFF SENSE line
with internal SPI-3 100-ms to 310-ms delay.
HVD
14
O
ICBD
50
I/O
ICBC
51
I
A high-voltage differential voltage level has been detected on the DIFF B pin. HVD pin high indicates that the
terminator is in high impedance mode.
I2C bus data. Serial control for impedance and bias current adjustments.
ICAD0–6
I
I2C bus clock.
I2C address.
Line n–
O
Negative line for differential applications of the SCSI bus.
Line n+
O
Positive line for differential applications of the SCSI bus.
O
A low-voltage differential voltage level has been detected on the DIFF B pin. LVD pin high indicates that the terminator is in LVD mode.
LVD
13
PVDD
8
I
Power supply for the regulator. PVDD should be tied to TERMPWR pin.
REG
10
O
Regulator bypass pin must be bypassed to ground with a 4.7-µF low ESR capacitor.
SE
12
O
A single ended voltage level has been detected on the DIFF B pin. SE pin high indicates that the terminator is in
high impedance mode.
TERMPWR
7
I
VIN 2.7-V to 5.25-V supply. TERMPWR should be bypassed to ground with a 4.7-µF low ESR capacitor.
www.ti.com
5
SLVS406B – JUNE 2002 – REVISED JUNE 2003
block diagram
–15 mA ≤ ISOURCE ≤ –5 mA
50 µA ≤ ISINK ≤ 200 µA
OPEN CIRCUIT ON POWER OFF OR OPEN
CIRCUIT IN A DISABLED TERMINATOR MODE
TERMPWR
7
2.7 V to 5.25 V
REF 1.3 V
DIFSENS
14
HIPD
13
LVD
12
SE
HIGH POWER DIFFERENTIAL
1.3 V +/– 0.1 V
PVDD
15
8
2.4 V to 1.9 V
LOW VOLTAGE DIFFERENTIAL
DIFFB
DIGITAL
FILTER
100 ms to 310 ms
16
SINGLE ENDED
0.7 V to 0.5 V
TERMPWR
HIGH IMPEDANCE RECEIVER EVEN WITH POWER OFF
1.05 mA*
SOURCE/SINK REGULATOR
52.5 Ω *
124 Ω
80
REF 1.25 V
L27–
52.5 Ω *
79
ICAD0
L27+
49
ICAD6
43
ICBD
50
ICBC
51
I 2C MESSAGE
CONTROLS
DIFFERENTIAL
BIAS CURRENT
AND
DIFFERENTIAL
IMPEDANCE
SWITCHES UP ARE HIGH IMPEDANCE
SWITCHES DOWN ARE LOW
VOLTAGE DIFFERENTIAL
1.05 mA*
TERMPWR
1.05 mA*
124 Ω
52.5 Ω *
2
L1–
52.5 Ω *
TERMPWR
1
L1+
10 µ A
1.05 mA*
DISCNT
52
ENABLE
SWITCH
54
10
GND
REG
4.7 µ F
6
www.ti.com
* DEFAULT CAN BE ADJUSTED BY I2C MESSAGES
UDG–01094
SLVS406B – JUNE 2002 – REVISED JUNE 2003
APPLICATION INFORMATION
The DIFF SENSE line is driven by the terminator and monitored by the terminator DIFF B input pin. DIFF B has
a digital filter and a 100-ms to 310-ms delay before the mode of the terminator is changed to reflect the new
DIFF B input level. A set of comparators that allow for ground shifts determines the bus status as follows: any
DIFF SENSE signal below 0.5 V is single ended, between 0.7 V and 1.9 V is LVD SCSI, and above 2.4 V is HVD
SCSI.
The UCC5696 is high-impedance in SE and HVD SCSI bus modes.
Layout is very critical for Ultra320 and Ultra640 systems. Multilayer boards need to adhere to the impedance
120-Ω standard, including connectors and feed-throughs. This is normally done on the outer layers with 4-mil
etch and 4-mil spacing between the runs within a pair, and a minimum of 8-mil spacing to the next pair. The
spacing between the pairs reduces potential cross-talk. Beware of feed-throughs and through-hole connectors,
each of which adds a lot of capacitance. The standard power and ground plane spacing yields about 1 pF to
each plane; each feed-through adds about 2.5 pF to 3.5 pF. Enlarging the clearance holes on both power and
ground planes can reduce the capacitance, and opening up the power and ground planes under the connector
can reduce the capacitance for through hole connector applications. Microstrip technology is normally too low
of impedance and should not be used. It is designed for 50-Ω not 120-Ω differential systems.
Capacitance balance is critical for Ultra640; the balance capacitance is 0.5 pF per line while the balance
between pairs is 2 pF. The components are designed with very tight balance, typically 0.1 pF between pins in
a pair and 0.3 pF between pairs. Layout balance is critical, feed-throughs and etch length must be balanced,
and preferably no feed-throughs would be used. Capacitance for devices should be measured in the typical
application. Materials and components above and below the circuit board effect the capacitance.
The differential impedance is adjustable to match the impedance of the backplane or cable system, adjusting
for the loading change when drives are added. The high frequency roll off of the system can reduce the size
of the single bit transition to less than the size of the reflected wave on a heavily loaded system. Adjusting the
terminator to match the impedance of the system, which changes as drives are added, minimizes the reflection
from the terminator. Ultra640 SCSI must have each segment of the bus adjusted to reduce errors, SCSI domain
validation (SDV) defines the margining of the segments.
System testing has shown that reducing the terminator impedances to slightly lower than the bus impedance
reduces isolated 0 and 1 bit errors and increases system performace for Ultra160, Ultra320 and Ultrra640
speeds.
In 3.3-V Termpwr systems, the UCC3912 or UCC3918 should be used to replace the diode and fuse function.
This reduces the voltage drop, allowing for the cable voltage drop for the terminators on the far end of the cable.
3.3-V battery systems have a 10% tolerance, the UCC3912 or UCC3918 has less than 150-mV drop under load,
allowing for 150 mV-drop in the cable system. All Texas Instrument LVD and multimode terminators are
designed for 3.3-V systems, operating down to 2.7 V.
In 5-V Termpwr systems the UCC3916, UCC3912 or UCC3918 can be used to replace the diode and fuse
function. These reduce the voltage drop and protect the systems better than the diode and fuse or polyfuse.
www.ti.com
7
SLVS406B – JUNE 2002 – REVISED JUNE 2003
APPLICATION INFORMATION
I2C interface
The two-wire serial interface is used to access the terminator and to independently adjust both the differential
impedance and the differential bias current. This interface consists of one clock line, (SCL), and one serial data
line, (SDA).
The access cycle consists of the following and is shown in Figure 2:
1. A start condition
2. A slave address cycle
3. A data cycle
4. A stop condition
SCL
SDA
Start Condition (S)
Stop Condition (P)
Figure 1. I2C Start and Stop Condition
The start and stop conditions are shown in Figure 1. The high-to-low transition of SDA while SCL is high defines
the start condition. The low-to-high transition of SDA while SCL is high, defines the stop condition. The start and
stop conditions are initiated by the master device.
Each cycle, data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the
receiving device. During the acknowledge clock pulse (the ninth clock) the transmitting device must release the
SDA line. The receiving device then pulls down the SDA line so that it remains stable LOW during the HIGH
period of the acknowledge clock pulse.
slave address
The slave address of the UCC5696 terminator has 8 bits consisting of 7 bits of address along with 1 bit, the LSB,
reserved for the read/write information (1 for read and 0 for write). The 7-bit address is fully programmable.
8
www.ti.com
SLVS406B – JUNE 2002 – REVISED JUNE 2003
APPLICATION INFORMATION
write/read
The UCC5696 operates using only a single byte transfer (a byte of address followed by a second byte for data).
Following a start condition and an address byte, the UCC5696 responds with an acknowledge by pulling the
SDA line low during the ninth clock cycle, if it is the terminator’s address.
In a write cycle, after receiving a data byte, the UCC5696 pulls the SDA low for one clock cycle. A stop condition
is initiated by the transmitting device after the acknowledge clock pulse. See Figure 2 for an example of a write
cycle.
Not
Acknowledge
from Master
Acknowledge
from Receiver
Start Condition
SDA
A6
A5
A4
A3
A2
A1
A0 R/W ACK D7
D6
D5
Device Address and Read/Write
D4
D3
D2
D1
D0
ACK
Stop
Condition
Data Byte
Figure 2. Write Cycle
In a read cycle, following the initial acknowledge for address, the UCC5696 becomes a transmitting device and
the master device becomes the receiver. At the end of the data byte, the not acknowledge, A, condition is
initiated by the master by keeping the SDA signal high before it asserts the stop condition. See Figure 3 for an
example of a read cycle.
Not
Acknowledge
from Master
Acknowledge
from Receiver
Start Condition
SDA
A6
A5
A4
A3
A2
A1
A0 R/W ACK D7
D6
Device Address and Read/Write
D5
D4
D3
Data Byte
D2
D1
D0 ACK
Stop
Condition
Figure 3. Read Cycle
data
Bit 7 (MSB) to bit 4 of the data byte are used to control the differential bias current. Bit 3 to bit 0 are used to control
the differential impedance. At powerup both differential bias current and differential impedance are set to
1.05 mA and 105 Ω, respectively. Reference Table 1 and 2 for other current and impedance settings. All these
values are nominal.
www.ti.com
9
SLVS406B – JUNE 2002 – REVISED JUNE 2003
APPLICATION INFORMATION
Table 1. Differential Bias Current Settings True
DIFFERENTIAL IBIAS (mA)
BIT7
(MSB)
BIT6
BIT5
BIT4
0.70
0
0
0
0
0.75
0
0
0
1
0.80
0
0
1
0
0.85
0
0
1
1
0.90
0
1
0
0
0.95
0
1
0
1
1.00
0
1
1
0
1.05 (See Note)
0
1
1
1
1.10
1
0
0
0
1.15
1
0
0
1
1.20
1
0
1
0
1.25
1
0
1
1
1.30
1
1
0
0
1.35
1
1
0
1
1.40
1
1
1
1
0
1
1
1
1.45
NOTE: Default settings
Table 2. Differential Impedance Settings True
DIFFERENTIAL IMPEDANCE (Ω)
BIT3
BIT2
BIT1
BIT0
55
0
0
0
0
60
0
0
0
1
65
0
0
1
0
70
0
0
1
1
75
0
1
0
0
80
0
1
0
1
85
0
1
1
0
90
0
1
1
1
95
1
0
0
0
100
1
0
0
1
105 (See Note)
1
0
1
0
110
1
0
1
1
115
1
1
0
0
120
1
1
0
1
125
1
1
1
0
130
1
1
1
1
NOTE: Default settings
10
www.ti.com
SLVS406B – JUNE 2002 – REVISED JUNE 2003
APPLICATION INFORMATION
Table 3. Characteristics of the SDA and SCL I/O Stages for Standard/Fast-Mode
STANDARD MODE
PARAMETER
SYMBOL
Termpwr voltage
MIN
VDD
VIL
Low-level input voltage
High-level input voltage
Hyst of schmitt-trigger input
Low-level input at 3-mA sink
Pulse width of spikes which must be
suppressed by input filter
FAST MODE
MAX
MIN
MAX
UNIT
2.7
5.25
2.7
5.25
V
–0.5
0.3 x VDD
–0.5
0.3 x VDD
V
VIH
VHYS
VOL
0.7 x VDD
tSP
0.7 x VDD
V
N/A
N/A
0.15
0
0.4
0
0.4
V
V
N/A
N/A
0
50
ns
Table 4. Timing Characteristics for I2C Interface
STANDARD MODE
PARAMETER
SYMBOL
Clock frequency, SCL
fSCL
tW(H)
tW(L)
Pulse duration, SCL high
Pulse duration, SCL low
Rise time, SCL to SDA
tr
tf
Fall time, SCL to SDA
setup time, SDA to SCL
MIN
MAX
0
4
FAST MODE
UNIT
MIN
MAX
100
0
400
kHz
–
0.6
–
µs
4.7
–
1.3
–
µs
–
1000
–
300
ns
–
300
–
300
ns
tSU1
th1
250
–
100
–
ns
Hold time, SCL to SDA
0.30
3.45
0.30
0.90
µs
Bus free time between stop and start
condition
tbuf
4.7
–
1.3
–
µs
4.7
–
0.6
–
µs
Hold time, start condition to SCL
tSU2
th2
4
–
0.6
–
µs
Setup time, SCL to stop condition
tSU2
4
–
0.6
–
µs
Setup time, SCL to start condition
tf
tr
t W(L)
SCL
t h2
t su2
t W(H)
t su1
t buf
t h1
t su3
SDA
Figure 4. SCL and SDA
www.ti.com
11
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products & application
solutions:
Products
Amplifiers
Applications
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2003, Texas Instruments Incorporated