LT1970A 500mA Power Op Amp with Adjustable Precision Current Limit FEATURES DESCRIPTION n The LT®1970A is a ± 500mA power op amp with precise externally controlled current limiting. Separate control voltages program the sourcing and sinking current limit sense thresholds with 1% accuracy. Output current may be boosted by adding external power transistors. n n n n n n n n n n n ± 500mA Minimum Output Current Independent Adjustment of Source and Sink Current Limits 1% Current Limit Accuracy Improved Reactive Load Driving Stability Operates with Single or Split Supplies Shutdown/Enable Control Input Open-Collector Status Flags: Sink Current Limit Source Current Limit Thermal Shutdown Fail-Safe Current Limit and Thermal Shutdown 1.6V/μs Slew Rate 3.6MHz Gain-Bandwidth Product Specified Temperature Range: –40°C to 85°C Available in a 20-Lead TSSOP Package The circuit operates with single or split power supplies from 5V to 36V total supply voltage. In normal operation, the input stage supplies and the output stage supplies are connected (VCC to V+ and VEE to V–). To reduce power dissipation it is possible to power the output stage (V+, V–) from independent, lower voltage rails. The amplifier is unity-gain stable with a 3.6MHz gain-bandwidth product and slews at 1.6V/μs. The LT1970A can drive capacitive and inductive loads directly. Open-collector status flags signal current limit circuit activation, as well as thermal shutdown of the amplifier. An enable logic input puts the amplifier into a low power, high impedance output state when pulled low. Thermal shutdown and a ±800mA fixed current limit protect the chip under fault conditions. APPLICATIONS n n n n Automatic Test Equipment Laboratory Power Supplies Motor Drivers Thermoelectric Cooler Driver The LT1970A is packaged in a 20-lead TSSOP package with a thermally conductive copper bottom plate to facilitate heat sinking. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Device Power Supply (DPS) with ±500mA Adjustable Current Limit VLIMIT 0V TO 5V 20V VCC VIN +IN 20V CURRENT LIMIT = 500mA 6k V + IOUT(MAX) = ± EN VCSRC VCSNK ISNK IOUT ISRC TSD LT1970A OUT SENSE+ SENSE– V– –IN VEE COMMON RCS 1Ω 1/4W VLIMIT t3CS VLOAD, RLOAD = 100Ω TRACE R TRACE L 100mΩ 200nH 2V/DIV 4.7μF SENSE VIN, 5V/DIV LOAD ESR 0.1Ω VLOAD, RLOAD = 10Ω 0V 1970A TA01 –5V 10k 100μs/DIV 1970A TA01b 100pF 1970afa 1 LT1970A ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW Supply Voltage (VCC to VEE) ..................................... 36V Positive High Current Supply (V+)................... V – to VCC Negative High Current Supply(V –) ....................VEE to V+ Amplifier Output (OUT) ..................................... V – to V+ Current Sense Pins (SENSE+, SENSE–, FILTER) ........................... V – to V+ Logic Outputs (ISRC, ISNK, TSD) ....... COMMON to VCC Input Voltage (–IN, +IN) ............ VEE – 0.3V to VEE + 36V Input Current......................................................... 10mA Current Control Inputs (VCSRC, VCSNK) .............. COMMON to COMMON + 7V Enable Logic Input .............................. COMMON to VCC COMMON ....................................................... VEE to VCC Output Short-Circuit Duration ......................... Indefinite Operating Temperature Range (Note 2).... –40°C to 85°C Specified Temperature Range (Note 3) LT1970AC ................................................ 0°C to 70°C LT1970AI.............................................. –40°C to 85°C Maximum Junction Temperature.......................... 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) .................. 300°C VEE 1 V– 2 OUT 3 18 TSD SENSE+ 4 17 ISNK FILTER 5 SENSE– 6 VCC 7 14 COMMON –IN 8 13 VCSRC +IN 9 12 VCSNK 20 VEE 21 – + VEE 10 19 V+ 16 ISRC 15 ENABLE 11 VEE FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 40°C/W (NOTE 8) EXPOSED PAD (PIN 21) IS CONNECTED TO VEE ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LT1970ACFE#PBF LT1970ACFE#TRPBF LT1970AFE 20-Lead Plastic TSSOP 0°C to 70°C LT1970AIFE#PBF LT1970AIFE#TRPBF LT1970AFE 20-Lead Plastic TSSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. See Test Circuit for standard test conditions. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 200 600 1000 1300 10 μV μV μV μV/°C 100 nA Power Op Amp Characteristics VOS Input Offset Voltage 0°C < TA < 70°C –40°C < TA < 85°C Input Offset Voltage Drift (Note 4) l l l –10 IOS Input Offset Current VCM = 0V l –100 IB Input Bias Current VCM = 0V l –600 Input Noise Voltage 0.1Hz to 10Hz –4 –160 3 nA μVP-P 1970afa 2 LT1970A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. See Test Circuit for standard test conditions. SYMBOL PARAMETER CONDITIONS en Input Noise Voltage Density 1kHz 15 nV/√Hz in Input Noise Current Density 1kHz 3 pA/√Hz RIN Input Resistance CIN Input Capacitance Common Mode Differential Mode Pin 8 and Pin 9 to Ground VCM Input Voltage Range CMRR Common Mode Rejection Ratio l PSRR Power Supply Rejection Ratio AVOL Large-Signal Voltage Gain RL = 1k, –12.5V < VOUT < 12.5V RL = 100Ω, –12.5V < VOUT < 12.5V RL = 10Ω, –5V < VOUT < 5V, V+ = – V – = 8V ISC Output Short-Circuit Current SR Slew Rate VOL = VOUT – V – RL = 100, VCC = V+ = 15V, VEE = V – = –15V RL = 10, VCC = – VEE = 15V, V+ = –V – = 5V VOH = V+ – VOUT RL = 100, VCC = V+ = 15V, VEE = V – = –15V RL = 10, VCC = – VEE = 15V, V+ = –V – = 5V Output Low, RSENSE = 0Ω Output High, RSENSE = 0Ω –10V < VOUT < 10V, RL = 1k FPBW Full Power Bandwidth VOUT = 10VPEAK (Note 5) GBW Gain-Bandwidth Product f = 10kHz tS Settling Time 0.01%, VOUT = 0V to 10V, AV = –1, RL = 1k VOH Output Sat Voltage Low Output Sat Voltage High TYP MAX 500 100 6 Typical Guaranteed by CMRR Test –12V < VCM < 12V VEE = V – = –5V, VCC = V+ = 3V to 30V VEE = V – = –5V, VCC = 30V, V+ = 2.5V to 30V VEE = V – = –3V to – 30V, VCC = V+ = 5V VEE = –30V, V – = –2.5V to –30V, VCC = V+ = 5V VOL MIN UNITS kΩ kΩ pF l –14.5 –12.0 92 105 V V dB l l l l 90 110 90 110 100 130 100 130 dB dB dB dB 100 75 80 40 20 5 150 V/mV V/mV V/mV V/mV V/mV V/mV l l l 13.6 12.0 120 45 l 1.9 0.8 2.5 V V l 1.7 1.0 800 –800 1.6 2.3 V V mA mA V/μs 500 –1000 0.7 1200 –500 11 kHz 3.6 MHz 8 μs Current Sense Characteristics VSENSE(MIN) Minimum Current Sense Voltage VCSRC = VCSNK = 0V VSENSE(4%) Current Sense Voltage 4% of Full Scale VCSRC = VCSNK = 0.2V VSENSE(10%) Current Sense Voltage 10% of Full Scale VCSRC = VCSNK = 0.5V VCSRC = VCSNK = 5V l 0.1 0.1 15 l l l 4 20 7 10 25 mV mV mV 45 50 55 mV 500 500 –0.2 505 520 0.1 mV mV μA VSENSE(FS) Current Sense Voltage 100% of Full Scale IBI Current Limit Control Input Bias Current VCSRC, VCSNK Pins l 495 480 –1 ISENSE– SENSE– Input Current 0V < (VCSRC, VCSNK) < 5V l –500 500 nA IFILTER FILTER Input Current 0V < (VCSRC, VCSNK) < 5V l –500 500 nA ISENSE+ SENSE+ Input Current l l l l –500 200 –300 –25 500 300 –200 25 ±0.1 nA μA μA μA % ±0.05 ±0.01 ±0.05 ±0.01 % % % % VCSRC= VCSNK = 0V VCSRC = 5V, VCSNK = 0V VCSRC= 0V, VCSNK = 5V VCSRC = VCSNK = 5V Current Sense Change with Output Voltage VCSRC = VCSNK = 5V, –12.5V < VOUT < 12.5V Current Sense Change with Supply Voltage VCSRC = VCSNK = 5V, 6V < (VCC, V+) < 18V 2.5V < V+ < 18V, VCC = 18V –18V < (VEE, V –) < –2.5V –18V < V – < –2.5V, VEE = –18V 250 –250 1970afa 3 LT1970A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. See Test Circuit for standard test conditions. SYMBOL PARAMETER CONDITIONS MIN TYP 750 1000 Current Sense Bandwidth RCSF MAX UNITS 2 Resistance FILTER to SENSE– l MHz 1250 Ω 1 μA 0.4 V Logic I/O Characteristics Logic Output Leakage ISRC, ISNK, TSD V = 15V l Logic Low Output Level I = 5mA (Note 6) l 0.2 Logic Output Current Limit VENABLE Enable Logic Threshold IENABLE Enable Pin Bias Current 25 l 0.8 l –1 mA 1.9 2.5 V 1 μA ICC(STBY) Supply Current Disabled VCC, V+ and V –, VEE Connected VCC, V+ and V –, VEE Separate VCC, V+ and V –, VEE Connected, VENABLE ≤ 0.8V tON Turn-On Delay (Note 7) 10 μs tOFF Turn-Off Delay (Note 7) 10 μs ISUPPLY Total Supply Current ICC VCC Supply Current Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT1970AC is guaranteed functional over the operating temperature range of – 40°C and 85°C. Note 3: The LT1970AC is guaranteed to meet specified performance from 0°C to 70°C. The LT1970AC is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1970AI is guaranteed to meet specified performance from –40°C to 85°C. l 7 13 mA l 3 7 mA l 0.6 1.5 mA Note 4: This parameter is not 100% tested. Note 5: Full power bandwidth is calculated from slew rate measurements: FPBW = SR/(2 • π • VP) Note 6: The logic low output level of pin TSD is guaranteed by correlating the output level of pin ISRC and pin ISNK over temperature. Note 7: Turn-on and turn-off delay are measured from VENABLE crossing 1.6V to the OUT pin at 90% of normal output voltage. Note 8: Thermal resistance varies depending upon the amount of PC board metal attached to the device. If the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected. TYPICAL PERFORMANCE CHARACTERISTICS Warm-Up Drift VIO vs Time Total Supply Current vs Supply Voltage Input Bias Current vs VCM –100 VS = ±15V TIME (100ms/DIV) 1970A G01 TOTAL SUPPLY CURRENT (mA) 0V INPUT BIAS CURRENT (nA) VOStN7%*7 –120 –140 –IBIAS –160 +IBIAS –180 –200 –220 –240 –260 –15 –12 –9 –6 –3 0 3 6 9 12 15 COMMON MODE INPUT VOLTAGE (V) 1970A G02 14 12 10 8 6 4 2 0 –2 –4 –6 –8 –10 –12 –14 ICC + IV+ 125°C 25°C –55°C IEE + IV– –55°C 25°C 125°C 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (±V) 16 18 1970A G03 1970afa 4 LT1970A TYPICAL PERFORMANCE CHARACTERISTICS Open-Loop Gain and Phase vs Frequency Supply Current vs Supply Voltage IV+ IV– IVCC 3.0 2.5 IVEE 2.0 1.5 1.0 TA = 25°C VCC = V+ = –VEE = –V– 0.5 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (±V) 18 60 60 90 58 80 56 50 OPEN-LOOP GAIN (dB) 3.5 100 20 GAIN 40 PHASE 20 50 10 40 0 30 –10 20 44 –20 10 42 1k 10k 100k 1M FREQUENCY (Hz) 4 8 12 16 20 24 28 32 TOTAL SUPPLY VOLTAGE (V) VS = ±15V –10 VS = ±5V –20 100k 1M FREQUENCY (Hz) AV = 10 AV = 1 0.01 0.001 1k 100k 1M FREQUENCY (Hz) 10M 100M 1970A G10 100k 1M FREQUENCY (Hz) 10M Slew Rate vs Supply Voltage 1.8 1.7 FALLING 1.6 10k 1k 100 RISING 1.5 1.4 1.3 1.2 10 10k 0nF –20 1970A G09 SLEW RATE (V/μs) OUTPUT IMPEDANCE (Ω) AV = 100 0.1 1nF –40 10k 10M VS = ±15V VENABLE = 0.8V 100k 1 10nF –10 Disabled Output Impedance 600k 10 30nF 1970A G08 Output Impedance VS = ±15V VS = ±15V AV = 1 –30 –40 10k 36 36 0 1970A G07 100 8 12 16 20 24 28 32 TOTAL SUPPLY VOLTAGE (V) Gain vs Frequency with CLOAD 10 –30 0 4 1970A G06 VOLTAGE GAIN (dB) VOLTAGE GAIN (dB) GAIN BANDWIDTH (MHz) 0 0 4 0 46 40 AV = 1 AV = 100 2 48 Gain vs Frequency 10 1 OUTPUT IMPEDANCE (Ω) 0 100M 10M 50 1970A G05 Gain Bandwidth vs Supply Voltage 3 52 60 –30 100 AV = –1 RF = RG = 1k TA = 25°C VOUT = VS/2 54 30 1870A G04 5 70 PHASE MARGIN (DEG) SUPPLY CURRENT (mA) 4.0 Phase Margin vs Supply Voltage 70 PHASE MARGIN (DEG) 4.5 1 1k AV = –1 RF = RG = 1k TA = 25°C 1.1 1.0 10k 100k 1M FREQUENCY (Hz) 10M 100M 1970A G11 4 6 14 8 12 10 SUPPLY VOLTAGE (±V) 16 18 1970A G12 1970afa 5 LT1970A TYPICAL PERFORMANCE CHARACTERISTICS Slew Rate vs Temperature 2.5 VS = ±15V Large-Signal Response, AV = 1 FALLING 2.0 10V 10V 1.5 5V/DIV RISING 5V/DIV SLEW RATE (V/μs) Large-Signal Response, AV = – 1 0V –10V 1.0 0V –10V 0.5 RL = 1k 0 –50 –25 50 0 75 25 TEMPERATURE (°C) 100 20μs/DIV RL = 1k CL = 1000pF 1970A G14 20μs/DIV 1970A G15 125 1970A G13 Small-Signal Response, AV = – 1 Output Overdriven VOUT 0V 5V/DIV 20mV/DIV 20mV/DIV Small-Signal Response, AV = 1 VIN 5V/DIV 0V RL = 1k 500ns/DIV RL = 1k CL = 1000pF 1970A G16 1970A G18 500 400 40 30 AV = –1 20 10 100 1k 10k CLOAD (pF) 1970A G19 SOURCING CURRENT 200 20 15 100 0 –100 10 5 0 300 VSENSE (mV) AV = 1 OUTPUT SWING (VP-P) 25 10 200μs/DIV Full Range Current Sense Transfer Curve 30 VS = ±15V 50 OVERSHOOT (%) VS = ±5V AV = 1 1970A G17 Undistorted Output Swing vs Frequency % Overshoot vs CLOAD 60 2μs/DIV SINKING CURRENT –200 –300 VS = ±15V AV = –5 1% THD 0 100 –400 1k 10k FREQUENCY (Hz) 100k 1970A G20 –500 0 1 3 2 VCSNK = VCSRC (V) 4 5 1970A G21 1970afa 6 LT1970A TYPICAL PERFORMANCE CHARACTERISTICS Low Level Current Sense Transfer Curve Logic Output Level vs Sink Current (Output Low) 1.0 + V = 15V 0.9 V– = –15V SOURCING CURRENT 5 0 –5 SINKING CURRENT –10 –15 1400 0.8 0.7 0.6 25°C 0.5 125°C 0.4 0.3 –55°C 0.2 25 50 75 100 125 150 175 200 225 250 VCSNK = VCSRC (mV) 0 0.001 0.01 0.1 1 10 SINK CURRENT (mA) 100 1200 SOURCE 1000 800 SINK 600 400 0 25 50 75 –75 –50 –25 0 TEMPERATURE (°C) 1970A G23 1970A G22 100 125 1970A G24 Output Stage Quiescent Current vs Supply Voltage Safe Operating Area 10 1200 IOUT AT 10% DUTY CYCLE 8 OUTPUT STAGE CURRENT (mA) 1000 IOUT PEAK (mA) 800 600 400 200 IV+ 6 125°C 25°C 4 –55°C 2 0 IV– –55°C –2 –4 25°C –6 125°C –8 –10 0 0 5 10 15 20 25 30 SUPPLY VOLTAGE (V) 35 0 40 2 4 6 8 10 12 14 SUPPLY VOLTAGE (±V) Control Stage Quiescent Current vs Supply Voltage 5 125°C 25°C –55°C 3 2 1 0 IEE –1 –55°C –2 25°C –3 125°C –4 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (±V) 16 18 1970A G27 VENABLE = 0V 85°C 700 25°C 600 –55°C 500 400 300 200 100 0 –5 18 Supply Current vs Supply Voltage in Shutdown 800 ICC 4 16 1970A G26 1970A G25 TOTAL SUPPLY CURRENT, ICC + IV+ (μA) 0 V+ = 15V V– = –15V 200 0.1 –20 SUPPLY CURRENT (mA) VSENSE (mV) LOGIC OUTPUT VOLTAGE (V) 15 10 1600 OUTPUT CURRENT (mA) 25 20 –25 Maximum Output Current vs Temperature 0 2 4 8 10 12 14 6 SUPPLY VOLTAGE (V) 16 18 1970A G28 1970afa 7 LT1970A PIN FUNCTIONS VEE (Pins 1, 10, 11, 20, 21): Minus Supply Voltage. VEE connects to the substrate of the integrated circuit die, and therefore must always be the most negative voltage applied to the part. Decouple VEE to ground with a low ESR capacitor. VEE may be a negative voltage or it may equal ground potential. Any or all of the VEE pins may be used. Unused VEE pins must remain open. V– (Pin 2): Output Stage Negative Supply. V – may equal VEE or may be smaller in magnitude. Only output stage current flows out of V –, all other current flows out of VEE. V – may be used to drive the base/gate of an external power device to boost the amplifier’s output current to levels above the rated 500mA of the on-chip output devices. Unless used to drive boost transistors, V– should be decoupled to ground with a low ESR capacitor. OUT (Pin 3): Amplifier Output. The OUT pin provides the force function as part of a Kelvin sensed load connection. OUT is normally connected directly to an external load current sense resistor and the SENSE+ pin. Amplifier feedback is directly connected to the load and the other end of the current sense resistor. The load connection is also wired directly to the SENSE– pin to monitor the load current. The OUT pin is current limited to ±800mA typical. This current limit protects the output transistor in the event that connections to the external sense resistor are opened or shorted which disables the precision current limit function. SENSE + (Pin 4): Positive Current Sense Pin. This lead is normally connected to the driven end of the external sense resistor. Sourcing current limit operation is activated when the voltage VSENSE (VSENSE+ – VSENSE –) equals 1/10 of the programming control voltage at VCSRC (Pin 13). Sinking current limit operation is activated when the voltage VSENSE equals –1/10 of the programming control voltage at VCSNK (Pin 12). FILTER (Pin 5): Current Sense Filter Pin. This pin is normally not used and should be left open or shorted to the SENSE– pin. The FILTER pin can be used to adapt the response time of the current sense amplifiers with a 1nF to 100nF capacitor connected to the SENSE – input. An internal 1k resistor sets the filter time constant. SENSE– (Pin 6): Negative Current Sense Pin. This pin is normally connected to the load end of the external sense resistor. Sourcing current limit operation is activated when the voltage VSENSE (VSENSE+ – VSENSE –) equals 1/10 of the programming control voltage at VCSRC (Pin 13). Sinking current limit operation is activated when the voltage VSENSE equals –1/10 of the programming control voltage at VCSNK (Pin 12). VCC (Pin 7): Positive Supply Voltage. All circuitry except the output transistors draw power from VCC. Total supply voltage from VCC to VEE must be between 3.5V and 36V. VCC must always be greater than or equal to V+. VCC should always be decoupled to ground with a low ESR capacitor. –IN (Pin 8): Inverting Input of Amplifier. –IN may be any voltage from VEE – 0.3V to VEE + 36V. –IN and +IN remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. Care must be taken to ensure that –IN or +IN can never go to a voltage below VEE – 0.3V even during transient conditions or damage to the circuit may result. A Schottky diode from VEE to –IN can provide clamping if other elements in the circuit can allow –IN to go below VEE. +IN (Pin 9): Noninverting Input of Amplifier. +IN may be any voltage from VEE – 0.3V to VEE + 36V. –IN and +IN remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. Care must be taken to ensure that –IN or +IN can never go to a voltage below VEE – 0.3V even during transient conditions or damage to the circuit may result. A Schottky diode from VEE to +IN can provide clamping if other elements in the circuit can allow + IN to go below VEE. 1970afa 8 LT1970A PIN FUNCTIONS VCSNK (Pin 12): Sink Current Limit Control Voltage Input. The current sink limit amplifier will activate when the sense voltage between SENSE+ and SENSE– equals –1.0 • VVCSNK/10. VCSNK may be set between VCOMMON and VCOMMON + 6V. The transfer function between VCSNK and VSENSE is linear except for very small input voltages at VCSNK < 60mV. VSENSE limits at a minimum set point of 4mV typical to ensure that the sink and source limit amplifiers do not try to operate simultaneously. To force zero output current, the ENABLE pin can be taken low. VCSRC (Pin 13): Source Current Limit Control Voltage Input. The current source limit amplifier will activate when the sense voltage between SENSE+ and SENSE– equals VVCSRC/10. VCSRC may be set between VCOMMON and VCOMMON + 6V. The transfer function between VCSRC and VSENSE is linear except for very small input voltages at VCSRC < 60mV. VSENSE limits at a minimum set point of 4mV typical to ensure that the sink and source limit amplifiers do not try to operate simultaneously. To force zero output current, the ENABLE pin can be taken low. COMMON (Pin 14): Control and ENABLE inputs and flag outputs are referenced to the COMMON pin. COMMON may be at any potential between VEE and VCC – 3V. In typical applications, COMMON is connected to ground. current. The current limit flag is off when the source current limit is not active. ISRC, ISNK and TSD may be wired “OR” together if desired. ISRC may be left open if this function is not monitored. ISNK (Pin 17): Sinking Current Limit Digital Output Flag. ISNK is an open-collector digital output. ISNK pulls low whenever the sinking current limit amplifier assumes control of the output. This pin can sink up to 10mA of current. The current limit flag is off when the source current limit is not active. ISRC, ISNK and TSD may be wired “OR” together if desired. ISNK may be left open if this function is not monitored. TSD (Pin 18): Thermal Shutdown Digital Output Flag. TSD is an open-collector digital output. TSD pulls low whenever the internal thermal shutdown circuit activates, typically at a die temperature of 160°C. This pin can sink up to 10mA of output current. The TSD flag is off when the die temperature is within normal operating temperatures. ISRC, ISNK and TSD may be wired “OR” together if desired. ISNK may be left open if this function is not monitored. Thermal shutdown activation should prompt the user to evaluate electrical loading or thermal environmental conditions. ENABLE (Pin 15): ENABLE Digital Input Control. When taken low this TTL-level digital input turns off the amplifier output and drops supply current to less than 1mA. Use the ENABLE pin to force zero output current. Setting VCSNK = VCSRC = 0V allows IOUT = ±4mV/RSENSE to flow in or out of VOUT. V+ (Pin 19): Output Stage Positive Supply. V + may equal VCC or may be smaller in magnitude. Only output stage current flows through V+, all other current flows into VCC. V+ may be used to drive the base/gate of an external power device to boost the amplifier’s output current to levels above the rated 500mA of the on-chip output devices. Unless used to drive boost transistors, V+ should be decoupled to ground with a low ESR capacitor. ISRC (Pin 16): Sourcing Current Limit Digital Output Flag. ISRC is an open-collector digital output. ISRC pulls low whenever the sourcing current limit amplifier assumes control of the output. This pin can sink up to 10mA of Exposed Pad (Pin 21): The exposed backside of the package is electrically connected to the VEE pins on the IC die. The package base should be soldered to a heat spreading pad on the PC board that is electrically connected to VEE. 1970afa 9 LT1970A BLOCK DIAGRAM AND TEST CIRCUIT RF 1k VCC 7 V+ 19 9 + – + VIN –IN 15V Q1 OUT 1= GM1 8 RG 1k +IN – 3 Q2 ISNK 10k 17 15V 18 15 5V 12 D1 ISNK TSD ENABLE VCSNK ENABLE VCSNK D2 13 VCSRC + – + – – 10k ISRC + 16 – 10k VCSRC VSNK SENSE+ FILTER VSRC SENSE– RFIL 1k ISRC 5 6 RLOAD 1k 2 VEE COMMON 4 V– + 14 RCS 1Ω 1, 10, 11, 20 –15V 1970ATC APPLICATIONS INFORMATION The LT1970A power op amp with precision controllable current limit is a flexible voltage and current source module. The drawing on the front page of this data sheet is representative of the basic application of the circuit, however many alternate uses are possible with proper understanding of the subcircuit capabilities. CIRCUIT DESCRIPTION Main Operational Amplifier Subcircuit block GM1, the 1X unity-gain current buffer and output transistors Q1 and Q2 form a standard operational amplifier. This amplifier has ± 500mA current output capability and a 3.6MHz gain-bandwidth product. Most applications of the LT1970A will use this op amp in the main signal path. All conventional op amp circuit configurations are supported. Inverting, noninverting, filter, summation or nonlinear circuits may be implemented in a conventional manner. The output stage includes current limiting at ±800mA to protect against fault conditions. The input stage has high differential breakdown of 36V minimum between –IN and +IN. No current will flow at the inputs when differential input voltage is present. This feature is important when the precision current sense amplifiers “ISINK” and “ISRC” become active. Current Limit Amplifiers Amplifier stages “ISINK” and “ISRC” are very high transconductance amplifier stages with independently controlled offset voltages. These amplifiers monitor the voltage between input pins SENSE+ and SENSE– which usually sense the voltage across a small external current sense resistor. The transconductance amplifiers outputs connect to the same high impedance node as the main input stage GM1 amplifier. Small voltage differences between SENSE+ and SENSE–, smaller than the user set VCSNK/10 1970afa 10 LT1970A APPLICATIONS INFORMATION and VCSRC /10 in magnitude, cause the current limit amplifiers to decouple from the signal path. This is functionally indicated by diodes D1 and D2 in the Block Diagram. When the voltage VSENSE increases in magnitude sufficient to equal or overcome one of the offset voltages VCSNK/10 or VCSRC /10, the appropriate current limit amplifier becomes active and because of its very high transconductance, takes control from the input stage, GM1. The output current is regulated to a value of IOUT = VSENSE /RSENSE = (VCSRC or VCSNK)/(10 • RSENSE). The time required for the current limit amplifiers to take control of the output is typically 4μs. Linear operation of the current limit sense amplifier occurs with the inputs SENSE+ and SENSE– ranging between VCC – 1.5V and VEE + 1.5V. Most applications will connect pins SENSE+ and OUT together, with the load on the opposite side of the external sense resistor and pin SENSE–. Feedback to the inverting input of GM1 should be connected from SENSE– to – IN. Ground side sensing of load current may be employed by connecting the load between pins OUT and SENSE+. Pin SENSE– would be connected to ground in this instance. Load current would be regulated in exactly the same way as the conventional connection. However, voltage mode accuracy would be degraded in this case due to the voltage across RSENSE. Creative applications are possible where pins SENSE+ and SENSE– monitor a parameter other than load current. The operating principle that at most one of the current limit stages may be active at one time, and that when active, the current limit stages take control of the output from GM1, can be used for many different signals. Current Limit Threshold Control Buffers Input pins VCSNK and VCSRC are used to set the response thresholds of current limit amplifiers “ISINK” and “ISRC”. Each of these inputs may be independently driven by a voltage of 0V to 5V above the COMMON reference pin. The 0V to 5V input voltage is attenuated by a factor of 10 and applied as an offset to the appropriate current limit amplifier. AC signals may be applied to these pins. The AC bandwidth from a VC pin to the output is typically 2MHz. For proper operation of the LT1970A, these control inputs cannot be left floating. For low VCC supply applications it is important to keep the maximum input control voltages, VCSRC and VCSNK, at least 2.5V below the VCC potential. This ensures linear control of the current limit threshold. Reducing the current limit sense resistor value allows high output current from a smaller control voltage which may be necessary if the VCC supply is only 5V. The transfer function from VC to the associated VOS is linear from about 0.1V to 5V in, or 10mV to 500mV at the current limit amplifier inputs. An intentional nonlinearity is built into the transfer functions at low levels. This nonlinearity ensures that both the sink and source limit amplifiers cannot become active simultaneously. Simultaneous activation of the limit amplifiers could result in uncontrolled outputs. As shown in the Typical Performance Characteristics curves, the control inputs have a “hockey stick” shape, to keep the minimum limit threshold at 4mV for each limit amplifier. Figure 1 illustrates an interesting use of the current sense input pins. Here the current limit control amplifiers are used to produce a symmetrically limited output voltage swing. Instead of monitoring the output current, the output voltage is divided down by a factor of 20 and applied to the SENSE+ input, with the SENSE– input grounded. When the threshold voltage between SENSE+ and SENSE– (VCLAMP/10) is reached, the current limit stage takes control of the output and clamps it a level of ±2 • VCLAMP. With control inputs VCSRC and VCSNK tied together, a single polarity input voltage sets the same + and – output limit voltage for symmetrical limiting. In this circuit the output will current limit at the built-in fail-safe level of typically 800mA. ENABLE Control The ENABLE input pin puts the LT1970A into a low supply current, high impedance output state. The ENABLE pin responds to TTL threshold levels with respect to the COMMON pin. Pulling the ENABLE pin low is the best way to force zero current at the output. Setting VCSNK = VCSRC = 0V allows the output current to remain as high as ± 4mV/RSENSE. 1970afa 11 LT1970A APPLICATIONS INFORMATION 12V VCLAMP OV TO 5V R3 3k VCSRC VCSNK VIN +IN –IN EN VCC 0V AT 2w VCLAMP V+ ISRC ISNK TSD OUT LT1970A SENSE+ SENSE– FILTER V– VEE –12V 1V/DIV –80mV TO ±CLAMP –10V REACHED OUTPUT CLAMPS COMMON RG VOUT 80mV TO 10V EN 10V/DIV 5V 0V 0V ENABLE VIN = 0.5V VIN = –0.5V 5μs/DIV DISABLE 5V 12V R1 21.5k RL R2 1.13k VCSRC VCSNK VIN +IN RF 1970A F01 –IN Figure 1. Symmetrical Output Voltage Limiting In applications such as circuit testers (ATE), it may be preferable to apply a predetermined test voltage with a preset current limit to a test node simultaneously. The ENABLE pin can be used to provide this gating action as shown in Figure 2. While the LT1970A is disabled, the load is essentially floating and the input voltage and current limit control voltages can be set to produce the load test levels. Enabling the LT1970A then drives the load. The LT1970A enables and disables in just a few microseconds. The actual enable and disable times at the load are a function of the load reactance. Operating Status Flags The LT1970A has three digital output indicators; TSD, ISRC and ISNK. These outputs are open-collector drivers referred to the COMMON pin. The outputs have 36V capabilities and can sink in excess of 10mA. ISRC and ISNK indicate activation of the associated current limit amplifier. The TSD output indicates excessive die temperature has caused the circuit to enter thermal shutdown. The three digital outputs may be wire “OR’d” together, monitored individually or left open. These outputs do not affect circuit operation, but provide an indication of the present operational status of the chip. EN VCC V+ ISRC ISNK TSD OUT LT1970A SENSE+ SENSE– FILTER V– VEE RS 1Ω RL 10Ω COMMON RG 10k –12V RF 10k 1970A F02 Figure 2. Using the ENABLE pin For slow varying output signals, the assertion of a low level at the current limit output flags occurs when the current limit threshold is reached. For fast moving signals where the LT1970A output is moving at the slew limit, typically 1.6V/μs, the flag assertion can be somewhat premature at typically 75% of the actual current limit value. The operating status flags are designed to drive LEDs to provide a visual indication of current limit and thermal conditions. As such, the transition edges to and from the active low state are not particularly sharp and may exhibit some uncertainty. Adding some positive feedback to the current limit control inputs helps to sharpen these transitions. With the values shown in Figure 3, the current limit threshold is reduced by approximately 0.5% when either current limit status flag goes low. With sharp logic transitions, the status outputs can be used in a system control loop to take protective measures when a current limit condition is detected automatically. 1970afa 12 LT1970A APPLICATIONS INFORMATION CURRENT LIMIT CONTROL VOLTAGE (0.1V TO 5V) R1 100Ω R3 20k R2 100Ω R4 20k 12V +IN –IN EN VCC WHEN CURRENT LIMIT IS FLAGGED, ILIMIT TRESHOLD IS REDUCED BY 0.5% V+ ISRC ISNK TSD OUT LT1970A SENSE+ – SENSE FILTER V– VEE IMAX 50mA 0 IOUT ISINK FLAG VCSRC VCSNK VIN 500mA ISOURCE FLAG ILOW –500mA RS 1Ω IMAX ≈ VCCt3 33 tt3S ILOW ≈ VCCt3]]3 <33]]3 >tt3S 12V RL R2 39.2k R1 54.9k R3 2.55k COMMON RG –12V VCSRC VCSNK RF 1970A F03 VIN +IN Figure 3. Adding Positive Feedback to Sharpen the Transition Edges of the Current Limit Status Flags –IN The current limit status flag can also be used to produce a dramatic change in the current limit value of the amplifier. Figure 4 illustrates a “snap-back” current limiting characteristic. In this circuit, a simple resistor network initially sets a high value of current limit (500mA). The circuit operates normally until the signal is large enough to enter current limit. When either current limit flag goes low, the current limit control voltage is reduced by a factor of 10. This then forces a low level of output current (50mA) until the signal is reduced in magnitude. When the load current drops below the lower level, the current limit is then restored to the higher value. This action is similar to a self resettable fuse that trips at dangerously high current levels and resets only when conditions are safe to do so. THERMAL MANAGEMENT Minimizing Power Dissipation The LT1970A can operate with up to 36V total supply voltage with output currents up to ± 500mA. The amount of power dissipated in the chip could approach 18W under worst-case conditions. This amount of power will cause die temperature to rise until the circuit enters thermal EN VCC V+ ISRC ISNK TSD OUT LT1970A SENSE+ – SENSE FILTER V– VEE RS 1Ω RL COMMON RG 10k –12V RF 10k 1970A F04 Figure 4. “Snap-Back” Current Limiting shutdown. While the thermal shutdown feature prevents damage to the circuit, normal operation is impaired. Thermal design of the LT1970A operating environment is essential to getting maximum utility from the circuit. The first concern for thermal management is minimizing the heat which must be dissipated. The separate power pins V+ and V– can be a great aid in minimizing on-chip power. The output pin can swing to within 1.0V of V+ or V– even under maximum output current conditions. Using separate power supplies, or voltage regulators, to set V+ and V– to their minimum values for the required output swing will minimize power dissipation. The supplies VCC and VEE may also be reduced to a minimal value, but these supply pins do not carry high currents, and the power saving is much less. VCC and VEE must be greater than the maximum output swing by 1.5V or more. 1970afa 13 LT1970A APPLICATIONS INFORMATION When V – and V+ are provided separately from VCC and VEE, care must be taken to ensure that V– and V+ are always less than or equal to the main supplies in magnitude. Protection Schottky diodes may be required to ensure this in all cases, including power on/off transients. Operation with reduced V+ and V– supplies does not affect any performance parameters except maximum output swing. All DC accuracy and AC performance specifications guaranteed with VCC = V+ and VEE = V– are still valid with the reduced output signal swing range. Heat Sinking The power dissipated in the LT1970A die must have a path to the environment. With 100°C/W thermal resistance in free air with no heat sink, the package power dissipation is limited to only 1W. The 20-pin TSSOP package with exposed copper underside is an efficient heat conductor if it is effectively mounted on a PC board. Thermal resistances as low as 40°C/W can be obtained by soldering the bottom of the package to a large copper pattern on the PC board. For operation at 85°C, this allows up to 1.625W of power to be dissipated on the LT1970A. At 25°C operation, up to 3.125W of power dissipation can be achieved. The PC board heat spreading copper area must be connected to VEE. Figure 5 shows examples of PCB metal being used for heat spreading. These are provided as a reference for what might be expected when using different combinations of metal area on different layers of a PCB. These examples are with a 4-layer board using 1oz copper on each layer. The most effective layers for spreading heat are those closest to the LT1970A junction. Soldering the exposed thermal pad of the TSSOP package to the board produces a thermal resistance from junction-to-case of approximately 3°C/W. As a minimum, the area directly beneath the package on all PCB layers can be used for heat spreading. However, limiting the area to that of the metal heat sinking pad is not very effective. Expanding the area on various layers significantly reduces the overall thermal resistance. The addition of vias (small 13 mil holes which fill during PCB plating) connecting all layers of metal also helps reduce the operating temperature of the LT1970A. These are also shown in Figure 5. It is important to note that the metal planes used for heat sinking are connecting electrically to VEE. These planes must be isolated from any other power planes used in the PCB design. Another effective way to control the power amplifier operating temperature is to use airflow over the board. Airflow can significantly reduce the total thermal resistance as also shown in Figure 5. DRIVING REACTIVE LOADS Capacitive Loads The LT1970A is much more tolerant of capacitive loading than most operational amplifiers. In a worst-case configuration as a voltage follower, the circuit is stable for capacitive loads less than 2.5nF. Higher gain configurations improve the CLOAD handling. If very large capacitive loads are to be driven, a resistive decoupling of the amplifier from the capacitive load is effective in maintaining stability and reducing peaking. The current sense resistor, usually connected between the output pin and the load can serve as a part of the decoupling resistance. Inductive Loads Load inductance is usually not a problem at the outputs of operational amplifiers, but the LT1970A can be used as a high output impedance current source. This condition may be the main operating mode, or when the circuit enters a protective current limit mode. Just as load capacitance degrades the phase margin of normal op amps, load inductance causes a peaking in the loop response of the feedback controlled current source. The inductive load may be caused by long lead lengths at the amplifier output. If the amplifier will be driving inductive loads or long lead lengths (greater than 4 inches) a 500pF capacitor from the SENSE– pin to the ground plane will cancel the inductive load and ensure stability. 1970afa 14 LT1970A APPLICATIONS INFORMATION STILL AIR VJA PACKAGE TOP LAYER 2ND LAYER 3RD LAYER BOTTOM LAYER TSSOP 100°C/W TSSOP 50°C/W TSSOP 45°C/W 1970A F05a Typical Reduction in VJA with Laminar Airflow Over the Device 0 % REDUCTION RELATIVE TO VJA IN STILL AIR REDUCTION IN VJA (%) –10 –20 –30 –40 –50 –60 0 100 200 300 400 500 600 700 800 900 1000 AIRFLOW (LINEAR FEET PER MINUTE, lfpm) 1970A F05b Figure 5. Examples of PCB Metal Used for Heat Dissipation. Driver Package Mounted on Top Layer. Heat Sink Pad Soldered to Top Layer Metal. Metal Areas Drawn to Scale of Package Size 1970afa 15 LT1970A APPLICATIONS INFORMATION 5V VIN 12V 0V 5V VCSRC VCSNK SOURCING +IN EN VCC SINKING 12V R1 95.3K 2.5V LT1634-2.5 –IN D1 1N4001 V+ ISRC ISNK RS ±500mA 1Ω TSD OUT LT1970A SENSE+ SENSE– FILTER V– VEE MAGNETIC TRANSDUCER D2 1N4001 COMMON 1970A F06 C1 500pF –12V Figure 6. Current Modulation of a Magnetic Transducer OPTIONAL TEST PIN ON/OFF CONTROL APPLY LOAD DRIVE 5V Hi-Z 0V 5V VOUT = 15V VCC CLR VREF ( ) CODE C – CODE D ≈ ±15V 1024 ISOURCE(MAX) = t$0%&# ≈ –4mA TO –500mA t3S DAC A ISINK(MAX) = t$0%&" ≈ 4mA TO 500mA t3S 18V 3-WIRE SERIAL INTERFACE CS/LD SCK DI R5 3k DAC B R6 3k + 10μF 0.1μF DECODER VCSRC VCSNK R1 3.4k DAC C +IN EN R2 10.2k V+ ISRC ISNK RS 1Ω TSD OUT LT1970A SENSE+ SENSE– FILTER V– VEE R3 3.4k DAC D VCC –IN TEST PIN LOAD COMMON SENSE R4 10.2k + –18V LTC1664 QUAD 10-BIT DAC FORCE 10μF 0.1μF 1970A F07 Figure 7. Digitally Controlled Analog Pin Driver 1970afa 16 LT1970A APPLICATIONS INFORMATION Figure 6 shows the LT1970A driving an inductive load with a controlled amount of current. This load is shown as a generic magnetic transducer, which could be used to create and modulate a magnetic field. Driving the current limit control inputs directly forces a current through the load that could range up to 2MHz in modulation. Clamp diodes are added to protect the LT1970A output from large inductive flyback potentials caused by rapid di/dt changes. Supply Bypassing The LT1970A can supply large currents from the power supplies to a load at frequencies up to 4MHz. Power supply impedance must be kept low enough to deliver these currents without causing supply rails to droop. Low ESR capacitors, such as 0.1μF or 1μF ceramics, located close to the pins are essential in all applications. When large, high speed transient currents are present additional capacitance may be needed near the chip. Check supply rails with a scope and if signal related ripple is seen on the supply rail, increase the decoupling capacitor as needed. To ensure proper start-up biasing of the LT1970A, it is recommended that the rate of change of the supply voltages at turn-on be limited to be no faster than 6V/μs. Application Circuit Ideas The digitally controlled analog pin driver is shown in Figure 7. All of the control signals are provided by an LTC®1664 quad, 10-bit DAC by way of a 3-wire serial interface. The LT1970A is configured as a simple difference amplifier with a gain of 3. This gain is required to produce ±15V from the 0V to 5V outputs from DACs C and D. To provide voltage headroom, the supplies for the LT1970A are set to the maximum value of ±18V. As ±18V is the absolute maximum rating of supply voltage for the LT1970A, care must be taken to not allow the supply voltage to increase. DACs A and B separately control the sinking and sourcing current limit to the load over the range of ± 4mA to ±500mA. An optional on/off control for the pin driver using the ENABLE input is shown. If always enabled the ENABLE pin should be tied to VCC. In some applications it may be necessary to know what the current into the load is at any time. Figure 8 shows an LT1787 high side current sense amplifier monitoring the current through sense resistor RS. The LT1787 is biased from the VEE supply to accommodate the common mode input range of ±10V. The sense resistor is scaled down to provide a 100mV maximum differential signal to the current sense amplifier to preserve linearity. The LT1880 amplifier provides gain and level shifting to produce a 0V to 5V output signal (2.5V DC ±5mV/mA) with up to 1kHz full-scale bandwidth. An A/D converter could then digitize this instantaneous current reading to provide digital feedback from the circuit. The LT1970A is just as easy to use as a standard operational amplifier. Basic amplification of a precision reference voltage creates a very simple bench DC power supply as shown in Figure 9. The built-in power stage produces an adjustable 0V to 25V at 4mA to 100mA of output current. Voltage and current adjustments are derived from the LT1634-5 5V reference. The output current capability is 500mA, but this supply is restricted to 100mA for power dissipation reasons. The worst-case output voltage for maximum power dissipated in the LT1970A output stage occurs if the output is shorted to ground or set to a voltage near zero. Limiting the output current to 100mA sets the maximum power dissipation to 3W. To allow the output to range all the way to 0V, an LTC1046 charge pump inverter is used to develop a –5V supply. This produces a negative rail for the LT1970A which has to sink only the quiescent current of the amplifier, typically 7mA. Using a second LT1970A, a 0V to ±12V dual tracking power supply is shown in Figure 10. The midpoint of two 10k resistors connected between the + and – outputs is held at 0V by the LT1881 dual op amp servo feedback loop. To maintain 0V, both outputs must be equal and opposite in polarity, thus they track each other. If one output reaches current limit and drops in voltage, the other output follows to maintain a symmetrical + and – voltage across a common load. Again, the output current limit is less than the full capability of the LT1970A due to thermal reasons. Separate current limit indicators are used on each LT1970A because one output only sources current and the other only sinks current. Both devices can share the same thermal shutdown indicator, as the output flags can be OR’ed together. 1970afa 17 LT1970A APPLICATIONS INFORMATION VCC 0V TO 1V 12V VCSRC VCSNK +IN EN VCC V+ ISRC ISNK RS 0.2Ω TSD OUT LT1970A SENSE+ – SENSE FILTER V– VEE –IN RLOAD COMMON R4 255k LT1787 RG VS– –12V RF VS+ BIAS –12V R1 60.4k 20k VEE R2 10k 12V – + R3 20k –12V VOUT 2.5V ±5mV/mA LT1880 1kHz FULL CURRENT BANDWIDTH –12V 0V TO 5V A/D 1970A F08 OPTIONAL DIGITAL FEEDBACK Figure 8. Sensing Output Current 30V DC R1 2.1k R2 40k R3 10k R4 10k OUTPUT VOLTAGE ADJUST CURRENT LIMIT ADJUST VCSRC VCSNK +IN LT1634-5 –IN COMMON R5 5.49k LOAD FAULT EN VCC V+ ISRC ISNK + + RF 10.2k + VOUT 0V TO 25V 4mA TO 100mA C3 10μF GND –5V LTC1046 RG 2.55k RS 1Ω TSD OUT LT1970A SENSE+ – SENSE FILTER – V VEE C2 10μF C1 10μF 1970A F09 Figure 9. Simple Bench Power Supply 1970afa 18 LT1970A APPLICATIONS INFORMATION R6 18.2k 15V VCSRC VCSNK R5 13k –IN VCC R8 3k +OUT CURRENT LIMIT THERMAL FAULT 0.1 V+ ISRC ISNK 10μF RS1 1Ω TSD OUT LT1970A SENSE+ – SENSE FILTER V– VEE +IN + + CURRENT LIMIT ADJUST 15V R11 10k 1/2 LT1881 – R12 10k OPTIONAL SYMMETRY ADJUST 100Ω 1/2 LT1881 R13 25.5k GROUND –15V 15V R15 3k R14 10.7k VCSRC VCSNK –IN +IN R10 10k 1% TO TSD PIN OF +OUT –OUT CURRENT LIMIT EN VCC V+ ISRC ISNK TSD OUT LT1970A SENSE+ – SENSE FILTER V– VEE RS2 1Ω + C3 10μF –OUT 0V TO –12V 4mA TO 150mA 1970A F10 COMMON –15V + R4 10k C1 1μF –15V + R3 23.2k 5V REF VOUT ADJUST R2 10k R9 10k 1% – R1 6.19k +OUT 0V TO 12V 4mA TO 150mA C2 10μF COMMON 18V LT1634-5 EN + R7 3k 10μF 0.1μF Figure 10. Dual Tracking Bench Power Supply 1970afa 19 LT1970A APPLICATIONS INFORMATION Another simple linear power amplifier circuit is shown in Figure 11. This uses the LT1970A as a linear driver of a DC motor with speed control. The ability to source and sink the same amount of output current provides for bidirectional rotation of the motor. Speed control is managed by sensing the output of a tachometer built on to the motor. A typical feedback signal of 3V/1000rpm is compared with the desired speed-set input voltage. Because the LT1970A is unity-gain stable, it can be configured as an integrator to force whatever voltage across the motor as necessary to match the feedback speed signal with the set input signal. Additionally, the current limit of the amplifier can be adjusted to control the torque and stall current of the motor. For reliability, a feedback scheme similar to that shown in Figure 4 can be used. Assuming that a stalled rotor will generate a current limit condition, the stall current limit can be significantly reduced to prevent excessive power dissipation in the motor windings. 15V +IN –IN EN VCC V+ ISRC ISNK TSD OUT LT1970A SENSE+ – SENSE FILTER V– VEE RS 1Ω 12V DC MOTOR COMMON GND 15V R1 1.2k R2 10k –15V REVERSE R4 49.9k R5 49.9k C1 1μF The other half of the LT1638 is used as a simple pulse oscillator to control the periodic sampling of the motor back EMF. Figure 13 shows how easy it is to boost the output current of the LT1970A. This ±5A power stage uses complementary external N- and P-channel MOSFETs to provide the additional current. The output stage power supply inputs, V+ and V–, are used to provide gate drive as needed. With higher output currents, the sense resistor RCS, is reduced in value to maintain the same easy current limit control. OV TO 5V TORQUE/STALL CURRENT CONTROL VCSRC VCSNK For motor speed control without using a tachometer, the circuit in Figure 12 shows an approach. Using the enable feature of the LT1970A, the drive to the motor can be removed periodically. With no drive applied, the spinning motor presents a back EMF voltage proportional to its rotational speed. The LT1782 is a tiny rail-to-rail amplifier with a shutdown pin. The amplifier is enabled during this interval to sample the back EMF voltage across the motor. This voltage is then buffered by one-half of an LT1638 dual op amp and used to provide the feedback to the LT1970A integrator. When re-enabled the LT1970A will adjust the drive to the motor until the speed feedback voltage, compared to the speed-set input voltage, settles the output to a fixed value. A 0V to 5V signal for the motor speed input controls both rotational speed and direction. TACH FEEDBACK 3V/1000rpm 1970A F11 FORWARD R3 1.2k –15V Figure 11. Simple Bidirectional DC Motor Speed Controller This Class B power stage is intended for DC and low frequency, <1kHz, applications as crossover distortion becomes evident at higher frequencies. Figure 13 shows some optional resistor dividers between the output connections and the current sense inputs. They are required only if the load of this power stage is removed or at a very low current level. Large power devices with no load on them can saturate and pull the output voltage very close to the power supply rails. The current sense amplifiers operate properly with input voltages at least 1V away from the VCC and VEE supply rails. In boosted current applications, it may be necessary to attenuate the maximum output voltage levels by 1V before connecting to the sense input pins. This only slightly deceases the current limit thresholds. 1970afa 20 LT1970A APPLICATIONS INFORMATION 12V OV TO 5V TORQUE/STALL CURRENT CONTROL FWD 5V VCSRC VCSNK R1 10k +IN STOP R2 20k FAULT/STALL VCC V+ ISRC ISNK –IN EN TSD OUT LT1970A SENSE+ SENSE– FILTER V– VEE RS 1Ω 12V DC MOTOR COM C1 4.7μF –12V R6 49.9k R14 10k R4 100k 12V – 1/2 LT1638 + –12V R13 10k 12V R12 10k 12V LT1782 C2 SHDN 0.01μF –12V 1μF R15 100Ω + 2.5V AT 10mA R5 120k – MOTOR SPEED CONTROL 0V REV R3 2k R7 10k R8 20k + 1/2 LT1638 – R9 20k D1 R10 82.5k 1N4148 C3 0.1μF D2 R11 9.09k 1N4148 1970A F12 –12V Figure 12. Simple Bidirectional DC Motor Speed Controller Without a Tachometer 1970afa 21 LT1970A PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev I) Exposed Pad Variation CA 6.40 – 6.60* (.252 – .260) 4.95 (.195) 4.95 (.195) 20 1918 17 16 15 14 13 12 11 6.60 t0.10 2.74 (.108) 4.50 t0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 t0.05 1.05 t0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50* (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 1.20 (.047) MAX 0s – 8s 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 0.05 – 0.15 (.002 – .006) FE20 (CA) TSSOP REV I 0211 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 1970afa 22 LT1970A REVISION HISTORY REV DATE DESCRIPTION A 06/12 Corrected D1, D2 orientation in Block Diagram PAGE NUMBER 10 Changed supply voltage in Figure 12 21 1970afa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LT1970A APPLICATIONS INFORMATION CURRENT LIMIT CONTROL VOLTAGE 0V TO 5V VCC 15V R2 100Ω 10μF 0.1μF IRF9530 VCC ENABLE VCSRC +IN VCSNK R1 1k R4 100Ω V+ LT1970A –IN SENSE+ SENSE– COMMON V– OUT R5 100Ω * VEE VIN * RF 2.2k RG 2.2k RCS 0.1Ω 5W * * LOAD IRF530 R3 100Ω VEE –15V *OPTIONAL, SEE TEXT 10μF 0.1μF 1970A F13 Figure 13. AV = – 1 Amplifier with Discrete Power Devices to Boost Output Current to 5A RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1010 Fast ±150mA Power Buffer 20MHz Bandwidth, 75V/μs Slew Rate LT1206 250mA/60MHz Current Feedback Amplifier Shutdown Mode, Adjustable Supply Current LT1210 1.1A/35MHz Current Feedback Amplifier Stable with CL = 10,000pF LT1999 High Voltage Bidirectional Current Sense Amplifier –5V to 80V Input Voltage Range 1970afa 24 Linear Technology Corporation LT 0612 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2011