LT1995 - 30MHz, 1000V/µs Gain Selectable Amplifier

LT1995
32MHz, 1000V/µs
Gain Selectable Amplifier
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FEATURES
DESCRIPTIO
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The LT®1995 is a high speed, high slew rate, gain selectable amplifier with excellent DC performance. Gains from
–7 to 8 with a gain accuracy of 0.2% can be achieved using
no external components. The device is particularly well
suited for use as a difference amplifier, where the excellent
resistor matching results in a typical common mode
rejection ratio of 79dB.
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Internal Gain Setting Resistors
Pin Configurable as a Difference Amplifier,
Inverting and Noninverting Amplifier
Difference Amplifier:
Gain Range 1 to 7
CMRR > 65dB
Noninverting Amplifier:
Gain Range 1 to 8
Inverting Amplifier:
Gain Range –1 to –7
Gain Error: <0.2%
Slew Rate: 1000V/µs
Bandwidth: 32MHz (Gain = 1)
Op Amp Input Offset Voltage: 2.5mV Max
Quiescent Current: 9mA Max
Wide Supply Range: ±2.5V to ±15V
Available in 10-Lead MSOP and
10-Lead (3mm × 3mm) DFN Packages
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APPLICATIO S
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The resistors have excellent matching, 0.2% maximum at
room temperature and 0.3% from –40°C to 85°C. The
temperature coefficient of the resistors is typically
–30ppm/°C. The resistors are extremely linear with voltage, resulting in a gain nonlinearity of 10ppm.
The LT1995 is fully specified at ±2.5V, ±5V and ±15V supplies and from –40°C to 85°C. The device is available in
space saving 10-lead MSOP and 10-Lead (3mm × 3mm)
DFN packages. For a micropower precision amplifier with
precision resistors, see the LT1991 and LT1996.
Instrumentation Amplifier
Current Sense Amplifier
Video Difference Amplifier
Automatic Test Equipment
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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The amplifier is a single gain stage design similar to the
LT1363 and features superb slewing and settling characteristics. Input offset of the internal operational amplifier
is less than 2.5mV and the slew rate is 1000V/µs. The
output can drive a 150Ω load to ±2.5V on ±5V supplies,
making it useful in cable driver applications.
TYPICAL APPLICATIO
High Slew Rate Differential Gain of 1
M1 M2 M4
15V
1k
Large-Signal Transient (G = 1)
OUT
4k
2k
–
INPUT
RANGE
–15V TO 15V
+
4k
–
4k
+
LT1995
2k
1k
4k
1995 TA01b
REF
P1 P2 P4
–15V
1995 TA01a
1995fb
1
LT1995
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V+ to V–) .............................. 36V
Input Current (Note 2) ....................................... ±10mA
Output Short-Circuit Duration (Note 3) ........... Indefinite
Operating Temperature Range (Note 4) .. – 40°C to 85°C
Specified Temperature Range (Note 5) ... – 40°C to 85°C
Storage Temperature Range
MS Package .................................... – 65°C to 150°C
DD Package ..................................... – 65°C to 125°C
Maximum Junction Temperature
MS Package ..................................................... 150°C
DD Package ..................................................... 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
P1
1
10 M1
P2
2
9 M2
P4
3
VS–
4
7 VS+
REF
5
6 OUT
+ –
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
8 M4
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TOP VIEW
LT1995CDD
LT1995IDD
DD PART
MARKING*
LBJF
LBJF
TJMAX = 125°C, θJA = 160°C/W (NOTE 6)
EXPOSED PAD INTERNALLY CONNECTED TO VS–
PCB CONNECTION OPTIONAL
P1
P2
P4
VS–
REF
1
2
3
4
5
+ –
10
9
8
7
6
LT1995CMS
LT1995IMS
M1
M2
M4
VS+
OUT
MS PART
MARKING*
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 160°C/W (NOTE 6)
LTBJD
LTBJD
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
Difference Amplifier Configuration. TA = 25°C, VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VSUPPLY
GE
Gain Error
VOUT = ±12V, RL = 1k, G = 1
VOUT = ±12V, RL = 1k, G = 2
VOUT = ±12V, RL = 1k, G = 4
VOUT = ±5V, RL = 150Ω, G = 1
VOUT = ±2.5V, RL = 500Ω, G = 1
VOUT = ±2.5V, RL = 150Ω, G = 1
GNL
Gain Nonlinearity
VOS
Input Offset Voltage
Referred to Input (Note 7)
MIN
TYP
MAX
UNITS
±15V
±15V
±15V
±15V
±5V
±5V
0.05
0.05
0.05
0.05
0.05
0.05
0.2
0.2
0.2
0.25
0.2
0.25
%
%
%
%
%
%
VOUT = ±12V, RL = 1k, G = 1
±15V
10
G = 1 (MS10)
G = 1 (DD10)
G = 2 (MS10)
G = 2 (DD10)
G = 4 (MS10)
G = 4 (DD10)
G = 1 (MS10)
G = 1 (DD10)
G = 1 (MS10)
G = 1 (DD10)
±15V
±15V
±15V
±15V
±15V
±15V
±5V
±5V
±2.5V
±2.5V
1
1.5
0.7
1.2
0.6
0.9
1
1.4
1
1.3
ppm
5
9
4
6.8
3.75
5.6
5
9
5
9
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
1995fb
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LT1995
ELECTRICAL CHARACTERISTICS
Difference Amplifier Configuration. TA = 25°C, VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VSUPPLY
VOS_OA
Op Amp Input Offset Voltage
(Note 10)
G = 1 (MS10)
G = 1 (DD10)
±2.5V, ±5V, ±15V
±2.5V, ±5V, ±15V
en
Input Noise Voltage
G = 1, f = 10kHz
G = 2, f = 10kHz
G = 4, f = 10kHz
±2.5V to ±15V
±2.5V to ±15V
±2.5V to ±15V
RIN
Common Mode Input Resistance VCM = ±15V, G = 1
CIN
Input Capacitance
CMRR
MIN
TYP
MAX
UNITS
0.5
0.75
2.5
4.5
mV
mV
27
18
14
nV/√Hz
nV/√Hz
nV/√Hz
±15V
4
kΩ
±15V
2.5
pF
Input Voltage Range
G=1
±15V
±5V
±2.5V
±15
±5
±1
±15.5
±5.5
±1.5
V
V
V
Common Mode Rejection Ratio
Referred to Input
G = 1, VCM = ±15V
G = 2, VCM = ±15V
G = 4, VCM = ±15V
G = 1, VCM = ±5V
G = 1, VCM = ±1V
±15V
±15V
±15V
±5V
±2.5V
65
71
75
65
61
79
84
87
73
68
dB
dB
dB
dB
dB
PSRR
Power Supply Rejection Ratio
P1 = M1 = 0V, G = 1, VS = ±2.5V to ±15V
78
87
dB
VOUT
Output Voltage Swing
RL = 1k
RL = 500Ω
RL = 500Ω
RL = 500Ω
±15V
±15V
±5V
±2.5V
±13.5
±13
±3.5
±1.3
±14
±13.5
±4
±2
V
V
V
V
ISC
Short-Circuit Current
G=1
±15V
±70
±120
mA
SR
Slew Rate
G = –2, VOUT = ±12V, P2 = 0V
Measured at VOUT = ±10V
G = –2, VOUT = ±3.5V, P2 = 0V
Measured at VOUT = ±2V
±15V
750
1000
V/µs
±5V
450
V/µs
FPBW
Full Power Bandwidth
10V Peak, G = –2 (Note 8)
3V Peak, G = –2 (Note 8)
±15V
±5V
16
24
MHz
MHz
HD
Total Harmonic Distortion
G = 1, f = 1MHz, RL = 1k, VOUT = 2VP-P
±15V
–81
dB
–3dB Bandwidth
G=1
±15V
±5V
±2.5V
32
25
21
MHz
MHz
MHz
tr, tf
Rise Time, Fall Time
10% to 90%, 0.1V, G = 1
±15V
±5V
10
15
ns
ns
OS
Overshoot
0.1V, G = 1, CL = 10pF
±15V
±5V
30
30
%
%
tpd
Propagation Delay
50% VIN to 50% VOUT, 0.1V, G = 1
±15V
±5V
9
11
ns
ns
ts
Settling Time
10V Step, 0.1%, G = 1
5V Step, 0.1%, G = 1
±15V
±5V
100
110
ns
ns
∆G
Differential Gain
G = 2, RL = 150Ω
±15V
0.06
%
∆θ
Differential Phase
G = 2, RL = 150Ω
±15V
0.15
Deg
ROUT
Output Resistance
f = 1MHz, G = 1
±15V
1.5
Ω
IS
Supply Current
G=1
±15V
±5V
7.1
6.7
9.0
8.5
mA
mA
1995fb
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LT1995
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C.
Difference Amplifier Configuration. VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VSUPPLY
GE
Gain Error
VOUT = ±12V, RL = 1k, G = 1
VOUT = ±12V, RL = 1k, G = 2
VOUT = ±12V, RL = 1k, G = 4
VOUT = ±2.5V, RL = 500Ω, G = 1
VOUT = ±2.5V, RL = 150Ω, G = 1
±15V
±15V
±15V
±5V
±5V
VOS
Input Offset Voltage
Referred to Input (Note 7)
G = 1 (MS10)
G = 1 (DD10)
G = 2 (MS10)
G = 2 (DD10)
G = 4 (MS10)
G = 4 (DD10)
G = 1 (MS10)
G = 1 (DD10)
G = 1 (MS10)
G = 1 (DD10)
VOS TC
Input Offset Voltage Drift
Referred to Input (Note 9)
VOS_OA
MIN
TYP
MAX
UNITS
●
●
●
●
●
0.05
0.05
0.05
0.05
0.05
0.25
0.25
0.25
0.25
0.35
%
%
%
%
%
±15V
±15V
±15V
±15V
±15V
±15V
±5V
±5V
±2.5V
±2.5V
●
●
●
●
●
●
●
●
●
●
1.1
1.5
0.8
1.2
0.7
0.9
1
1.4
1
1.3
6.5
11.5
5.5
9
5
7.5
6.5
11.5
6.5
11.5
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
G = 1 (MS10)
G = 1 (DD10)
±15V
±15V
●
●
10
10
26
35
Op Amp Input Offset Voltage
(Note 10)
G = 1 (MS10)
G = 1 (DD10)
±2.5V, ±5V, ±15V
±2.5V, ±5V, ±15V
●
●
0.55
0.75
3.25
5.75
Input Voltage Range
G=1
±15V
±5V
±2.5V
●
●
●
±15
±5
±1
±15.5
±5.5
±1.5
V
V
V
CMRR
Common Mode Rejection Ratio
Referred to Input
VCM = ±15V, G = 1
VCM = ±15V, G = 2
VCM = ±15V, G = 4
VCM = ±5V, G = 1
VCM = ±1V, G = 1
±15V
±15V
±15V
±5V
±2.5V
●
●
●
●
●
63
69
73
62
59
77
83
86
72
66
dB
dB
dB
dB
dB
PSRR
Power Supply Rejection Ratio
P1 = M1 = 0V, G = 1, VS = ±2.5V to ±15V
●
76
86
dB
VOUT
Output Voltage Swing
RL = 1k
RL = 500Ω
RL = 500Ω
RL = 500Ω
±15V
±15V
±5V
±2.5V
●
●
●
●
±13.1
±12.6
±3.4
±1.2
±14
±13.5
±4
±2
V
V
V
V
ISC
Short-Circuit Current
G=1
±15V
●
±55
±115
mA
SR
Slew Rate
G = –2, VOUT = ±12V, P2 = 0V
Measured at VOUT = ±10V
±15V
●
600
900
V/µs
IS
Supply Current
G=1
±15V
±5V
●
●
7.9
7.4
µV/°C
µV/°C
mV
mV
10.5
9.9
mA
mA
TYP
MAX
UNITS
0.05
0.05
0.05
0.05
0.05
0.3
0.35
0.35
0.3
0.5
%
%
%
%
%
The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C.
Difference Amplifier Configuration. VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VSUPPLY
GE
Gain Error
VOUT = ±12V, RL = 1k, G = 1
VOUT = ±12V, RL = 1k, G = 2
VOUT = ±12V, RL = 1k, G = 4
VOUT = ±2.5V, RL = 500Ω, G = 1
VOUT = ±2.5V RL = 150Ω, G = 1
±15V
±15V
±15V
±5V
±5V
MIN
●
●
●
●
●
1995fb
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LT1995
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C.
Difference Amplifier Configuration. VREF = VCM = 0V and unused gain pins are unconnected, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VSUPPLY
VOS
Input Offset Voltage
Referred to Input (Note 7)
G = 1 (MS10)
G = 1 (DD10)
G = 2 (MS10)
G = 2 (DD10)
G = 4 (MS10)
G = 4 (DD10)
G = 1 (MS10)
G = 1 (DD10)
G = 1 (MS10)
G = 1 (DD10)
±15V
±15V
±15V
±15V
±15V
±15V
±5V
±5V
±2.5V
±2.5V
VOS TC
Input Offset Voltage Drift
Referred to Input (Note 9)
G = 1 (MS10)
G = 1 (DD10)
VOS_OA
Op Amp Input Offset Voltage
(Note 10)
Input Voltage Range
MIN
TYP
MAX
UNITS
●
●
●
●
●
●
●
●
●
●
1.2
1.6
0.9
1.2
0.7
0.9
1.1
1.4
1.1
1.5
7.5
13
6
10
5.5
8.5
7.5
13
7.5
13
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
±15V
±15V
●
●
10
10
26
35
µV/°C
µV/°C
G = 1 (MS10)
G = 1 (DD10)
±2.5V, ±5V, ±15V
±2.5V, ±5V, ±15V
●
●
0.6
0.8
3.75
6.5
G=1
±15V
±5V
±2.5V
●
●
●
±15
±5
±1
±15.5
±5.5
±1.5
V
V
V
±15V
±15V
±15V
±5V
±2.5V
●
●
●
●
●
62
68
72
61
57
77
83
86
72
66
dB
dB
dB
dB
dB
●
74
86
dB
mV
mV
CMRR
Common Mode Rejection Ratio VCM = ±15V, G = 1
Referred to Input
VCM = ±15V, G = 2
VCM = ±15V, G = 4
VCM = ±5V, G = 1
VCM = ±1V, G = 1
PSRR
Power Supply Rejection Ratio
P1 = M1 = 0V, G = 1, VS = ±2.5V to ±15V
VOUT
Output Voltage Swing
RL = 1k
RL = 500Ω
RL = 500Ω
RL = 500Ω
±15V
±15V
±5V
±2.5V
●
●
●
●
±13
±12.5
±3.3
±1.1
±14
±13.5
±4
±2
V
V
V
V
ISC
Short-Circuit Current
G=1
±15V
●
±50
±105
mA
SR
Slew Rate
G = –2, VOUT = ±12V, P2 = 0V
Measured at VOUT = ±10V
±15V
●
550
900
V/µs
IS
Supply Current
G=1
±15V
±5V
●
●
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The inputs are protected by diodes connected to VS+ and VS–.
If an input goes beyond the supply range, the input current should be
limited to 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum.
Note 4: The LT1995C and LT1995I are guaranteed functional over the
operating temperature range of –40°C to 85°C.
Note 5: The LT1995C is guaranteed to meet specified performance from
0°C to 70°C. The LT1995C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LT1995I is guaranteed to meet
specified performance from –40°C to 85°C.
8.0
7.6
11.0
10.4
mA
mA
Note 6: Thermal resistance (θJA) varies with the amount of PC board metal
connected to the leads. The specified values are for short traces connected
to the leads. If desired, the thermal resistance can be reduced slightly in
the MS package to about 130°C/W by connecting the used leads to a
larger metal area. A substantial reduction in thermal resistance down to
about 50°C/W can be achieved by connecting the Exposed Pad on the
bottom of the DD package to a large PC board metal area which is either
open-circuited or connected to VS–.
Note 7: Input offset voltage is pulse tested and is exclusive of warm-up
drift. VOS and VOS TC refer to the input offset of the difference amplifier
configuration. The equivalent input offset of the internal op amp can be
calculated from VOS_OA = VOS • G/(G +1).
Note 8: Full Power bandwidth is calculated from the slew rate measurement: FPBW = SR/2πVP.
Note 9: This parameter is not 100% tested.
Note 10: The input offset of the internal op amp is calculated from the
input offset voltage: VOS_OA = VOS • G/(G +1).
1995fb
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LT1995
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TYPICAL PERFOR A CE CHARACTERISTICS (Difference Amplifier Configuration)
Supply Current vs Supply Voltage
and Temperature
VOS Distribution
25
10
15
10
INPUT VOLTAGE NOISE (nV/√Hz)
TA = 125°C
8
SUPPLY CURRENT (mA)
TA = 25°C
6
TA = –55°C
4
5
2
0
1.5 2.5
–3.5 –2.5 –1.5 –0.5 0.5
INPUT OFFSET VOLTAGE (mV)
0
3.5
10
5
15
SUPPLY VOLTAGE (±V)
0
1995 G01
G=2
G=1
–0.03
–1.5
RL = 500Ω
1.5
RL = 1k
1
2
3 4 5 6 7 8
RESISTIVE LOAD (kΩ)
9
10
V–
10
5
15
SUPPLY VOLTAGE (±V)
0
120
OUTPUT SHORT-CIRCUIT CURRENT (mA)
200
G=1
G=7
100
50
0
0
1
2
3
4
TIME AFTER POWER ON (MINUTES)
5
1995 G07
–1.0
–1.5
–40°C
3.0
–2.0
85°C
85°C
25°C
2.5
2.0
–40°C
1.5
V–
–50
20
–25
0
25
OUTPUT CURRENT (mA)
50
1995 G06
Output Short-Circuit Current
vs Temperature
VS = ±15V
TA = 25°C
MS PACKAGE
150
–0.5
25°C
1995 G05
Warm-Up Drift vs Time
250
V+
VS = ±5V
0.5
1995 G04
300
100
1.0
0.5
–0.04
CHANGE IN INPUT OFFSET VOLTAGE (µV)
–1.0
RL = 500Ω
1.0
0
1
10
FREQUENCY (kHz)
1995 G03
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
CHANGE IN GAIN ERROR (%)
0
–0.05
0.1
–0.5
G=4
–0.02
1
0.01
V+
RL = 1k
0.01
–0.01
G=4
Output Voltage Swing vs Load
Current
TA = 25°C
G=7
0.02
G=2
G=7
10
Output Voltage Swing vs Supply
Voltage
VS = ±15V
TA = 25°C
VOUT = ±12V
0.04
G=1
1995 G02
Change in Gain Error
vs Resistive Load
0.05
VS = ±15V
TA = 25°C
100
20
Output Impedance vs Frequency
1000
VS = ±5V
VS = ±15V
TA = 25°C
100
80
SOURCE
60
SINK
40
OUTPUT IMPEDACNE (Ω)
NUMBER OF UNITS (%)
VS = ±15V
VCM = 0V
G=1
20
MS PACKAGE
0.03
Input Noise Spectral Density
1000
100
G=7
10
G=1
1
20
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
1995 G08
0.1
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1995 G09
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LT1995
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TYPICAL PERFOR A CE CHARACTERISTICS (Difference Amplifier Configuration)
Settling Time vs Output Step
(Non-Inverting)
Settling Time vs Output Step
(Inverting)
10
10
VS = ±15V
8 TA = 25°C
RL = 1k
6 G = –1
VS = ±15V
8 TA = 25°C
RL = 1k
6 G=1
10mV
2
OUTPUT STEP (V)
4
1mV
0
–2
10mV
1mV
–4
1M
10M
FREQUENCY (Hz)
100M
–8
20
0
40
60 80 100 120 140 160 180
SETTLING TIME (ns)
1mV
20
0
40
60 80 100 120 140 160
SETTLING TIME (ns)
1995 G12
30
–3dB BANDWIDTH
30
25
20
42
OVERSHOOT
CL = 15pF
41
–3dB BANDWIDTH (MHz)
–3dB BANDWIDTH (MHz)
60
G = –1
VS = ±15V
25
VS = ±5V
–3dB BANDWIDTH
20
50
OVERSHOOT
CL = 15pF
45
VS = ±15V
40
VS = ±5V
5
4
GAIN (V/V)
6
8
7
2
0
4
8 10 12 14
6
SUPPLY VOLTAGE (±V)
Frequency Response vs Supply
Voltage (G = 1, G = –1)
20
TA = 25°C
8 RL = 1k
±15V
±5V
–2
–4
–6
VOLTAGE MAGNITUDE (dB)
15
6
0
–50 –25
VS = ±15V
TA = 25°C
RL = ∞
G = –1
10
C = 50pF
0
–5
C = 0pF
–8
–15
100M
1995 G16
1
35
125
100
C = 200pF
C = 100pF
5
100
Common Mode Rejection Ratio
vs Frequency
–10
1M
10M
FREQUENCY (Hz)
50
25
75
0
TEMPERATURE (°C)
1995 G15
Frequency Response
vs Capacitive Load
10
2
40
1995 G14
1995 G13
±2.5V
18
16
OVERSHOOT (%)
80
35
TA = 25°C
G = –1
35
100
–3dB Bandwidth and Overshoot
vs Temperature
OVERSHOOT (%)
SETTLING TIME (ns)
10mV
–4
–10
40
120
GAIN (dB)
0
–2
–8
–3dB Bandwidth and Overshoot
vs Supply Voltage
140
–10
100k
1mV
1995 G11
Settling Time vs Gain
(Non-Inverting)
4
10mV
2
–10
1995 G10
40 VS = ±15V
TA = 25°C
20 ∆VOUT = 10V
RL = 1k
0.1% SETTLING
0
1
3
2
4
–6
–6
COMMON MODE REJECTION RATIO (dB)
20
18
G=7
16
14
G=4
12
10
8
G=2
6
4
2
G=1
0
–2
–4 V = ±15V
S
–6 T = 25°C
A
–8 RL = 1k
–10
100k
10k
OUTPUT STEP (V)
GAIN (dB)
Gain vs Frequency
10
FREQUENCY (MHz)
100
1995 G17
VS = ±15V
90 TA = 25°C
G=1
80
70
60
50
40
30
20
10
0
1k
10k
1M
100k
FREQUENCY (Hz)
10M
100M
1995 G18
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LT1995
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TYPICAL PERFOR A CE CHARACTERISTICS (Difference Amplifier Configuration)
Power Supply Rejection Ratio
vs Frequency
Slew Rate vs Supply Voltage
VS = ±15V
TA = 25°C
G=1
70
TA = 25°C
1400 G = –1 +
VOUT = VS – VS– – 3VP-P
+PSRR
50
–PSRR
40
30
20
10
0
–10
10k
1k
1M
100k
FREQUENCY (Hz)
1400
1200
60
10M
1000
800
600
5
0
10
1000
800
600
400
6 8 10 12 14 16 18 20
INPUT LEVEL (VP-P)
30
TA = 25°C
Vo = 3VRMS
RL = 500Ω
25
0.001
G=1
G = –1
0.0001
0.01
0
0.1
1
10
FREQUENCY (kHz)
G=1
20
G = –1
15
10
5 VS = ±15V
TA = 25°C
HD <2%
0
0.1
100
1
FREQUENCY (MHz)
1995 G24
2nd and 3rd Harmonic Distortion
vs Frequency
Differential Gain and Phase
vs Supply Voltage
–40
VS = ±5V
9 TA = 25°C
HD <2%
8
G=1
5
4
G = –1
3
2
1995 G25
0.3
0.2
–70
2ND HARMONIC
–80
3RD HARMONIC
1
10
0.4
–60
–90
1
FREQUENCY (MHz)
0.5
TA = 25°C
RL = 150Ω
G=2
DIFFERENTIAL PHASE (DEG)
6
DISTORTION (dBc)
VS = ±15V
VOUT = 2VP-P
–50 RL = 500Ω
G=2
–100
0.1
1
FREQUENCY (MHz)
10
1995 G26
DIFFERENTIAL
GAIN
1.0
0.1
0.8
0
DIFFERENTIAL GAIN (%)
10
7
10
1995 G23
1995 G22
Undistorted Output Swing vs
Frequency (±5V)
125
100
Undistorted Output Swing vs
Frequency (±15V)
OUTPUT VOLTAGE (VP-P)
0.01
TOTAL HARMONIC DISTORTION (%)
SLEW RATE (V/µs)
0
25
50
75
TEMPERATURE (°C)
1995 G21
Total Harmonic Distortion vs
Frequency
200
OUTPUT VOLTAGE (VP-P)
–25
1995 G20
TA = 25°C
V = ±15V
1200 GS= –1
0
0.1
0
–50
15
SUPPLY VOLTAGE (±V)
1400
4
VS = ±5V
VOUT = 7VP-P
600
200
Slew Rate vs Input Level
2
800
400
1995 G19
0
1000
200
0
VS = ±15V
VOUT = 27VP-P
1200
400
100M
G = –2
1600
SLEW RATE (V/µs)
80
Slew Rate vs Temperature
1800
1600
SLEW RATE (V/µs)
POWER SUPPLY REJECTION RATIO (dB)
90
0.6
0.4
DIFFERENTIAL
PHASE
0.2
0
0
5
10
15
20
SUPPLY VOLTAGE (V)
25
30
1995 G27
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TYPICAL PERFOR A CE CHARACTERISTICS (Difference Amplifier Configuration)
Capacitive Load Handling
Capacitive Load Handling
100
100
70
G=1
G=2
G=4
OVERSHOOT (%)
OVERSHOOT (%)
VS = ±15V
90 TA = 25°C
RL = ∞
80
G=7
60
50
40
30
VS = ±5V
90 TA = 25°C
RL = ∞
80
G=1
70
50
30
20
10
1000pF 0.01µF 0.1µF
CAPACITIVE LOAD
0
10pF
1µF
G=7
40
10
100pF
G=4
60
20
0
10pF
G=2
100pF
1000pF 0.01µF 0.1µF
CAPACITIVE LOAD
1µF
1995 G29
1995 G28
Small-Signal Transient (G = 1)
Small-Signal Transient (G = –1)
Small-Signal Transient
(Noninverting, G = 1, CL = 100pF)
VS = ±15V
RL = 1k
VS = ±15V
RL = 1k
VS = ±15V
RL = 1k
100ns/DIV
1995 G30
100ns/DIV
1995 G31
100ns/DIV
1995 G32
Large-Signal Transient (G = 1)
Large-Signal Transient (G = –1)
Large-Signal Transient
(Noninverting, G = 1, CL = 100pF)
VS = ±15V
RL = 1k
VS = ±15V
RL = 1k
VS = ±15V
RL = 1k
100ns/DIV
1995 G33
100ns/DIV
1995 G34
100ns/DIV
1995 G35
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LT1995
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PI FU CTIO S (Difference Amplifier Configuration)
P1 (Pin 1): Noninverting Gain-of-1 Input. Connects a 4k
internal resistor to the op amp’s noninverting input.
OUT (Pin 6): Output Voltage. VOUT = VREF + 1 • (VP1 – VM1)
+ 2 • (VP2 – VM2) + 4 • (VP4 – VM4).
P2 (Pin 2): Noninverting Gain-of-2 Input. Connects a 2k
internal resistor to the op amp’s noninverting input.
VS+ (Pin 7): Positive Supply Voltage.
P4 (Pin 3): Noninverting Gain-of-4 Input. Connects a 1k
internal resistor to the op amp’s noninverting input.
VS– (Pin 4): Negative Supply Voltage.
REF (Pin 5): Reference Voltage. Sets the output level when
the difference between the inputs is zero. Connects a 4k
internal resistor to the op amp’s non inverting input.
M4 (Pin 8): Inverting Gain-of-4 Input. Connects a 1k
internal resistor to the op amp’s inverting input.
M2 (Pin 9): Inverting Gain-of-2 Input. Connects a 2k
internal resistor to the op amp’s inverting input.
M1 (Pin 10): Inverting Gain-of-1 Input. Connects a 4k
internal resistor to the op amp’s inverting input.
1995fb
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LT1995
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BLOCK DIAGRA
VS+
1
2
3
P1
7
RP1 = 4k
RFB = 4k
0.5pF
0.3pF
P2
RP2 = 2k
P4
RP4 = 1k
M4
RM4 = 1k
M2
RM2 = 2k
REF
5
+
–
8
9
10
M1
0.5pF
0.3pF
RM1 = 4k
RFB = 4k
VS–
4
OUT
6
1995 BD
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APPLICATIO S I FOR ATIO
Configuration Flexibility
The LT1995 combines a high speed precision operational
amplifier with eight ratio-matched on-chip resistors. The
resistor configuration and pinout of the device is shown in
the Block Diagram. The topology is extremely versatile and
provides for simple realizations of most classic functional
configurations including difference amplifiers, inverting
gain stages, noninverting gain stages (including Hi-Z
input buffers) and summing amplifiers. The LT1995 delivers load currents of at least 30mA, making it ideal for cable
driving applications as well.
The input voltage range depends on gain and configuration. ESD diodes will clamp any input voltage that exceeds
the supply potentials by more than several tenths of a volt;
and the internal op amp input ports must remain at least
1.75V within the rails to assure normal operation of the
part. The output will swing to within one and a half volts of
the rails, which in low supply voltage and high gain
configurations will create a limitation on the usable input
range. It should be noted that while the internal op amp can
withstand transient differential input voltages of up to 10V
without damage, this does generate large supply current
increases (tens of mA) as required for high slew rates. If
the device is used with sustained differential input across
the internal op amp (such as when the output is clipping),
the average supply current will increase, excessive power
dissipation will result, and the part may be damaged (i.e.,
the LT1995 is not recommended for use in comparator
applications or with the output clipped).
Difference Amplifier
The LT1995 can be connected as a classic difference
amplifier with an output function given by:
VOUT = G • (VIN+ – VIN–) + VREF
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APPLICATIO S I FOR ATIO
As shown in Figure 1, the options for fixed gain G include:
1, 1.33, 1.67, 2, 3, 4, 5, 6 and 7, all achieved by pinstrapping alone. With split-supply applications where the
output is to be ground referenced, the VREF input is simply
tied to ground. The input common mode voltage is
rejected by the high CMRR of the part within the usable
input range.
Inverting Gain Amplifier
The LT1995 can be connected as an inverting gain amplifier with an output function given by:
VOUT = –(G • VIN–) + VREF
As shown in Figure 1, the options for fixed gain G include:
1, 1.33, 1.67, 2, 3, 4, 5, 6 and 7, all achieved by pin
strapping alone. The VIN+ connection used in the difference amp configuration is simply tied to ground (or a low
impedance potential equal to the input signal bias to create
an input “virtual ground”). With split-supply applications
where the output is to be ground referenced, the VREF input
is simply tied to ground as well.
Noninverting Gain Buffer Amplifier
The LT1995 can be connected as a high input impedance
noninverting gain buffer amplifier with an output function
given by:
VOUT = G • VIN
As shown in Figure 2, the options for fixed gain G include:
1, 1.14, 1.2, 1.33, 1.4, 1.6, 2, 2.33, 2.66, 3, 4, 5, 6, 7 and
8, all achieved by pin strapping alone. With single supply
applications, the grounded M input pins may be tied to a
low impedance potential equal to the input signal bias to
create a “virtual ground” for both the input and output
signals. While there is no input attenuation from VIN to the
internal noninverting op amp port in these configurations,
the P connections vary to minimize offset by providing
balanced input resistances to the internal op amp.
Noninverting Gain Amplifier Input Attenuation
The LT1995 can also be connected as a noninverting gain
amplifier having an input attenuation network to provide a
wide range of additional noninverting gain options. In
combination with the feedback configurations for gains of
G shown in Figure 2 (connections to the M inputs), the P
and REF inputs may be connected to form several resistor
divider attenuation ratios A, so that a compound output
function is given by:
VOUT = A • G • VIN
As shown in Figure 3, the options for fixed attenuation A
include 0.875, 0.857, 0.833, 0.8, 0.75, 0.714, 0.667, 0.625
and 0.571, all achieved by pin strapping alone. With just
the attenuation configurations of Figure 3 and the feedback configurations of Figure 2, seventy-three unique
composite gains in the range of 1 to 8 are available (many
options for gain below unity also exist). Figure 3 does not
include the additional pin-strap configurations offering A
values of 0.5, 0.429, 0.375, 0.333, 0.286, 0.25, 0.2, 0.167,
0.143 and 0.125, as these values tend to compromise the
low noise performance of the part and don’t generally
contribute many more unique gain options. It should be
noted that with these configurations some degree of
imbalance will generally exist between the effective resistances RP and RM seen by the internal op amp input ports,
noninverting and inverting, respectively. Depending on
the specific combination of A and G, the following DC
offset error due to op amp input bias current (IB) should be
anticipated: The IB of the internal op amp is typically 0.6µA
and is prepackage tested to a limit of 2µA. Additional
output-referred offset = IB • (RP – RM) • G. In some
configurations, this could be as much as 1.7mV • G
additional output offset. The IOS of the internal op amp is
typically 120nA and is prepackage tested to a limit of
350nA. The Electrical Characteristics table includes the
effects of IB and IOS.
1995fb
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APPLICATIO S I FOR ATIO
8
9
VIN–
10
VIN+
1
2
3
+V
M4
M2
M1
P1
P4
VOUT
REF
5
P2
4
9
10
6
LT1995
8
VIN–
7
1
2
3
VIN+
VREF
+V
M4
M2
M1
P1
P4
–V
VOUT
REF
5
P2
1
2
9
10
1
VIN+
VIN–
2
3
8
9
10
1
2
VIN+
3
M1
8
7
M1
VIN–
6
LT1995
P1
P2
4
9
10
VOUT
REF
5
6
LT1995
P1
REF
5
P2
–V
1
2
VIN+
3
VREF
G = 1.67
+V
M4
7
M2
M1
P1
P4
VOUT
REF
5
P2
4
9
10
6
LT1995
8
VIN–
1
2
3
VIN+
VREF
+V
M4
7
M2
M1
6
LT1995
P1
REF
5
P2
4
P4
–V
–V
G = 2.00
G = 3.00
G = 4.00
+V
8
VIN–
7
9
M2
M1
6
LT1995
P1
10
VOUT
REF
5
P2
4
1
2
3
VIN+
VREF
+V
M4
7
M2
M1
P4
VOUT
REF
5
P2
4
9
10
6
LT1995
P1
8
VIN–
1
2
VIN+
VREF
3
VOUT
VREF
–V
M4
VOUT
4
P4
G = 1.33
M2
P4
7
M2
VREF
+V
M4
P4
+V
M4
–V
G = 1.00
VIN–
3
VIN+
4
VREF
8
9
10
6
LT1995
8
VIN–
7
+V
M4
7
M2
M1
6
LT1995
P1
REF
5
P2
4
P4
VOUT
1995 F01
VREF
–V
–V
–V
G = 5.00
G = 6.00
G = 7.00
Figure 1. Difference (and Inverting) Amplifier Configurations
Table 1. Pin Use, Input Range, Input Resistance, Bandwidth in Difference Amplifier Configuration
GAIN
Use of P1/M1
1
2
3
4
5
6
7
VIN
Open
VIN
Open
VIN
Open
VIN
Use of P2/M2
Open
VIN
VIN
Open
Open
VIN
VIN
Use of P4/M4
Open
Open
Open
VIN
VIN
VIN
VIN
Positive Input Range: VREF = 0V, VS = ±15V
±15V
±15V
±15V
±15V
±15V
±15V
±15V
Positive Input Range: VREF = 0V, VS = ±5V
Positive Input Range: VREF = 0V, VS = ±2.5V
Positive Input Resistance
±5V
±4.88V
±4.33V
±4.06V
±3.9V
±3.79V
±3.71V
±1.5V
±1.13V
±1V
±0.94V
±0.9V
±0.88V
±0.86V
8k
6k
5.33k
5k
4.8k
4.67k
4.57k
Minus Input Resistance
4k
2k
1.33k
1k
800Ω
667Ω
571Ω
Ref Input Resistance
8k
6k
5.33k
5k
4.8k
4.67k
4.57k
Input Common Mode Resistance, VREF = 0V
4k
3k
2.67k
2.5k
2.4k
2.33k
2.29k
Input Differential Mode Resistance, VREF = 0V
–3dB Bandwidth
8k
4k
2.67k
2k
1.6k
1.33k
1.14k
32MHz
27MHz
27MHz
23MHz
18MHz
16MHz
15MHz
1995fb
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APPLICATIO S I FOR ATIO
8
9
10
1
2
3
+V
M4
8
7
9
M2
M1
6
LT1995
P1
REF
5
P2
P4
10
VOUT
1
2
3
4
+V
M4
8
7
9
M2
M1
6
LT1995
P1
REF
5
P2
P4
–V
10
VOUT
2
3
4
9
10
1
2
3
9
M2
M1
6
LT1995
P1
REF
5
P2
10
VOUT
1
2
3
4
8
7
9
M2
M1
6
LT1995
P1
REF
5
P2
P4
10
VOUT
9
10
1
2
3
3
4
7
9
M2
M1
6
LT1995
REF
5
P1
P2
10
VOUT
1
2
3
4
+V
7
M1
9
6
LT1995
REF
5
P1
P2
P4
10
VOUT
1
2
3
M1
9
6
LT1995
P1
REF
5
P2
P4
2
3
4
10
VOUT
1
2
3
4
8
7
9
M2
M1
6
LT1995
P1
REF
5
P2
P4
10
VOUT
10
1
2
3
9
M2
M1
6
LT1995
P1
REF
5
P2
10
VOUT
1
2
3
4
–V
VIN
3
4
4
P4
+V
M4
7
M2
M1
6
LT1995
P1
REF
5
P2
VOUT
4
P4
–V
G = 5.00
+V
M4
8
7
9
M2
M1
6
LT1995
P1
REF
5
P2
P4
10
VOUT
1
2
3
4
–V
VIN
G = 6.00
VOUT
VIN
8
7
REF
5
P2
G = 4.00
+V
P4
1
2
VIN
M4
6
LT1995
P1
G = 2.66
+V
G = 3.00
9
M1
–V
VIN
7
M2
–V
M4
–V
8
1
+V
M4
VIN
8
7
4
P4
G = 2.33
M2
VOUT
1995 F02
8
M2
G = 2.00
9
REF
5
P2
–V
+V
6
LT1995
P1
G = 1.60
VIN
10
M1
–V
M4
–V
M4
7
M2
VIN
8
VIN
8
+V
M4
G = 1.40
+V
P4
1
2
VIN
M4
4
P4
–V
G = 1.33
8
P2
VOUT
G = 1.20
+V
M4
–V
VIN
REF
5
VIN
8
7
6
LT1995
P1
G = 1.14
+V
P4
M1
–V
VIN
G = 1.00
M4
7
M2
–V
VIN
8
1
+V
M4
+V
M4
7
M2
M1
REF
5
P2
VOUT
4
P4
–V
VIN
G = 7.00
6
LT1995
P1
1995 F02b
G = 8.00
Figure 2. Noninverting Buffer Amplifier Configurations (Hi-Z Input)
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8
*
VIN
9
10
1
2
3
8
*
9
10
1
2
VIN
3
8
*
9
10
1
VIN
2
3
+V
M4
8
7
M2
*
M1
6
LT1995
P1
REF
5
P2
P4
VOUT
1
VIN
4
3
7
M2
*
M1
6
LT1995
P1
REF
5
P2
VOUT
1
VIN
2
3
4
P4
9
10
+V
M4
7
M2
M1
6
LT1995
P1
REF
5
P2
P4
–V
–V
A = 0.857
A = 0.833
8
7
M2
*
M1
6
LT1995
P1
REF
5
P2
VOUT
VIN
9
10
1
2
3
4
+V
M4
8
7
M2
*
M1
6
LT1995
P1
REF
5
P2
VOUT
10
1
VIN
2
3
4
P4
9
+V
M4
7
M2
M1
6
LT1995
P1
REF
5
P2
P4
–V
–V
–V
A = 0.750
A = 0.714
+V
8
7
M2
*
M1
6
LT1995
P1
REF
5
P2
4
VOUT
VIN
9
10
1
2
3
+V
M4
8
7
M2
*
M1
6
LT1995
P1
REF
5
P2
VOUT
10
1
2
4
P4
9
VIN
3
VOUT
4
A = 0.800
M4
VOUT
4
–V
+V
P4
2
8
A = 0.875
M4
P4
9
10
+V
M4
+V
M4
7
M2
M1
6
LT1995
P1
REF
5
P2
P4
VOUT
1995 F03
4
–V
–V
–V
A = 0.667
A = 0.625
A = 0.571
*CONFIGURE M INPUTS FOR DESIRED G PARAMETER; REFER TO FIGURE 2 FOR CONNECTIONS
Figure 3. Noninverting Amplifier Input Attenuation Configurations (A > 0.5)
8
The LT1995 can be used in many single-supply applications
using AC-coupling without additional biasing circuitry.
7
AC-coupling the LT1995 in a difference amplifier configuration (as in Figure 1) is a simple matter of adding coupling
capacitors to each input and the output as shown in the
example of Figure 5. The input voltage VBIAS applied to the
REF pin establishes the quiescent voltage on the input and
output pins. The VBIAS signal should have a low source
impedance to avoid degrading the CMRR (0.5Ω for
1dB CMRR change typically).
NONINVERTING GAIN
AC-Coupling Methods for Single Supply Operation
6
5
4
3
2
1
73
1
GAIN COMBINATION
1995 F04
Figure 4. Unique Noninverting Gain Configurations
1995fb
15
LT1995
U
W
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APPLICATIO S I FOR ATIO
In operation as a noninverting gain stage, the P and REF
inputs may be configured as a “supply splitter,” thereby
providing a convenient mid-supply operating point. Figure 7 illustrates the three attenuation configurations that
generate 50% mid-supply biasing levels with no external
components aside from the desired coupling capacitors.
As with the DC-coupled input attenuation ratios, A, a
compound output function including the feedback gain
parameter G is given by:
Using the LT1995 as an AC-coupled inverting gain stage,
the REF pin and the relevant P inputs may all be driven from
a VBIAS source as depicted in the example of Figure 6, thus
establishing the quiescent voltage on the input and output
pins. The VBIAS signal will only have to source the bias
current (IB) of the noninverting input of the internal op amp
(0.6µA typically), so a high VBIAS source impedance (RS)
will cause the quiescent level of the amplifier output to
deviate from the intended VBIAS level by IB • RS.
VOUT = A • G • VIN
8
CIN
9
10
VIN–
1
CIN
2
3
VIN+
+V
M4
8
7
M2
M1
6
LT1995
P2
P4
1
2
3
4
VBIAS
*
10
1
2
VIN
3
CIN
7
M2
M1
6
LT1995
REF
5
P2
P4
*
COUT
P1
6
LT1995
4
VOUT
9
10
1
2
3
VIN
P2
4
P4
1995 F06
+V
8
M4
7
M2
M1
6
LT1995
P1
REF
5
P2
P4
*
COUT
VOUT
4
9
10
1
2
VIN
3
CIN
M4
7
M2
COUT
M1
6
LT1995
P1
REF
5
P2
P4
VOUT
4
CIN
A = 0.750
VOUT
REF
5
P1
+V
8
M4
COUT
M1
Figure 6. AC-Coupled Inverting Gain Amplifier
General Configuration (G = 5 Example)
+V
9
7
M2
VBIAS
1995 F05
Figure 5. AC-Coupled Difference Amplifier
General Configuation (G = 5 Example)
8
10
VIN–
VOUT
REF
5
P1
9
CIN
COUT
+V
M4
1995 F07
A = 0.667
A = 0.500
*CONFIGURE M INPUTS FOR DESIRED G PARAMETER; REFER TO FIGURE 2 FOR CONNECTIONS. ANY M
INPUTS SHOWN GROUNDED IN FIGURE 2 SHOULD INSTEAD BE CAPACITIVELY COUPLED TO GROUND
Figure 7. AC-Coupled Noninverting Amplifier Input Attenuation Configurations (Supply Splitting)
1995fb
16
LT1995
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APPLICATIO S I FOR ATIO
If one of the A parameter configurations in Figure 3 is
preferred, or the use of an external biasing source is
desired, the P and REF input connections shown grounded
in a Figure 3 circuit may be instead driven by a VBIAS
voltage to establish a quiescent operating point for the
input and output pins. The VIN connections of the Figure 3
circuit are then driven via a coupling capacitor. Any
grounded M inputs for the desired G configuration (refer
to Figure 2) must be individually or collectively
AC-coupled to ground. Figure 8 illustrates a complete
example circuit of an externally biased AC-coupled noninverting amplifier. The VBIAS source impedance should be
low (a few ohms) to avoid degrading the inherent accuracy
of the LT1995. 0.013% of additional Gain Error for each
ohm of resistance on the REF pin is typical.
8
CBYP
9
10
1
CIN
2
3
VIN
+V
M4
7
M2
COUT
M1
6
LT1995
REF
5
P1
P2
P4
VBIAS
4
VOUT
CONFIGURATION EXAMPLE:
A = 0.625
G = 6.00
(VOUT/VIN = 3.75V)
1995 F08
Figure 8. AC-Coupled Noninverting Amplifier
with External Bias Source (Example)
Resistor Considerations
The resistors in the LT1995 are very well matched, low
temperature coefficient thin film based elements. Although
their absolute tolerance is fairly wide (typically ±5% but
±25% worst case), the resistor matching is to within 0.2%
at room temperature, and to within 0.3% over temperature. The temperature coefficient of the resistors is typically –30ppm/°C. The resistors have been sized to accommodate 15V across each resistor, or in terms of power,
225mW in the 1k resistors, 113mW in the 2k resistors, and
56mW in the 4k resistors.
Power Supply Considerations
As with any high speed amplifier, the LT1995 printed
circuit layout should utilize good power supply decoupling
practices. Good decoupling will typically consist of one or
more capacitors employing the shortest practical interconnection traces and direct vias to a ground plane. This
practice minimizes inductance at the supply pins so the
impedance is low at the operating frequencies of the part,
thereby suppressing feedback or crosstalk artifacts that
might otherwise lead to extended settling times, frequency response anomalies, or even oscillation. For high
speed parts like the LT1995, 10nF ceramics are suitable
close-in bypass capacitors, and if high currents are being
delivered to a load, additional 4.7µF capacitors in parallel
can help minimize induced power supply transients.
Because unused input pins are connected via resistors to
the input of the op amp, excessive capacitances on these
pins will degrade the rise time, slew rate, and step response of the output. Therefore, these pins should not be
connected to large traces which would add capacitance
when not in use.
Since the LT1995 has a wide operating supply voltage
range, it is possible to place the part in situations of
relatively high power dissipation that may cause excessive
die temperatures to develop. Maximum junction temperature (TJ) is calculated from the ambient temperature (TA)
1995fb
17
LT1995
U
W
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APPLICATIO S I FOR ATIO
and power dissipation (PD) as follows for a nominal PCB
layout:
TJ = TA + (PD • θJA)
For example, in order to maintain a maximum junction
temperature of 150°C at 85°C ambient in an MS10 package, the power must be limited to 0.4W. It is important to
note that when operating at ±15V supplies, the quiescent
current alone will typically account for 0.24W, so careful
thermal management may be required if high load currents and high supply voltages are involved. By additional
copper area contact to the supply pins or effective thermal
coupling to extended ground plane(s), the thermal impedance can be reduced to 130°C/W in the MS10 package. A
substantial reduction in thermal impedance of the DD10
package down to about 50°C/W can be achieved by
connecting the Exposed Pad on the bottom of the package
to a large PC board metal area which is either opencircuited or connected to VS–.
8
9
10
1
2
3
Frequency Compensation
The LT1995 comfortably drives heavy resistive loads such
as back-terminated cables and provides nicely damped
responses for all gain configurations when doing so.
Small capacitances are included in the on-chip resistor
network to optimize bandwidth in the basic difference gain
configurations of Figure 1. For the noninverting configurations of Figure 2, where the gain parameter G is 2 or less,
significant overshoot can occur when driving light loads.
For these low gain cases, providing an RC output network
as shown in Figure 9 to create an artificial load at high
frequency will assure good damping behavior.
+V
M4
7
M2
M1
6
LT1995
REF
5
P1
P2
P4
4
VOUT
10nF
47Ω
–V
VIN
1995 F09
CONFIGURATION EXAMPLE:
G = 1.14
Figure 9. Optional Frequency Compensation
Network for (1 ≤ G ≤ 2)
Figure 10. Step Response of Circuit in Figure 9
1995fb
18
LT1995
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
10 9 8 7 6
DETAIL “A”
0.254
(.010)
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
0° – 6° TYP
GAUGE PLANE
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.497 ± 0.076
(.0196 ± .003)
REF
0.53 ± 0.152
(.021 ± .006)
1 2 3 4 5
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
0.50
(.0197)
BSC
MSOP (MS) 0603
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 ± 0.10
10
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
0.25 ± 0.05
0.200 REF
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
1995fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT1995
U
TYPICAL APPLICATIO S
Tracking Negative Reference
High Input Impedance Precision Gain of 2 Configuration
3V
8
9
10
1
2
3
+V
M4
1.25V
LT1790-1.25
7
M2
M1
6
LT1995
VOUT
REF
5
P1
P2
IIN = 600nA
4
P4
M1
LT1995
G = –1
P1
1µF
–V
–1.25V
REF
1995 TA03
1995 TA02
VIN
–3V
0A to 2A Current Source
Current Sense with Alarm
15V
15V TO –15V
15V
I
RS
0.2Ω
15V
M4
M1
P1
P4
LT1995
G=5
LT6700-3
10nF
P1
0.1Ω LT1995
G=1
M1
–
1k
REF
+
–15V
LT1880
VIN
–15V
100Ω
–15V
10k
REF
SENSE
OUTPUT
100mV/A
10k
+
–
FLAG
OUTPUT
4A LIMIT
400mV
IRF9530
1995 TA05
1995 TA04
10nF
IOUT
IOUT =
VIN
5 • RS
Single Supply Video Line Driver
5V
9
47µF
10
1
47µF
+
VIN
2
3
M4
7
M2
M1
P1
5
P2
P4
75Ω
6
LT1995
VOUT
f–3dB = 27MHz
RL = 75Ω
+
8
+
4
220µF
10k
1995 TA06
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1363
70MHz, 1000V/µs Op Amp
50ns Settling Time to 0.1%, CLOAD Stable
LT1990
High Voltage Difference Amplifier
±250V Common Mode Voltage, Micropower, Pin Selectable G = 1, 10
LT1991
Precision Gain Selectable Amplifier
Micropower, Precision, Pin Selectable G = –13 to 14
LTC1992
Fully Differential Amplifier
Differential Input and Output, Rail-to-Rail Output, IS = 1.2mA, CLOAD Stable
to 10,000pF, Adjustable Common Mode Voltage
LTC6910-x
Programmable Gain Amplifiers
3 Gain Configurations, Rail-to-Rail Input and Output
1995fb
20
Linear Technology Corporation
LT/LT 0805 REV B • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004