TI TI380PCI

TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
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Glueless Interface Between the Peripheral
Component Interconnect (PCI) Bus and the
TI380C2x Family of Processors
Compliant With PCI Specification,
Revision 2.0†
Allows Use of Existing TI2000 Drivers
Includes TI2000 Interface Configuration
Register
Supports Bus Master Operations for High
Performance
Provides 32-Bit Address-Data Path
Implements Address / Data Parity Checking
Includes Internal Error Checking for Illegal
Bus Operations
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Supports DMA Bursts With 64-Byte FIFO
Supports EPROM Interface for Remote
Program Load (RPL) Operation
Supports I2C Interface for Optional Serial
EEPROM for Configuration Information
Allows BIA to be Implemented in
Configuration EEPROM
Includes NAND Tree Structure to Allow for
In-Circuit Connectivity Testing
144-Pin JEDEC PCM Plastic Quad Flat
Package (PCM Suffix)
Operating Temperature Range
0_C to 70_C
description
The TI380PCI provides a glueless interface between a TI380C2x commprocessor and the PCI bus. The
TI380PCI transfers information / data between the PCI bus and the TI380C2x System Interface (SIF ) using any
of these three methods:
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Direct memory access (DMA)
Direct input / output (DIO)
Pseudo-direct memory access (PDMA)
DMA (or PDMA) transfers all data between host memory (by way of the PCI Local Bus) and TI380C2x local
memory. DIO accesses are typically used to load software into TI380C2x local memory and for initializing the
TI380C2x.
The TI380PCI conforms to the PCI standards found in “PCI Local Bus Specification,” Revision 2.0.†
The TI380PCI is available in a 144-pin EIAJ plastic quad flat package (PCM suffix) and is rated from 0_C to
70_C.
† The “PCI Local Bus Specification”, Revision 2.0, and the TI380C2x series of data sheets (literature numbers SPWS012, SPWS013, and
SPWS014) should be used as references to this document.
PacketBlaster
FPA
EEPROM
SIF
PCI Bus
TI380PCI
TI380C2x
RPL
ROM
DRAM
Physical
Layer
To Network
Figure 1. TI380PCI Applications Diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PacketBlaster is a trademark of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
POST OFFICE BOX 1443
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1
ADVANCE INFORMATION
D
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
pin assignments
The pin assignments for the TI380PCI (144-pin plastic quad flat package) are shown in Figure 2.
110
109
115
114
113
112
111
118
117
116
120
119
123
122
121
127
126
125
124
128
129
132
131
130
134
133
137
136
135
138
141
140
139
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
70
71
72
66
67
68
69
62
63
64
65
58
59
60
61
54
55
56
57
50
51
52
53
46
47
48
49
V DD
AD24
C/BE3
GND
IDSEL
AD23
AD22
AD21
AD20
V DD
AD19
AD18
AD17
V DD
AD16
GND
C/BE2
GND
FRAME
IRDY
TRDY
V DD
DEVSEL
STOP
PERR
SERR
PAR
GND
C/BE1
AD15
GND
AD14
AD13
V DD
AD12
AD11
41
42
43
44
45
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
ADVANCE INFORMATION
SLDS
SAS
SHALT
GND
SBGR
SIRQ
SBERR
MROMEN
MAX0
VDD
SBRLS
SCS
SRSX
SRS0
SRS1
GND
SRESET
MAX2
MBIAEN
INTA
RST
VDD
PCLK
GND
GNT
REQ
AD31
GND
AD30
AD29
GND
AD28
AD27
VDD
AD26
AD25
142
144
143
SXAL
SALE
V DD
SBCLK
SADL7/ROMD0
SADL6/ROMD1
SADL5/ROMD2
SADL4/ROMD3
GND
SADL3/ROMD4
SADL2/ROMD5
SADL1/ROMD6
SADL0/ROMD7
MBCLK1
V DD
SBRQ
SRNW
SDBEN
SOWN
SDTACK
GND
SUDS
EDC
SADH7/ROMA15
SADH6/ROMA14
SADH5/ROMA13
V DD
SADH4/ROMA12
SADH3/ROMA11
SADH2/ROMA10
SADH1/ROMA09
SADH0/ROMA08
GND
EDIO
ICT
ROMA00
PCM PACKAGE
( TOP VIEW )
NOTE: Pin 1 is positioned at the upper left corner.
Figure 2. TI380PCI Pinout
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ROMA01
ROMA02
VDD
ROMA03
ROMA04
ROMA05
ROMA06
ROMA07
GND
MADH00
MADH01
MADH02
MADH03
MADH04
VDD
MADH05
MADH06
MADH07
ROMCS
DB9 / UTP
GND
AD00
AD01
AD02
AD03
AD04
VDD
AD05
AD06
VDD
AD07
C / BE0
GND
AD08
AD09
AD10
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
block diagram
TI380PCI can connect to up to four devices in a system: the PCI bus, the SIF bus, an optional serial EEPROM,
and an optional boot ROM. The major blocks of the TI380PCI include the PCI Interface (PCIIF ), SIF, and ROM
Interface (ROMIF ) as shown in Figure 3.
ICT
MBIAEN
Burned-In
Address
Emulation
Interface
(BIF)
Local Memory
Bus Snoop
MAX2
MAX0
MROMEN
SADH0 – SADH7
AD31 – AD00
C/BE3 – C/BE0
DEVSEL
FRAME
PCI Interface
(PCIIF)
64-Byte FIFO
System Interface
(SIF)
Controls
Communication
Between
TI380C2x and
the TI380PCI
Controls
Communication
Between
TI380PCI
and PCI Bus
SADL0 – SADL7
ADVANCE INFORMATION
MBCLK1
MADH00 –0 7
DB9 / UTP
SRNW
SDTACK
SBRLS
SBRQ
SHALT
SDBEN
GNT
SALE
SXAL
IDSEL
SOWN
SBCLK
INTA
SUDS
IRDY
SLDS
PAR
PCLK
RST
SIRQ
SBGR
REQ
PERR
SERR
SBERR
STOP
TRDY
SRS0 – SRS1
SAS
SRESET
SRSX
SCS
ROMA08 – ROMA15
I2C Serial
EEPROM
Interface
(EIF)
ROM Interface
(ROMIF)
ROMA00 – ROMA07
ROMCS
EDIO
EDC
Figure 3. TI380PCI Block Diagram
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3
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Pin Functions
PIN
NAME
NO.
DESCRIPTION
I/O†
ADVANCE INFORMATION
GND
4
16
24
28
31
40
52
54
64
67
76
88
100
112
124
136
I
Ground. These pins must be attached to the common system ground plane.
DB9 / UTP
89
O
Connector. The value on DB9 / UTP indicates the type of connector in use. Upon reset, DB9 / UTP’s value
is 0.
1 = D-Shell (AUI or DB9)
0 = UTP / 10BaseT
ICT
110
I
ROMA07
ROMA06
ROMA05
ROMA04
ROMA03
ROMA02
ROMA01
ROMA00
101
102
103
104
105
107
108
109
I/O
ROM address. ROMA07 – ROMA00 form the least significant eight bits of the address for the RPL ROM.
The most significant bits (MSBs) of the ROM address are multiplexed onto the SADHx lines.
When RST is driven high, the value on ROMA07 – ROMA00 is latched into the board configuration register
in the TI380PCI configuration space. The value on ROMA07 – ROMA00 can be provided by pullup and
pulldown resistors that do not affect operation after reset. This feature allows designers to support jumpers
or board stuffing options that can be sensed by software that reads the board configuration register. If
pullup and pulldown registers are not used, the contents of the board configuration register are undefined
after reset.
ROMCS
90
O
ROMCS enables the outputs of the ROM when the ROM has been accessed. ROMCS enable allows the
data lines from the ROM to be driven.
VDD
10
22
34
37
46
50
58
70
79
82
94
106
118
130
142
I
5 - V supply. These pins must be attached to the common system power supply plane.
ICT supports in-circuit tests. ICT should be pulled high for normal operation of the TI380PCI.
When pulled along with RST to a steady low state, all bi-directional signals in the TI380PCI are configured
as inputs, and all output pins of the TI380PCI are in 3-state mode.
† I = in, O = out
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Pin Functions – System Interface†
NO.
SADH0 /ROMA08
SADH1 /ROMA09
SADH2 /ROMA10
SADH3 /ROMA11
SADH4 /ROMA12
SADH5 /ROMA13
SADH6 /ROMA14
SADH7 /ROMA15
113
114
115
116
117
119
120
121
SADL0 /ROMD7
SADL1 /ROMD6
SADL2 /ROMD5
SADL3 /ROMD4
SADL4 /ROMD3
SADL5 /ROMD2
SADL6 /ROMD1
SADL7 /ROMD0
132
133
134
135
137
138
139
140
I/O‡
DESCRIPTION
System address / data bus — high byte. These lines make up the most significant byte of each
TI380C2x address word (32-bit address bus) and data word (16-bit data bus). The most
significant bit (MSB) is SADH0, and the least significant bit (LSB) is SADH7.
I/O
Address multiplexing bits 31 – 24 and bits 15 – 8§
Data multiplexing bits 15 – 8§
During accesses to the ROM address space from the PCI bus, these lines provide the eight most
significant address bits to the ROM.
System address / data bus — low byte. These lines make up the least significant byte of each
address word (32-bit address bus) and data word (16-bit data bus). The MSB is SADL0, and the
LSB is SADL7. These address lines also make up the ROM address.
I/O
Address multiplexing bits 23 – 16 and bits 7 – 0§
Data multiplexing bits 7 – 0§
During accesses to the ROM address space from the PCI bus, these lines transfer data from the
ROM to the TI380PCI.
SALE
143
I
System address latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of
the address from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle.
Systems that implement address parity also can externally latch the parity bits (SPH and SPL)
for the latched address.
SBCLK
141
O
SIF bus clock. The TI380C2x requires SBCLK to synchronize its bus timings for all DMA transfers
(see Note 1).
ADVANCE INFORMATION
PIN
NAME
SIF bus release. SBRLS indicates to the TI380C2x that a higher-priority device requires the SIF
bus. The value on SBRLS is ignored by the TI380C2x when DMA is not performed.
SBRLS
11
O
H = The TI380C2x can hold onto the system bus.
L = The TI380C2x should release the system bus upon completion of current DMA cycle. If
the DMA transfer is not yet complete, the SIF rearbitrates for the SIF bus.
System chip select. SCS activates the system interface of the TI380C2x for a DIO read or write.
SCS
12
O
H = Not selected
L = Selected
System data bus enable. SDBEN causes the TI380PCI to allow its external data buffers to begin
driving data. SDBEN is accepted during both DIO and DMA.
SDBEN
127
I
H = Keep external data buffers in highĆimpedance state
L = Cause external data buffers to begin driving data
SOWN
126
I
SIF bus owned. SOWN signals to the PIF to indicate to external devices that the TI380C2x has
control of the SIF bus. SOWN drives the enable signal of the bus transceiver chips, which drive
the address and bus control signals.
L = TI380PCI does not have control of the SIF bus.
H = TI380PCI has control of the SIF bus.
† The TI380PCI SIF pin names correspond to a subset of the system interface pins on a TI380C2x. Consult the TI380C2x data sheet for more
information on individual pins. Like-named pins on the TI380PCI and TI380C2x system interfaces are intended to be connected to each other.
‡ I = in, O = out
§ Typical bit ordering for Intel and Motorola processor buses
NOTE 1: The TI380PCI allows driver software to set SBCLK output to a steady high state. This signal is driven to a steady high state during
power-down operations.
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5
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Pin Functions – System Interface† (Continued)
PIN
NAME
NO.
I/O‡
DESCRIPTION
System reset. SRESET is sent to initialize the TI380C2x. It is set low whenever RST goes low or by
a config write to MISCCTRL.
SRESET
17
SRSX
SRS0
SRS1
13
14
15
O
H
= No system reset
L
= System reset
Rising edge = Latch bus width for DMA operation
System register select. These outputs are sent to select the word or byte to be transferred during a
system DIO access. The most significant bit is SRSX and the least significant bit is SRS1.
O
Registers selected =
SXAL
144
I
MSB
SRSX
SRS0
LSB
SRS1
System extended address latch. SXAL provides the enable pulse that externally latches the most
significant 16 bits of the 32-bit system address during DMA. SXAL is activated by the TI380C2x prior
to the first cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of
the DMA address counter causes a carryout of the lower 16 bits).
ADVANCE INFORMATION
Upper data strobe. SUDS serves as the active-low upper data strobe. SUDS is an output during DIO
and an input during DMA.§
SUDS
123
I/O
H = Not valid data on SADH0 – SADH7 lines
L = Valid data on SADH0 – SADH7 lines
SDTACK
125
I/O
System data transfer acknowledge. The purpose of SDTACK is to indicate to the bus master that a data
transfer is complete. SDTACK is internally synchronized to SBCLK by the TI380C2x. During DMA
cycles, it is asserted before the falling edge of SBCLK in state T2 by the TI380PCI to prevent a wait
state. SDTACK is an input when the TI380C2x is selected for DIO, and an output otherwise.§
H = System bus NOT ready
L = Data transfer is complete; system bus is ready.
SBERR
7
O
Bus error. SBERR corresponds to the bus error signal of the 68000 microprocessor. SBERR is driven
low during a DMA cycle to indicate to the TI380C2x that the cycle must be terminated. See Section
3.4.5.3 of the TMS380 Second - Generation Token Ring User’s Guide (SPWU005) for more
information.
Lower data strobe. SLDS is an output during DIO and an input during DMA. SLDS serves as the
active-low lower data strobe.§
SLDS
1
I/O
H = Not valid data on SADL0-SADL7 lines
L = Valid data on SADL0-SADL7 lines
SHALT
3
O
System halt/bus error retry. If SHALT is asserted along with bus error (SBERR), the adapter retries the
last DMA cycle. This is the rerun operation as defined in the 68000 specification. See Section 3.4.5.3
of the TMS380 Second - Generation Token Ring User’s Guide (SPWU005) for more information.
System bus grant. SBGR serves as an active-low bus grant, as defined in the standard 68000
interface.
SBGR
5
O
H = System bus not granted
L = System bus granted
System bus request. SBRQ is used to request control of the system bus in preparation for a DMA
transfer. SBRQ is internally synchronized to SBCLK.
SBRQ
129
I
H = System bus not requested
L = System bus requested
† The TI380PCI SIF pin names correspond to a subset of the system interface pins on a TI380C2x. Consult the TI380C2x data sheet for more
information on individual pins. Like-named pins on the TI380PCI and TI380C2x system interfaces are intended to be connected to each other.
‡ I = in, O = out
§ The signal connecting this pin to the TI380C2x also should be connected to a 4.7-kW pullup resistor.
6
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Pin Functions – System Interface† (Continued)
PIN
NAME
NO.
I/O‡
6
I
DESCRIPTION
System interrupt request. TI380C2x drives SIRQ to signal an interrupt request to the host processor.
SIRQ
H = No interrupt request
L = Interrupt request by TI380C2x
System memory address strobe. SAS is an active-low address strobe that is an output during DIO and
an input during DMA.§
SAS
2
I/O
H = Address not valid
L = Address is valid and a transfer operation is in progress
System read not write. SRNW serves as a control signal to indicate a read or write cycle.
128
I/O
H = Read Cycle
L = Write Cycle
† The TI380PCI SIF pin names correspond to a subset of the system interface pins on a TI380C2x. Consult the TI380C2x data sheet for more
information on individual pins. Like-named pins on the TI380PCI and TI380C2x system interfaces are intended to be connected to each other.
‡ I = in, O = out
§ The signal connecting this pin to the TI380C2x also should be connected to a 4.7-kW pullup resistor.
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7
ADVANCE INFORMATION
SRNW
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Pin Functions – Burned-In Address Emulation Interface†
PIN
NAME
NO.
I/O‡
MBLCK1
131
I
MADH00
MADH01
MADH02
MADH03
MADH04
MADH05
MADH06
MADH07
99
98
97
96
95
93
92
91
I/O
Local memory address, data, and status bus — high byte. For the first quarter of the local memory cycle,
MADH00 – MADH07 monitor address bits AX4 and A0 to A6; for the second quarter they monitor status
bits, and for the third and fourth quarters they carry data bits 0 to 7. The most significant bit is MADH00,
and the least significant bit is MADH07.
MBIAEN
19
I
Burned-in address enable. MBIAEN enables the output of data on the MADHxx lines during BIA
accesses.
MAX2
18
MAX0
9
DESCRIPTION
Local memory bus clock 1.
Local memory extended address bit. For the first quarter of a local memory cycle MAX2 monitors AX2.
For quarters two through four, MAX2 monitors A14.
I
ADVANCE INFORMATION
Local memory extended address bit. For the first quarter of a local memory cycle MAX0 monitors AX0.
For quarters two through four, MAX0 monitors A12.
8
I
MROMEN monitors the local memory bus ROM enable signal.
MROMEN
† The TI380PCI BIF pin names correspond to a subset of the local memory bus interface pins on a TI380C2x. Like-named pins on the two devices
are intended to be connected to each other. Consult the TI380C2x data sheets for more information on individual pins.
‡ I = in, O = out
8
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Pin Functions – PCI Interface
NO.
I/O†
DESCRIPTION
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
27
29
30
32
33
35
36
38
42
43
44
45
47
48
49
51
66
68
69
71
72
73
74
75
78
80
81
83
84
85
86
87
I /O
C/BE3
C/BE2
C/BE1
C/BE0
39
53
65
77
I /O
Bus command and byte enables. During the address phase of a transaction, C/BE3 – C/BE0 define the
bus command. During the data phase, C/BE3 – C/BE0 are used as byte enables. The byte enables are
valid for the entire data phase and they determine which byte lanes carry meaningful data. C/BE0
applies to the LSB and C/BE3 applies to the MSB.
DEVSEL
59
I /O
Device select. When DEVSEL is actively driven, it indicates the driving device has decoded its address
as the target of the current access. As an input, DEVSEL indicates whether any device on the bus has
been selected. If no PCI agent has asserted DEVSEL, then the TI380PCI shall remove itself as the
PCI bus master.
PCI address and data. A bus transaction to or from one of these pins consists of an address phase
followed by one or more data phases.
The address phase is the clock cycle in which FRAME is asserted. During the address phase
AD31 – AD00 contain a physical address (32 bits). For I / O, this is a byte address; for configuration and
memory it is a DWORD address. During data phases, AD07– AD00 contain the LSB, and AD31 – AD24
contain the MSB. Write data is stable and valid when IRDY is asserted, and read data is stable and
valid when TRDY is asserted. Data is transferred during those clocks where both IRDY and TRDY are
asserted.
FRAME
55
I /O
Cycle frame. FRAME is driven by the current master to indicate the beginning and duration of an
access.
It is asserted to indicate a bus transaction is beginning. While FRAME is asserted, data transfers
continue. When FRAME is deasserted, the transaction is in the final data phase.
GNT
25
I
Grant. GNT indicates to the TI380PCI that access to the PCI bus has been granted. This is a
point-to-point signal.
IDSEL
41
I
Initialization device select. IDSEL is used as a chip select during configuration read and write
transactions.
INTA
20
O
Interrupt A. INTA is used to request an interrupt. The assertion and deassertion of INTA is asynchronous to PCLK.
ADVANCE INFORMATION
PIN
NAME
† I = in, O = out
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9
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Pin Functions – PCI Interface (Continued)
PIN
NAME
NO.
I/O†
DESCRIPTION
IRDY
56
I /O
Initiator ready. IRDY indicates the bus master’s ability to complete the current data phase of the
transaction. If a data phase is completed on any clock, both IRDY and TRDY are sampled and asserted.
During a write, IRDY indicates that valid data is present on AD31 – AD00. During a read, it indicates the
master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted
together.
PCLK
23
I
Clock. PCLK provides timing for all transactions on the PCI bus. All other PCI signals, except RST and
INTA, are sampled on the rising edge of PCLK. PCLK is used to generate the SBCLK signal that goes to
the TI380C2x.
Parity error. PERR is for the reporting of data parity errors during all transactions. It is driven active by the
agent receiving data two clocks following the data when a data parity error is detected. The minimum
duration of PERR is one clock for each data phase that a data parity error is detected.
61
PERR
I/O
There are no special conditions when a PERR can be lost or when reporting of an error can be delayed.
An agent cannot report a PERR until it has claimed the access by asserting DEVSEL and completing a
data phase.
ADVANCE INFORMATION
REQ
26
O
Request. REQ indicates to the arbiter that TI380PCI desires use of the bus. REQ is a point-to-point signal.
Reset. RST is used to hard reset the LAN subsystem, including TI380C2x and the TI380PCI.
RST
21
I
SERR
62
I/O
System error. SERR, when enabled, reports address parity errors or any other system error where the
result is catastrophic. The assertion of SERR is synchronous to the clock and meets the setup and hold
times of all PCI signals.
STOP
60
I/O
Stop. STOP indicates the current slave is requesting the master to stop the current transaction.
I/O
Target ready. TRDY indicates the target agent’s (the TI380PCI) ability to complete the current data phase
of the transaction. If a data phase is completed on any clock, both TRDY and IRDY are sample asserted.
During a read, TRDY indicates that valid data is present on AD31 – AD00. During a write, it indicates that
the target is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted
together.
57
TRDY
To prevent AD, C/BE, and PAR signals from floating during reset, the central device can drive these lines
during reset (bus parking) but only to a logic low level; they can not be driven high.
† I = in, O = out
Pin Functions – Serial EEPROM Interface
PIN
NO.
I/O†
EDIO
111
I/O
EDC
122
O
NAME
DESCRIPTION
EEPROM data input / output is a bidirectional signal used to transfer data into or out of the EEPROM
memory. Note I2C memory devices typically require a pullup resistor to VCC on this line. This is an open
drain output. If the optional EEPROM is not present, EDIO should be tied high.
EEPROM clock signal used to synchronize all data in and data out of the memory. I2C memory devices
typically require a pullup resistor to VCC on this line. If the optional EEPROM is not present, EDC should
be tied low.
† I = in, O = out
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
architecture
The major blocks of the TI380PCI, illustrated in Figure 3, include the PCI interface (PCIIF ), TI380C2x interface
(SIF ), ROM interface (ROMIF ), serial EEPROM interface (EIF), and burned-in address emulation interface
(BIF). The functionality of each block is described in the following sections.
PCI interface (PCIIF)
The PCIIF block contains all logic needed to interact with the PCI bus and allows the TI380PCI to assume the
role of bus master or slave. This block controls all communication between the TI380PCI and the PCI bus. All
signals entering the PCIIF and generated within it are synchronous to the PCLK signal.
The TI380PCI also checks and generates parity for data presented on the PCI bus at the PCIIF.
The PCIIF generates and responds to the following PCI cycles:
TI380PCI RESPONDS TO:
Memory read line
I / O reads and writes
Memory write and invalidate
Configuration reads and writes
Memory write
All types of memory reads and writes
The TI380PCI asserts slave-initiated termination, if the initiator exceeds one data phase transfer.
address decode
The TI380PCI uses only the most significant 27 address bits presented in AD31 – AD00 to decode an access
directed at the TI380PCI for a TI380C2x DIO access, and the most significant 16 bits for a ROM access. The
TI380PCI’s base address selects a block of eight continuous 32-bit memory or I / O locations for DIO access or
64K bytes of address space for ROM access. Access to each register within the selected memory, I / O, or
configuration space is uniquely decoded. The decode logic returns DEVSEL as a medium device.
The PCIIF logic generates control signals that propagate either to configuration registers, the SIF, ROMIF, or
EIF within the TI380PCI. The address, command, and byte enables are valid and sustained throughout each
PCI cycle. Configuration registers can be accessed through configuration cycles when the TI380PCI’s address
is decoded.
address/ data parity checking and generation
The PCIIF is responsible for checking and generating parity for addresses during bus master operation and for
data during master and slave operations. If the PCIIF encounters SERR two PCLKs after the address phase
when it is mastering the PCI bus, it terminates its transaction immediately and regains control of the TI380C2x
SIF. If the PCIIF detects any address (even if not selected) or data parity (only when selected) while operating
as a PCI slave, or if it detects data parity while operating as a PCI bus master, it pulses PERR and sets bit 15
in the status register. Bus transactions causing the parity error are otherwise ignored by the LAN subsystem.
Any bus mastering transaction that encounters a parity error is aborted by the TI380PCI. This detection also
prevents future bus master cycles from occuring until a reset occurs.
The TI380PCI performs a bus master cycle when bus mastering is enabled and the TI380C2x requests the SIF
bus.
The supported PCI master cycles are:
D
D
D
Memory write
Memory read line
Memory write and invalidate
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11
ADVANCE INFORMATION
TI380PCI CAN GENERATE:
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
address/ data parity checking and generation (continued)
During PCI master cycles, PCIIF is able to handle the following:
D
D
D
Master-abort termination: due to no DEVSEL response
Slave-initiated termination: disconnect / retry and slave-abort
Parity error handling
TI380C2x interface (SIF)
The SIF handles all communications between the TI380C2x and the TI380PCI.
The TI2000 software standard† requires the TI380PCI SIF to include a configuration register at I / O address
0xE– 0xF. This is the same location as the TI380C2x DIO DMALEN register, therefore, access to the DIO
DMALEN register from the TI380PCI is masked, and the TI380PCI configuration register information is
presented instead.
ADVANCE INFORMATION
When there is no DIO access pending, the TI380PCI SIF acknowledges all SBRQ from the TI380C2x and allows
the TI380C2x to control the SIF bus. If the PCIIF initiates a DIO access while the TI380C2x is controlling the
SIF bus and is performing a DMA access, the SIF signals the TI380C2x to relinquish control of the SIF bus and
let the DIO proceed. On completion of the DIO cycle, the SIF logic again grants the SIF bus to the TI380C2x,
if the interrupted DMA sequence is not complete.
The interface between the TI380PCI and the TI380C2x operates in Motorola mode. The interface is designed
so it can operate with drivers that use 8- or 16-bit I/O instructions on the host. Accesses to the SIFDAT,
SIFDAT/INC, and SIFADR registers are ideally made with 16-bit I/O instructions from the host. If a driver has
to perform byte-accesses to these registers, then the odd byte must be accessed before the even byte.
Note that on Intel platforms the INSTR word and the OUTSTR word 16-bit I/O instructions use a little-endian
byte ordering that does not work without additional byte-swapping when used with the TI380PCI Motorola-mode
big-endian interface. These instructions are typically used only in 16-bit pseudo DMA drivers.
For more information on byte operations between the host and the TI380C2x, see the description of DIO
operations on pages 4-16 and 4-28 in the TMS380 Second Generation User’s Guide.
interrupt request
interrupting the PCI host
The SIF takes an SIRQ from the TI380C2x, sends it to the PCIIF, and the PCIIF then translates it into an INTA
on the PCI bus. The generation of INTA on the PCI bus is held off until the data in the TI380PCI FIFO has been
emptied. This interrupt is done to assure data coherency.
clearing the host interrupt request
Driver software running on the host can clear the SIRQ interrupt by writing a 0 to bit 8 of the SIFCMD register
in the TI380C2x. Writing a 1 to this location has no effect (see TI380C2x User’s Guide).
ROM interface (ROMIF)
The ROMIF supports remote program load for PCI LAN adapter cards. This interface supports a 64K-byte ROM
address range aligned on a 64K-byte boundary. Since the PCI bus can access the ROM in any byte order, the
ROMIF reads all 32 bits for each PCI ROM access. This latency is acceptable because the PCI bus does not
execute code out of the ROM. The ROM is normally accessed during system configuration with performance
is not critical. The ROMIF uses either 14 or 16 bits of the address depending on the setting of bit 17 in the
MISCCTRL register. In 14-bit mode, the ROMIF appends two bits to the most significant end of the address from
its internal page register. The TI2000† software standard requires that writes to the ROM location increment to
the next 16K pages and that the ROM pages be cycled through only once until the next reset. Note that ROMCS
does not go low when the host attempts to write to the EPROM.
† TI2000 software standard specification is available from your local TI Sales Office.
12
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
ROM interface (ROMIF) (continued)
When RST is driven high, the value on ROMA[07:00] is latched into the board configuration register in the
TI380PCI configuration space. The value on ROMA[07:00] can be provided by pullup and pulldown resistors
that do not affect operation after reset. This feature allows designers to support jumpers or board stuffing options
sensed by software that reads the board configuration register. If pullup and pulldown registers are not used,
the contents of the board configuration register are undefined after reset.
When the host computer initiates a 32-bit read to the ROMIF, the TI380PCI fetches four bytes from the ROM
and presents the resulting 32-bit DWORD to the PCI bus. The fetches from the ROM start with the least
significant byte, byte 0, followed by bytes 1, 2, and 3. The data is presented to the PCI data bus as shown in
Figure 4.
TI380PCI PCI DATA BUS PINS
AD24 AD23
AD16 AD15
BYTE 3
ROMA00
BYTE 2
ROMA00
ROMA07
AD08 AD07
BYTE 1
ROMA00
ROMA07
AD00
BYTE 0
ROMA00 ROMA07
ROMA00
TI380PCI ROM DATA BUS PINS
Figure 4. PCI Bus Data
The ROMIF has been designed for operation with EPROM devices with 100 ns access times.
serial EEPROM interface (EIF)
The TI380PCI includes an interface for an optional I2C serial EEPROM. The EEPROM contains the following:
D
D
D
D
D
D
Bytes 0 × 0 – 0 × 7 contain eight bytes of PCI configuration information that automatically are loaded into
the appropriate PCI configuration register by the 380PCI at power on.
Byte 0 × 8 is a checksum calculated on bytes 0 – 7. This checksum byte automatically is read at power on
by the TI380PCI. If the checksum read from byte 8 does not agree with the checksum that the 380PCI
calculated from bytes 0 – 7, then the 380PCI sets the ECRCERR and NEP bits in the EEPROM read/write
register in 380PCI configuration space.
Bytes 0 × 09 – 0 × 10 contain the six bytes of the BIA and two bytes of BIA checksum. The 380PCI reads
these bytes and stores them in an internal register, the contents of which are presented to TI380C2x local
memory bus when the TI380PCI detects an access to the BIA. In this way the TI380PCI emulates the
presence of a BIA ROM on the TI380C2x local memory bus. Note that the TI380PCI does not verify the BIA
checksum.
Byte 0 × 11 is reserved for use by TI2000 drivers. This byte is not read automatically by the TI380PCI, but
it is read by TI2000 drivers that load bit 0 from this byte into the TI380PCI MISCCTRL register bit 8 and load
bit 1 from this byte into TI380PCI MISCCTRL register bit 9. This byte allows the TI2000 driver to read the
network speed and topology from nonvolatile memory before attempting to access the network.
Bytes 0 × 12 – 0 × 20 are reserved for future use by the TI380PCI.
Bytes 0 × 21 – 0 × FF are available for user-defined variable storage.
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13
ADVANCE INFORMATION
AD31
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
serial EEPROM interface (EIF) (continued)
The user can program several copies of the BIA into the EEPROM user-defined space as a protection against
inadvertent modification of the copy of the BIA at addresses 0x08 – 0x0F.
Table 1. EIF Configuration Registors
PARAMETER DESCRIPTION
ADVANCE INFORMATION
EEPROM BYTE ADDRESS
DEFAULT VALUE
Vendor ID least significant byte
0x00
0x4C
Vendor ID most significant byte
0x01
0x10
Device ID least significant byte
0x02
0x08
Device ID most significant byte
0x03
0x05
Revision ID
0x04
0x10
Sub-class
0x05
0x80
Min_Gnt
0x06
0x01
Max_Lat
0x07
0x00
Checksum
0x08
0x7A
Burned-in address
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
BIA MSbyte
BIA byte
BIA byte
BIA byte
BIA byte
BIA LSbyte
BIA MS checksum
BIA LS checksum
TI2000 reserved byte
0x11
0x01
Reserved for future use
0x12 ... 0x20
Reserved
User defined
0x21 ... 0xFF
User defined
Systems that do not use an EEPROM should tie the EDC pin low and the EDIO pin high. This action causes
default values to be loaded into the configuration registers as shown in Table 1. EDC and EDIO are sampled
at the deassertion of RST. If EDC is low and EDIO is high at the deassertion of reset, the TI380PCI assumes
that no EEPROM is present in the system.
The default values for the parameters stored in the EEPROM can always be accessed by software because
copies of these values are stored in a series of hardwired registers in the TI380PCI configuration space. These
registers are read only and are unaffected by the process of loading data from the optional EEPROM.
The algorithm that should be used to generate the cyclic redundancy check (CRC) code placed in the serial
EEPROM byte 08 is included here. When the TI380PCI reads the EEPROM after power up, it checks the CRC
in byte 08 to ensure that it was generated with this algorithm. If the CRC from byte 08 of the EEPROM does
not match the CRC calculated from EEPROM bytes 0 – 7, then the TI380PCI sets the NEP and ECRCERR bits
in the EEPROM read/write register. When the NEP and ECRCERR bits are set owing to a CRC mismatch on
the data read from the EEPROM, the TI380PCI still continues to load the data read EEPROM into the PCI
configuration registers. Note that in the event that the EEPROM is unprogrammed, the TI380PCI configuration
registers may be left in an unknown state. In such a case, the EEPROM can be initialized by using PCI BIOS
calls to read the hardwired configuration register addresses associated with each PCI slot. The slot containing
the TI380PCI responds with the contents of the hardwired registers. Once the slot containing the TI380PCI has
been identified, the EEPROM can be programmed using the EEPROM register in the PCI configuration space.
After the next power cycle the TI380PCI loads the contents of the initialized EEPROM.
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
serial EEPROM interface (EIF) (continued)
Input MSB to LSB >>
LS
XOR
on each clock
MS
CRC MSB to LSB >>
LS
CRC SEED = 10101010
It is assumed that data in the serial EEPROM is shifted LSB to MSB, consistent with other serial communication
streams.
unsigned short xor-crc (unsigned short
{
*msb, int bytes)
BYTE crc=0xaa; // seed
int i;
for (i=0; i<bytes; i++)
crc^=msb[i];
return (crc);
}
The BIA downloaded from the EEPROM ultimately appears in the adapter RAM at chapter 0, address 0. The
high or odd byte of each 16-bit word contains two hex digits of the 12-digit BIA, the most significant digit first.
The last two high bytes of the first eight 16-bit words contain the 16-bit checksum of the BIA. The checksum
is performed as shown below.
example:
Here is an adapter RAM memory dump for a card with BIA = 0001fafe1093.
Address
000000
Data
: 0000 0100 fa00 fe00 1000 9300 0b00 9200
Address
Data
01
03
05
07
09
0b
0c
0d
00
01
fa
fe
10
93
0b
92
Checksum
0001
fafe
+ 1093
_____
(1) 0b92
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15
ADVANCE INFORMATION
This is the routine that calculates the Serial EEPROM CRC over the first eight bytes of the EEPROM. The return
value is written to the ninth byte of the EEPROM. The “MSB” argument passed is a copy of the bytes read from
the EEPROM and stored in an array. Note that the BIA has its own checksum, which is not verified by the
TI380PCI.
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
serial EEPROM interface (EIF) (continued)
HARDWIRED REGISTER NAME
(CONTAINS READ-ONLY COPY
OF DEFAULT VALUE)
REGISTER ADDRESS IN TI380PCI
CONFIGURATION SPACE
Vendor ID
Hardwired vendor ID
4C
Device ID
Hardwired device ID
4C
Revision ID
Hardwired revision ID
50
Hardwired subclass
50
Min_Gnt
Hardwired Min_Gnt
50
Max_Lat
Hardwired Max_Lat
50
PARAMETER DESCRIPTION
Subclass
The EEPROM also can be read and written under software control by PCI configuration register 0x48. A typical
I2C EEPROM that can be used with the TI380PCI is the 24C02. EEPROMs that provide external address pins
for identification of several devices on the I2C bus should have these address pins pulled down to logic 0.
ADVANCE INFORMATION
burned-in address interface (BIF)
The BIF logic is designed to connect directly to the local memory bus of the TI380C2x. The BIF serves two
purposes:
D
D
Snoops the status cycles on the local memory bus to detect the initialization and completion of DMA
transfers from the TI380C2x.
Detects accesses to the BIA ROM from the TI380C2x. During a BIA access, the TI380PCI drives data onto
MADH00– 07, emulating a BIA PROM. This eliminates the need for a separate BIA PROM.
in-circuit test NAND tree operation
The terminal function table in this data sheet explains how to use the ICT pins on the TI380PCI to place the
output pins of the TI380PCI in a 3-state mode to allow for in-circuit testing of a PCB.
The TI380PCI also contains a NAND tree that can be used during the in-circuit testing process to verify the
integrity of the solder connections to the TI380PCI. The NAND tree is activiated by latching a control value on
the SADL0–7 pins on the rising edge of the signal applied to the ICT pin.
To activate the NAND tree:
1. Drive and hold ICT low.
2. Drive and hold the MAX0 input low and drive the MAX2 input high. Drive and hold the SADL0–7 pins as
follows:
SADL7
SADL6
SADL5
SADL4
SADL3
SADL2
SADL1
SADL0
0
0
0
0
0
0
1
0
3. While holding the values in step 2, pull the ICT input high to latch the values from step 2.
The connections to the TI380PCI can now be tested with the NAND tree. The NAND tree can be deactivated
by repeating steps 1 through 3 with the data applied to the SADL0–7 pins in step 2 set as follows:
16
SADL7
SADL6
SADL5
SADL4
SADL3
SADL2
SADL1
SADL0
0
0
0
0
0
0
0
0
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
TI380PCI device operation
TI380PCI behavior as a PCI bus target
The PCIIF in the TI380PCI acts as an I/O slave to the PCI bus after power up and when the LAN subsystem
is not the PCI bus master. It monitors and decodes PCI commands for memory, I/O, and configuration accesses.
Enabling of memory and I/O accesses are performed by setting and cleaning bits in the COMMAND register.
TI380PCI behavior as a PCI bus master
If the access is a read access, the TI380PCI acknowledges the request and latches the DMA address. It then
initiates a read access on the PCI bus. If the DMA length exceeds the cache line size, as defined by the contents
of the TI380PCI cache line size configuration register, then the read access on the PCI bus is a burst read. As
data is available from the PCI bus, it is provided to the TI380C2x. Since the PCI bus has a higher bandwidth
than the TI380C2x SIF bus, the 64-byte FIFO in the TI380PCI fills as the burst read continues. If the FIFO fills
before the DMA length is reached, the PCI master relinquishes the bus until the FIFO is almost empty.
If a DIO conflict occurs while the DMA is in progress, the TI380PCI forces the TI380C2x off the SIF bus to allow
the DIO to complete. The DMA operation resumes at the point it was interrupted and continues until completion.
removal of TI380PCI as bus master
The TI380PCI is removed as the PCI bus master under two conditions:
D
D
target-inititiated retry and/or termination
master-initiated termination as no PCI agent asserted DEVSEL.
TI380PCI behavior on the SIF bus
SIF behavior as a SIF master
The TI380PCI SIF logic masters the TI380C2x system interface to translate signals from the PCIIF into
TI380C2x control signals and relays TI380C2x return signals to the PCIIF.
SIF behavior as a slave
The SIF acts as a slave when the TI380C2x is engaged in DMA operations. During DMA transfers, other PCI
masters can access the TI380C2x’s DIO registers. The TI380PCI retries all accesses from the PCI bus while
posting a preempt to the TI380PCI SIF. When the TI380PCI SIF receives the preempt, it signals the TI380C2x
to relinquish the SIF bus at the earliest opportunity and does not grant the TI380C2x the SIF bus until the
preempt is removed.
FIFO control
The 64-byte FIFO serves to reduce the bandwidth demand on the PCI bus from the TI380PCI. It is used only
when the TI380C2x is functioning as a PCI bus master during DMA accesses.
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17
ADVANCE INFORMATION
The TI380PCI requests to become a master on the PCI bus after the TI380C2x initiates a DMA transfer to the
TI380PCI. The TI380C2x begins a DMA series by asserting SBRQ and requesting its own system interface bus.
The TI380PCI performs a DIO access to the TI380C2x and reads the DMA length before granting the SIF bus
to the TI380C2x. (Note that the read cycle occurs only on the first transaction of the DMA access). If the
TI380C2x has requested DMA write access and no DIO access from the PCI bus is pending, the TI380PCI
acknowledges the request and latches the DMA address and completes the write cycle from the TI380C2x to
start filling the FIFO. Subsequent writes continue to fill the FIFO. When the FIFO contains 60 bytes of data, the
PCIIF logic arbitrates for the PCI bus and transfer the data in a burst sequence.
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
FIFO operation (write cycles)
The TI380PCI BIF snoops the status cycles on the TI380C2x local bus. When the TI380PCI detects a status
code that indicates the start of a DMA write from the TI380C2x to the host computer, the TI380PCI immediately
initiates a DIO read of the DMALEN register in the TI380C2x. When the DMALEN register has been read, the
TI380PCI grants the TI380C2x control of the SIF bus and the DMA write can proceed.
The DMALEN register is not read again until the next DMA transaction starts. During DMA write cycles from
the TI380C2x, the TI380PCI stores one cache line in the FIFO before requesting the PCI bus. It drives data on
the PCI bus as long as it has sufficient data in the FIFO or until it loses the PCI bus. The FIFO control requests
the PCI bus under the following conditions:
D
D
ADVANCE INFORMATION
D
A full cache line is available for writing and the DMA address is aligned on a cache boundary. The PCI bus
cycle is a write-and-invalidate cycle.
The TI380C2x relinquishes control of the SIF bus owing to completion of a DMA write from the TI380C2x
with DMA data in the TI380PCI FIFO. If the quantity of data in the TI380PCI FIFO is greater than or equal
to the cache line size and the DMA address is aligned on a cache line boundary, the PCI cycles are
write-and-invalidates. If the quantity of data in the TI380PCI FIFO is less than the cache line size or the DMA
address is not aligned on a cache line boundary, the PCI cycles are memory writes.
A full 32-bit word is available for the PCI bus and the cache line size is zero.
If the host attempts a DIO access during a DMA transfer between the TI380C2x and the host, the TI380PCI
signals the TI380C2x to pause the DMA transfer. When the TI380PCI regains control of the SIF bus, the DIO
access from the host is allowed to complete, and then the TI380PCI allows the DMA transfer to restart and run
to completion. Note that the TI380PCI signals the host to retry the DIO access until the TI380PCI gains control
of the SIF bus and can allow the DIO access to complete. In the case of a DMA write from the TI380C2x to the
host (which is almost complete), the TI380PCI can give up control of the SIF bus prior to transferring the last
data from the FIFO to the host. If the host initiates a DIO access at this time, the DIO access is allowed to
complete immediately, i.e., before the FIFO empties.
FIFO operation (read cycles)
The TI380PCI BIF snoops the status cycles on the TI380C2x local bus. When the TI380PCI detects a status
code that indicates the start of a DMA read by the TI380PCI from the host computer, the TI380PCI immediately
initiates a DIO read of the DMALEN register in the TI380C2x. When the DMALEN register has been read, the
TI380PCI grants the TI380C2x control of the SIF bus, and the DMA read can proceed. The DMALEN register
is not read again until the next DMA transaction starts. The TI380PCI then requests the PCI bus and begins
filling the FIFO. As data is available, it is provided to the TI380C2x. The TI380PCI counts the bytes received
from the PCI bus and decrements its DMA length counter. If the DMA count is not zero, but the TI380C2x
releases the SIF bus, the TI380PCI continues to read data from the PCI bus. The TI380PCI logic terminates
the PCI ownership when the DMA count goes to zero.
The TI380PCI always performs memory-read line commands on the PCI bus regardless of DMA count or
address alignment.
BIA interface
On power up, BIA data is loaded from the EEPROM and held in registers inside the TI380PCI. All the pins on
the local bus of the TI380C2x necessary to sense an access from the TI380C2x to an attached BIA ROM are
connected to the TI380PCI. When the TI380PCI senses an access to the BIA ROM, it drives the BIA data onto
the MADHxx bus, simulating the presence of a BIA ROM on the TI380C2x local bus.
18
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
TI380PCI registers
The TI380PCI supports a number of registers to facilitate communications between the host computer and the
token-ring LAN subsystem. It also performs address translation to map TI380C2x DIO registers into host
computer memory or I / O space. Table 2 describes the configuration space registers implemented within the
TI380PCI. The registers shown as shaded are autoloaded from an external serial EEPROM at power up.
Table 2. Configuration Space Header
BYTE 3
BYTE 2
BYTE 1
BYTE 0
READ/WRITE
0x00
Device ID
Vendor ID
R
0x04
Status
Command
R/W
0x08
Base-Class
0x0C
Sub-Class
Header Type
Latency Timer
Revision ID
R
Cache Line Size
R/W
0x10
Base Address I/O
R/W
0x14
Base Address Memory
R/W
0x18
Reserved (returns 0)
R
0x1C
Reserved (returns 0)
R
0x20
Reserved (returns 0)
R
0x24
Reserved (returns 0)
R
0x28
Reserved (returns 0)
R
0x2C
Reserved (returns 0)
R
0x30
Expansion ROM Base Address
R/W
0x34
Reserved (returns 0)
R
0x38
Reserved (returns 0)
R
0x3C
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
R/W
0x40
Miscellaneous Control (MISCCTRL) Register
R/W
0x44
Board Config Register
R
0x48
Reserved (returns 0)
EEPROM
R/W
0x4C
Hardwired DEVICE ID
Hardwired VENDOR ID
R
0x50
H/W Subclass
H/W Max Lat
H/W Min Gnt
0x54
380PCI Interface Control Register
0x58–0xFF
Reserved (returns 0 when read)
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H/W Revision ID
ADVANCE INFORMATION
DWORD ADDRESS
R
R
19
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
device identification
The TI380PCI contains the following device identification information in its configuration space.
REGISTER
Device ID
HEX VALUE
†
104Ch
0508h†
Revision ID
01
Header type
00
Class code
028000
Vendor ID
† These values are defaults and can be overwritten by the
contents of the optional EEPROM.
COMMAND register—configuration space DWORD address (0x04)
15
10
Reserved
9
0
8
7
0
6
5
4
3
2
1
0
0
ADVANCE INFORMATION
Fast Back-to-Back Enable
SERR Enable
Wait Cycle Control
Parity Error Response
VGA Palette Snoop
Memory Write and Invalidate Enable
Special Cycles
Bus Master
Memory Space
I / O Space
Figure 5. Command Register Layout
The COMMAND register provides coarse control over the TI380PCI’s ability to generate and to respond to PCI
cycles. When 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses
except configuration accesses.
The COMMAND register is set to 0 at power up and after hardware reset.
Bit 00: Controls TI380PCI’s response to I / O space accesses. A value of 0 disables TI380PCI’s response. A
value of 1 allows TI380PCI to respond to I / O space accesses.
Bit 01: Controls TI380PCI’s response to memory space accesses. A value of 0 disables TI380PCI’s response.
A value of 1 allows TI380PCI to respond to memory space accesses.
Bit 02: Controls TI380PCI’s ability to act as a master on the PCI bus. A value of 0 disables TI380PCI from
generating PCI accesses. A value of 1 allows the TI380PCI to behave as a bus master. Note that if the automatic
software reset bit in the 380PCI interface control register (0x54) is set to a one then the action of clearing the
bus master bit of the 380PCI command register from one to zero also resets the TI380PCI.
Bit 03: CONTROL[3] allows the LAN subsystem to enter low-power mode following a shutdown broadcast. All
other special cycle messages are ignored. Device drivers must reinitialize and download micro code to the LAN
subsystem when the subsystem exits low-power mode.
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
COMMAND register—configuration space DWORD address (0x04) (continued)
Bit 04: CONTROL[4] controls memory write-and-invalidate cycles. A value of 1 enables the TI380PCI to
generate memory write-and-invalidate cycles.
Bit 05: CONTROL[5] applies to VGA subsystems and is hardwired to 0.
Bit 06: This bit controls the TI380PCI’s response to parity errors. When this bit is set, the TI380PCI takes its
normal action when a parity error is detected. When this bit is reset, the TI380PCI ignores any parity errors that
it detects and continues normal operation. This bit is set to 0 after reset.
Bit 07: CONTROL[7] is hardwired to a 0 since the TI380PCI does not support address / data stepping.
Bit 08: This bit is an enable bit for the SERR driver. A value of 0 disables the SERR driver and a value of 1
enables it. This bit’s state after RST is 0.
Bit 09: CONTROL[9] is hardwired to a 0 since the TI380PCI does not support fast back-to-back transaction to
different devices.
ADVANCE INFORMATION
Bits 10 – 15: Reserved. These reserved bits read as 0.
STATUS register—configuration space DWORD address (0x04)
15 14 13 12 11 10
0
9
8
1
7
0
6
0
Reserved
Fast Back-to-Back Capability
Data Parity Detection
DEVSEL Timing
00 – Fast
01 – Medium
10 – Slow
Signal Target Abort
Receive Target Abort
Receive Master Abort
Signal System Error
Detect Parity Error
Figure 6. Status Register Layout
The STATUS Register records status information for PCI bus-related events. Reads to this register behave
normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register
is written, and the data in the corresponding bit location is a 1.
Bits 0 – 6: Reserved
Bit 7: STATUS[7] is hardwired to a 0 as the TI380PCI does not support fast back-to-back cycles as a slave.
Bit 8: This bit is set when three conditions are met: 1) the PCI device asserted PERR itself or observed PERR
asserted; 2) the device setting the bit acted as the bus master for the operation in which the error occurred; 3) the
parity error response bit (command register) is set.
Bits 9 – 10: DEVSEL timing for the TI380PCI is set to 01 (medium).
Bit 11: This bit is set whenever TI380PCI terminates a transaction with slave-abort.
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21
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
STATUS register—configuration space DWORD address (0x04) (continued)
Bit 12: This bit is set whenever TI380PCI’s transaction is terminated with slave-abort.
Bit 13: This bit is set whenever TI380PCI’s transaction is terminated with master-abort.
Bit 14: This bit is set whenever TI380PCI asserts SERR.
Bit 15: This bit is set by TI380PCI whenever it detects a parity error, even if parity-error handling is disabled
(as controlled by bit 6 in the command register).
board configuration register (Board Config)—configuration space DWORD address (0x44)
31
0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
0
Figure 7. Board Configuration Register
ADVANCE INFORMATION
Bits 08 – 31: These bits must read as 0.
Bits 00 – 07: When RST is driven high, the value on ROMA[07:00] is latched into the board configuration register
in the TI380PCI configuration space. The value on ROMA[07:00] can be provided by pullup and pulldown
resistors that do not affect operation after reset. This feature allows designers to support jumpers or
board-stuffing options that can be sensed by software that reads the board configuration register. If pullup and
pulldown registers are not used, the contents of the board configuration register are undefined after reset.
miscellaneous functions
cache line size (CLS)—configuration space DWORD address (0x0c)
The CLS register is loaded with the host system data cache line size. On reset, it is set to 0. The value in this
register controls the TI380PCI FIFO fill / flush algorithm. The value in this register should be a power of two that
is greater than or equal to 4, or a sum of those powers of two.
latency timer (LT)—configuration space DWORD address (0x0C)
The TI380PCI supports burst data transfer on the PCI bus; therefore, a latency timer register is needed as
defined in the PCI specification.
built-in self-test (BIST)—configuration space DWORD address (0x0C)
The TI380PCI does not support built-in self-test and returns 0 when the BIST register is read.
base address register (BASE0)—configuration space DWORD address (0x10)
31
Base Address
4
3
2
1
0
0
0
0
0
1
Reserved
I / O Space Indicator
Figure 8. Base Address Register for I / O
The TI380PCI supports only one I / O address range decoded down to eight continuous 32-bit locations. After
reset, the value of the address map is set to 0x1. Bits 0 – 4, are read only as 0x1. The LAN subsystem is expected
to reside in I / O space under normal operations for conformance with the TI2000 software specification.
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
base address register (BASE1)—configuration space DWORD address (0x14)
31
4
Base Address
0
3
0
2
1
0
0
0
0
Prefetchable
Type
Memory Space Indicator
Figure 9. Base Address Register for Memory
interrupt line—configuration space DWORD address (0x3C)
TI380PCI uses a PCI bus interrupt so this register is implemented as an 8-bit read / write register. The value after
reset is 0x00. The least significant four bits are passed to the MISCCTRL register and the TI2000 configuration
register.
interrupt pin—configuration space DWORD address (0x3C)
This is hardwired to 0x01 indicating INTA is used as the interrupt pin.
maximum latency (Max_Lat)—configuration space DWORD address (0x3C)
The TI380C2x has a larger than 1-Kbyte buffer for storing network data; thus, at the maximum network data
rate of 16 Mbps, the TI380C2x can be serviced at intervals greater than 64 µs. This register is loaded with a
value from the EEPROM. If no EEPROM is present, the register is loaded with 0x00.
minimum grant (Min_Gnt)—configuration space DWORD address (0x3C)
This register is loaded with a value from the EEPROM. If no EEPROM is present, the register is loaded with
0x01.
expansion ROM base address register (BASEROM)—configuration space DWORD address (0x30)
11 10
31
Expansion ROM Base Address
(Upper 21 Bits)
1
0
Reserved
Address Decode Enable
Figure 10. Expansion ROM Base Address Register Layout
The TI380PCI supports an RPL expansion ROM on a PCI bus add-in card. This register is used to configure
the location of the expansion ROM. The BASEROM supports address alignment on a 64Kbyte boundary.
Bits 16 – 31 and bit 0 of BASEROM are read / write, the rest are read only as 0x0. TI380PCI supports 64Kbyte
ROM. Bit 0 is intended to be set by the host.
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ADVANCE INFORMATION
The TI380PCI supports only one memory address range decoded down to eight continuous 32-bit locations.
After reset, the value of the address map is set to 0x0. Bits 0 – 4 are read only as 0x0. The LAN subsystem is
expected to reside in I / O space under normal operations for conformance with the TI2000 software, indicating
that this register is not utilized.
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
subsystem-specific registers
The TI380PCI contains the following registers in addition to the PCI-prescribed registers.
miscellaneous control register (MISCCTRL)—configuration space DWORD address (0x40)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DMA Channels
INT
Speed and
Topology
CONNECTOR
Reserved
Sleep
ADVANCE INFORMATION
Expansion ROM
Address Mode
Reserved
SBCLK Divide
Ratio
Reserved
Address Parity
Error
Target Reported
Parity Error
Retry Count
Expired
Software Reset
Figure 11. Miscellaneous Control Register
The MISCCTRL is a collection of LAN subsystem control functions. The value of the bit fields in this register
after reset are as indicated.
Bits 0 – 3: DMA channels: DMA channel has no meaning in a PCI context. These four bits also appear in the
TI2000 configuration register where they select between bus master DMA operation and pseudo-DMA
operation as defined by the TI2000 software specification. When this field has the value zero, a TI2000 driver
should operate in pseudo-DMA mode. When the field is nonzero, a TI2000 driver should operate in bus master
DMA mode.
Bits 4 – 7: The four INT bits indicate the interrupt level. At reset, these bits are set to 0x0. They are read only
and echo the least significant bits of the Interrupt Line Register.
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
miscellaneous control register (MISCCTRL)—configuration space DWORD address (0x40) (continued)
Bits 8 – 9: Speed and topology. These bits are echoed in bits 8 – 9 of TI2000 configuration registers. At reset,
these bits are set to 0x1.
SPEED BIT 9
TOPOLOGY BIT 8
0
0
Full-duplex Ethernet
DESCRIPTION
1
0
Ethernet
0
1
Token Ring 16 Mbps
1
1
Token Ring 4 Mbps
Bit 10: The CONNECTOR bit indicates the connector in use: TI2000 drivers do not currently use this bit;
however, it must always read as 0 if it is not implemented in adapter logic. The value of this bit is presented on
pin DB9 / UTP of the TI380PCI. Upon reset, this bit is 0.
Bits 11 – 15: Reserved and is read as 0x9.
Bit 16: Sleep. Setting this bit to a 1 causes the SBCLK and output from the TI380PCI to be driven to a steady
high state. SBCLK is used as SBCLK for the TI380C2x, holding it high causes the TI380C2x to suspend
operations and go into power-saving mode. When this bit changes from a 1 to 0, the SBCLK returns to normal
operation. This bit is set to 0 on reset.
Bit 17: Expansion ROM address mode, 14/ 16. This bit indicates to the ROMIF that it should either use full 16-bit
addressing or support the TI2000 paging protocol. When using TI2000 paging, the ROMIF uses the least
significant 14 bits of the 16-bit ROM address and the most significant two bits are provided by an internal
TI380PCI page register. This bit is set to 0x0 after reset, indicating full 16-bit mode.
Bit 18: This bit is reserved and is set to zero during reset by the TI380PCI. This bit is read as zero and should
always remain set to zero.
Bits 19 – 20: SBCLK divide ratio. These bits specify the relationship between the PCI clock and the TI380C2x’s
SBCLK. After reset, these bits are set to 0x1.
BIT 20
BIT 19
SBCLK FREQUENCY
0
0
PCLK / 1
0
1
PCLK / 2
1
0
PCLK / 3
1
1
PCLK / 4
Bits 21 – 27: Reserved
Bit 28: Address Parity Error is set to 1 when the TI380PCI detects an address-parity error when acting as a PCI
slave. This bit is set to 0 after reset.
Bit 29: Target Reported Parity Error is set to 1 when the TI380PCI receives a data parity error (that is, receives
PERR during a master write and / or detected a parity error during master read). This bit is set to 0 after reset.
Bit 30: Retry Count Expired is set to 1 when the TI380PCI has exceeded the maximum retry count with a master
transaction. This bit is set to 0 after reset.
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25
ADVANCE INFORMATION
1 = D-Shell (AUI or DB9 )
0 = UTP /10BaseT
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
miscellaneous control register (MISCCTRL)—configuration space DWORD address (0x40) (continued)
Bit 31: Software Reset is a programmable reset. Setting this bit to a 1 causes the SRESET output to pulse low
for a minimum of 14 µs and results in a hard reset to the LAN subsystem. (This function is provided primarily
for hardware and driver-software debug purposes.) This bit is set to 0 after reset. When set to 1, this bit resets
itself to 0 after four PCI clock cycles.
EEPROM read / write register (0 × 48)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
ECRCERR
NEP
ECLK
EEN
EDATA
rsvd
rsvd
rsvd
rsvd
ADVANCE INFORMATION
Bit 8
ECRCERR
EEPROM CRC error detected. This bit is normally 0 but is set to a 1 if an error is detected in the CRC read from
the EEPROM at power up. If this bit is set, the TI380PCI also sets bit 7, the NEP bit.
Bit 7
NEP
EEPROM not present. This bit indicates that the EEPROM interface was disabled either by a pulldown resistor on
the EDIO pin or by the detection of an error in the checksum during the EEPROM download process.
Bit 6
ECLK
EEPROM SIO Clock: This bit controls the state of the EDC pin.
1 = pin high
0 = pin low
Bit 5
EEN
EEPROM enable: This bit controls the direction of the EDIO pin. When this bit is set to a 1, the EDIO pin is driven
with a value in the EDATA bit.
Bit 4
EDATA
EEPROM data: This bit is used to read or write the EDIO data pin on the EEPROM. When bit 5 is a 1, the
EEPROM data pin is driven with the value of this bit. If bit 5 is a 0, this bit is driven by the level on the EEPROM
EDIO data pin.
380PCI interface control register —configuration space DWORD address (0x54)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bits 0 – 15
Reserved; may not
be read as zero.
Bit 16
Automatic
Software Reset
Bits 17 – 31
Reserved; may not
be read as zero.
Figure 12. Interface Control Register
Bits 0 – 15: Reserved may not read as zero.
Bit 16: The automatic software reset controls the impact of writing a zero to the bus master bit (bit 2) in the
TI380PCI command register 0x04. When this bit is set to zero, the TI380PCI resets itself if the host processor
causes a transition from one to zero of the bus master bit. When bit 16 is set to one, the TI380PCI does not reset
itself when the host processor causes a transition from one to zero of the master bus.
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
380PCI interface control register—configuration space DWORD address (0x54) (continued)
Typically, in personal computer (PC) systems the TI380PCI automatic software reset bit is set to a default value
of zero. In a PC system, when a CTRL-ALT-DEL is issued from the keyboard, the PCI bus does not receive a
reset. A TI380PCI bus master in the middle of a DMA transaction when the CTRL-ALT-DEL is issued can be
left in an unknown state. In this condition, the bus master could perform unexpected memory accesses to the
host after the TI380PCI device is enabled by the PCI BIOS during the boot process.
To eliminate this problem, the automatic software reset bit should be left set to the default value of zero. The
action of clearing the bus master bit in the TI380PCI control register (which is a direct consequence of issuing
the CTRL-ALT-DEL) also automatically resets the TI380PCI and clears any pending DMA transactions. The
reset induced by clearing the TI380PCI bus master bit is the same as the software reset that takes place when
bit 31 of the TI380PCI MISCCNTRL register is set to a one.
Bits 17 – 31: Reserved may not read as zero.
TI380C2x interface configuration register (TI2000)
This is a READ ONLY register with the following functions:
CONFIG bit 15: The most significant bit of the configuration register, when set, indicates the existence of the
configuration register. This bit is hardwired to 1, to indicate the presence of a configuration register.
CONFIG=1
CONFIG=0
There is a configuration register.
There is no configuration register.
RESERVED bits 13 – 14: These bits must read as 0.
DEDMACTL bit 12: The Don’t Enable ISA DMA Controller (DEDMACTL) bit indicates whether the TI2000 driver
must enable the ISA DMA controller. The ISA DMA controller is not used to control operations on the PCI bus.
In order to allow the TI2000 software specification to be expanded to comprehend the PCI bus, this bit is
hardwired to a 1 to indicate that a TI2000 driver controlling a PCI-based network interface card should not enable
an ISA DMA controller. (The setting of this bit does not affect DMA on the PCI bus.)
DMA MODE
DEDMACTL BIT VALUE
DMA
1 = Driver must NOT enable ISA DMA controller
DMA
0 = Driver must enable ISA DMA controller
PDMA
x = Driver must NOT enable ISA DMA controller
INST8 bit 11: This bit indicates whether the driver can use 16-bit instructions to access the adapter registers.
This bit is hardwired to 0 because PCI-based machines are able to perform 16-bit instructions.
1 = The TI2000 driver must use 8-bit instructions to access the LAN adapter registers.
0 = The TI2000 driver can use 16-bit instructions to access the LAN adapter registers.
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ADVANCE INFORMATION
The TI380PCI contains the following register which is defined in I / O space.
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
TI380C2x interface configuration register (TI2000) (continued)
CONNECTOR bit 10: The CONNECTOR bit indicates the connector in use: TI2000 drivers do not currently use
this bit; however, it must always read as 0 if it is not implemented in adapter logic. The value of this bit is
presented on pin DB9 / UTP of the TI380PCI. Upon reset, this bit is 0. This bit echoes bit 10 of the MISCCNTL
register.
1 = D-Shell (AUI or DB9)
0 = UTP / 10BaseT
SPEED bit 9: Indicates whether the driver must initialize 4- or 16-Mbps token-ring operation. See TOPOLOGY
bit 8.
TOPOLOGY bit 8: Indicates whether the driver must initialize token-ring or Ethernet operation.
TI2000 drivers interpret the speed and topology bits together to determine whether to initialize the adapter under
4- or 16-Mbps token-ring, or 10-Mbps Ethernet operation:
ADVANCE INFORMATION
SPEED BIT 9
TOPOLOGY BIT 8
0
0
Reserved
DESCRIPTION
1
0
Ethernet
0
1
Token Ring, 16 Mbps
1
1
Token Ring, 4 Mbps
These two bits echo bits 8 and 9 in the MISCCNTL Register.
INT bits 4 – 7: The four INT bits indicate the interrupt level. At reset these bits are set to 0x0. These bits echo
the LSBs of the Interrupt Line Register.
7
6
5
4
INTERRUPT LEVEL
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
.
.
.
.
...
1
1
1
1
15
DMA bits 0 – 3: The four DMA bits indicate the DMA channel. At reset, these bits are 0x0. They are used by
TI2000-compatible software, and the channel number has no meaning in terms of PCI bus DMA. However,
TI2000 drivers read this field, and if it is set to 0, they operate in pseudo-DMA mode. Any other value allows
TI2000 drivers to use PCI DMA operation.
28
3
2
1
0
DMA CHANNEL
0
0
0
0
DMA bus master
0
0
0
1
DMA bus master
0
0
1
0
DMA bus master
.
.
.
.
DMA bus master
1
1
1
1
Pseudo DMA operation
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 20 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 2 V to 7 V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: Voltage values are with respect to VSS.
VCC
VIH
VIL
tt
VO
Supply voltage
High-level DC input voltage (TTL)‡
Low-level DC input voltage (TTL)‡
MIN
NOM
MAX
UNIT
4.75
5.0
5.25
V
VCC
0.8
V
0
25
ns
0
VCC
V
0
70
°C
2.0
0
Input transitions (tr and tf, 10% to 90%)
Output voltage§
TA
Operating free-air temperature range
‡ Applies for external input buffers without hysteresis
§ Applies for external output buffers
V
electrical characteristics over recommended range of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS
(see Note 3)
PARAMETER
VOH
VOL
High-level output voltage, TTL-level signal (see Note 4)
IO
High-impedance output current
II
IDD
Input current, any input or input / output pin
Supply current
VI = VSS to VDD
VDD = MAX
Ci
Input capacitance, any input
f = 1 MHz,
Co
Output capacitance, any output or input /output
f = 1 MHz,
Low-level output voltage, TTL-level signal
VDD = MIN, IOH = MAX
VDD = MIN, IOL = MAX
VDD = MAX, VO = 2.4 V
VDD = MAX, VO = 0.4 V
MIN
TYP
MAX
2.4
UNIT
V
0.6
V
20
– 20
µA
± 20
µA
TBD
mA
other pins at 0 V
15
pF
other pins at 0 V
15
pF
NOTES: 3. For conditions shown as MIN or MAX, use the appropriate value specified under the recommended operating conditions.
4. The following signals require an external pullup resistor: SRAS / SAS, SRDY / SDTACK, SRD / SUDS, SWR / SLDS.
POST OFFICE BOX 1443
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ADVANCE INFORMATION
recommended operating conditions
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
Outputs are driven to a minimum high-logic level of 2.4 volts and to a maximum low-logic level of 0.6 volts. These
levels are compatible with TTL devices.
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,
the level at which the signal is said to be no longer high is 2 volts, and the level at which the signal is said to
be low is 0.8 volts. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 volts,
and the level at which the signal is said to be high is 2 volts, as shown below.
The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically
1.5 ns.
2 V (High)
0.8 V (Low)
test measurement
ADVANCE INFORMATION
The test load circuit shown in Figure 13 represents the programmable load of the tester pin electronics used
to verify timing parameters of TI380PCI output signals.
TESTER PIN
ELECTRONICS
IOL
OUTPUT
UNDER
TEST
VLOAD
CT
IOH
Where:
IOL = 2.0 mA DC level verification (all outputs)
IOH = 400 µA (all outputs)
VLOAD = 1.5 V typical DC level verification
0.7 V typical timing verification
CT = 65 pF typical load circuit capacitance and includes probe and jig capacitance.
Figure 13. Test Load Circuit
30
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TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
PCI INTERFACE TIMING
Vth
CLK
Vtest
Vtl
Tval
OUTPUT DELAY
Vtest
3-STATE OUTPUT
Vtest
Vtest
Ton
Toff
ADVANCE INFORMATION
Figure 14. Output Timing Measurement Conditions
Vth
CLK
Vtest
tsu
Vth
th
Inputs
Valid
Vtest
INPUT
Vtl
Vtl
Vtest
Vmax
Figure 15. Input Timing Measurement Conditions
measure and test condition parameters
SYMBOL
5-V SIGNALING
UNITS
Vth
Vtl
2.4
V
0.4
V
Vtest
Vmax
Input signal edge rate
1.5
V
2.0
V
1 V / ns
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31
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
timing parameters (5-V signaling environment)
MIN
MAX
tval
tval(ptp)
CLK to signal valid delay-bussed signals (see Notes 5, 6, 7)
PARAMETER
2
11
ns
CLK to signal valid delay-point-to-point (see Notes 5, 6, 7)
2
12
ns
ton
toff
Float to active delay (see Note 5)
2
tsu
tsu(ptp)
Input setup time to CLK-bussed signals (see Notes 7, 8)
th
trst
Input hold time from CLK (see Note 8)
0
ns
Reset active time after power stable (see Note 9)
1
ms
trst-clk
trst-off
Reset active time after CLK stable (see Note 8)
Active to float delay (see Note 5)
ns
28
Input setup time to CLK-point-to-point (see Notes 7, 8)
ns
7
ns
10, 12
ns
µs
100
Reset active to output float delay (see Notes 8, 10)
UNIT
40
ns
ADVANCE INFORMATION
NOTES: 5. See timing measurement conditions in the Output Timing Measurement Conditions diagram of the PCI Specification 2.0.
6. Minimum times are measured with 0 pF equivalent load; maximum times are measured with 50 pF equivalent load. Actual test
capacitance can vary, but results should be correlated to these specifications.
7. REQ and GNT are point-to-point signals, and have different output valid delay and input setup times than do bussed signals. GNT
has a setup of 10; REQ has a setup of 12. All other signals are bussed.
8. See timing measurement conditions in the Input Timing Measurement Conditions diagram of the PCI Specification 2.0.
9. RST is asserted and deasserted asynchronously with respect to CLK. Refer to PCI Specifications 2.0 for more information.
10. All output drivers must be floated when RST is active.
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
Serial EEPROM Interface
tCHCL
tCLCH
CLK
tDXCX
tDLCL
tCHDH
INPUT
tCLDX
tDHDL
SDA
INPUT
START
CONDITION
STOP AND
BUS FREE
SDA
CHANGE
ADVANCE INFORMATION
tCHDX
SCL
tCLQX
tCLQV
DATA VALID
SDA OUT
DATA OUTPUT
tDHDL
SCL
tW
SDA IN
tCHDX
tCHDH
DATA OUTPUT
STOP
CONDITION
START
CONDITION
Figure 16. AC Waveforms
POST OFFICE BOX 1443
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33
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
AC characteristics
PARAMETER
ALT
ADVANCE INFORMATION
tCH1CH2
tCL1CL2
Rise time, clock
tDH1DH2
tDL1DL1
Rise time, input
tCHDX
tCHCL
Setup time, clock high to input transition (see Note 11)
tDLCL
tCLDX
Input low to clock low (START)
tCLCH
tDXCX
Pulse duration, clock low
tCHDH
tDHDL
Clock high to input high (STOP)
tCLQV
tCLQX
Clock low to output valid
fC
tLPF
Clock frequency
MIN
tR
tF
Fall time, clock
tR
tF
Fall time, input
Pulse duration, clock high
Clock low to input transition
Input high to input low (bus free)
Clock high to output transition
Input low pass first order filter time constant (SCL and SDA inputs)
UNIT
1
µs
300
ns
1
µs
300
ns
tSU:STA
t-HIGH
4.7
µs
4
µs
tHD:STA
tHD:DAT
4
µs
0
µs
4.7
µs
tLOW
tSU:DAT
Input transition to clock transition
MAX
250
ns
tSU:STO
tBUF
4.7
µs
tAA
tDH
0.3
fSCL
TI
µs
4.7
3.5
µs
100
KHz
100
ns
300
ns
tW
Write time (see Note 12)
tWR
10
ms
NOTES: 11. For a reSTART condition, or following a write cycle
12. In the multibyte write mode only, if accessed bytes are on two consecutive rows (upper 5 MSB must not change), the maximum
programming time is doubled to 20 ms.
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TI380PCI
PCI BUS INTERFACE FOR THE TI380 COMMPROCESSORS
SPWS020 – AUGUST 1995
MECHANICAL DATA
PCM (S-PQFP-G***)
PLASTIC QUAD FLATPACK
144 PIN SHOWN
73
109
NO. OF
PINS***
A
144
22,75 TYP
160
25,35 TYP
72
0,38
0,22
0,13 M
0,65
144
37
0,16 NOM
1
36
A
28,20 SQ
27,80
31,45
SQ
30,95
3,60
3,20
Gage Plane
0,25
0,25 MIN
1,03
0,73
Seating Plane
4,10 MAX
0,10
4040024 / B 10/94
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-022
The 144 PCM is identical to the 160 PCM except that four leads per corner are removed.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
ADVANCE INFORMATION
108
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