TI TI380C27

TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
•
•
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•
•
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•
IEEE 802.5 and IBM Token-Ring Network 
Compatible
•
IEEE 802.3 and Blue Book Ethernet 
Network Compatible
Compatible With TI380FPA FNL
PacketBlaster
Token-Ring Features
– 16- or 4-Megabit-per-Second Data Rates
– Supports Up to 18K-Byte Frame Size
(16-Mbps Operation Only)
– Supports Universal and Local Network
Addressing
– Early Token-Release Option (16-Mbps
Operation Only)
– Compatible With the TMS38054
•
•
•
•
Ethernet Features
– 10 Megabit-per-Second Data Rate in
Half-Duplex Mode
– 20 Megabit-per-Second Data Rate in
Full-Duplex Mode
– Compatible With Most Ethernet
Serial-Network-Interface Devices
– Network-Speed Self-Test Feature
•
•
•
•
•
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•
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•
Glueless Interface to DRAMs
High-Performance 16-Bit CPU for
Communications-Protocol Processing
1- to 16.5-Megabyte-per-Second
High-Speed Bus Master DMA Interface
Low-Cost Host-Slave I/O Interface Option
Up to 32-Bit Host Address Bus
•
Selectable Host System-Bus Options
Adapter Local-Bus Speed Is Switchable
Between 4 MHz and 6 MHz
80x8x or 68xxx-Type Bus and Memory
Organization
– 8 - or 16-Bit Data Bus on 80x8x Buses
– Optional Parity Checking
Dual-Port DMA and Direct I/O Transfers to
Host Bus
Supports 8 - or 16-Bit Pseudo-DMA
Operation
Enhanced-Address-Copy-Option (EACO)
Interface Supports External
Address-Checking Logic for Bridging or
External Custom Applications
Support for Module High-Impedance
In-Circuit Testing
ADVANCE INFORMATION
•
Built-In Real-Time Error Detection
Bring-Up and Self-Test Diagnostics With
Loopback
Automatic Frame-Buffer Management
2- to 33-MHz System-Bus Clock
Slow-Clock Low-Power Mode
Single 5-V Supply
0.8 -µm CMOS Technology
250-mA Typical Latch-Up Immunity at 25°C
ESD Protection Exceeds 2 000 V
144-Pin Plastic Thin Quad Flat Package
(PGE Suffix)
Operating Temperature Range
0°C to 70°C
LAN Subsystem
Attached
System
Bus
(2 MHz
to
33 MHz)
TI380C27
Token-Ring
or Ethernet
Physical-Layer
Circuitry
Transmit
To
Network
Receive
Memory
Figure 1. Network-Commprocessor Applications Diagram
IBM and Token-Ring Network are trademarks of International Business Machines Corporation.
PacketBlaster is a trademark of Texas Instruments Incorporated.
Ethernet is a trademark of Xerox Corporation.
Copyright  1995, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
pin assignments
112
111
110
109
116
115
114
113
120
119
118
117
124
123
122
121
128
127
126
125
132
131
130
129
136
135
134
133
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
70
71
72
66
67
68
69
62
63
64
65
58
59
60
61
54
55
56
57
50
51
52
53
46
47
48
49
VDDL
CLKDIV
VSSC
NSELOUT0
PRTYEN
BTSTRP
SIACK
SRESET
SRS1
SRS0
SRSX
SCS
SBRLS
SBBSY
S8 / SHALT
VSSL
VSSL
SRS2 / SBERR
VDDL
SI / M
SINTR / SIRQ
SHLDA / SBGR
SDDIR
SRAS / SAS
SWR / SLDS
VSS
SXAL
SALE
SBCLK
SADL7
SADL6
SADL5
SADL4
SADL3
NC
VDD
41
42
43
44
45
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
ADVANCE INFORMATION
NC
VSSL
MOE
MBEN
MADH7
MADH6
MADH5
MADH4
VDD
NC
VSS
MADH3
MADH2
MADH1
MADH0
MAXPH
MBRQ
MBGR
VSS
MAXPL
MADL7
MADL6
MADL5
MADL4
MADL3
MADL2
MADL1
MADL0
EXTINT3
EXTINT2
EXTINT1
EXTINT0
NMI
VDD
NC
VSSL
140
139
138
137
144
143
142
141
V SSC
MRAS
MW
MCAS
MAX2
MAX0
MDDIR
VDD
SYNCIN
OSCIN
VSS
MROMEN
MACS
MAL
MREF
VSSL
VSSL
MBIAEN
VDDL
MRESET
MBCLK2
MBCLK1
OSCOUT
RCVR / RXD
RCLK / RXC
NSELOUT1
PXTALIN / TXC
VSSC
WRAP / TXEN
DRVR
DRVR
WFLT/COLL
NSRT / LPBK
FRAQ / TXD
REDY/CRS
NC
PGE PACKAGE
( TOP VIEW )
2
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VSSL
NC
VDD
XMATCH
XFAIL
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
SADH0
SADH1
SADH2
SADH3
SADH4
SADH5
VSSD
NC
VDD
NC
VSSC
SADH6
SADH7
SPH
SRD / SUDS
SRDY / SDTACK
SOWN
SDBEN
SBHE / SRNW
SHRQ / SBRQ
SPL
SADL0
SADL1
SADL2
VSSL
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
description
The TI380C27 is a single-chip network-communications processor (commprocessor) that supports token-ring
or Ethernet local area networks (LANs). Token ring at a data rate of either 16 Mbps or 4 Mbps or Ethernet at
a data rate of either 10 Mbps (half duplex) or 20 Mbps (full duplex) can be selected. A flexible configuration
scheme allows network type and speed to be configured by hardware or software. This allows the design of LAN
subsystems that support both token-ring and Ethernet networks by electrically or physically switched network
front-end circuits. In addition, the TI380C27 can be used with the TI380FPA PacketBlaster for maximum
performance.
The TI380C27 token-ring capability conforms to ISO 8802 – 5 / IEEE 802.5 – 1992 standards and has been
verified to be completely IBM Token-Ring Network compatible. By integrating the essential control building
blocks needed on a LAN-subsystem card into one device, the TI380C27 can ensure that this IBM compatibility
is maintained in silicon.
The high degree of integration of the TI380C27 makes it a virtual LAN subsystem on a single chip. Protocol
handling, host-system interfacing, memory interfacing, and communications processing are all provided
through the TI380C27. To complete LAN-subsystem design, only the network-interface hardware, local
memory, and minimal additional components such as PAL  devices and crystal oscillators need to be added.
The TI380C27 provides a 32-bit system-memory address reach with a high-speed bus-master DMA interface
that supports rapid communications with the host system. In addition, the TI380C27 supports direct I/O and a
low-cost 8- or 16-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit
slave I/O interface. Finally, selectable 80x8x or 68xxx-type host-system bus and memory organization add to
design flexibility.
The TI380C27 supports addressing for up to 2M bytes of local memory. This expanded memory capacity can
improve LAN-subsystem performance by minimizing the frequency of host LAN-subsystem communications by
allowing larger blocks of information to be transferred at one time. The support of large local memory is important
in applications that require large data transfers (such as graphics or data-base transfers) and in heavily loaded
networks where the extra memory can provide data buffers to store data until it can be processed by the host.
The proprietary CPU used in the TI380C27 allows protocol software to be downloaded into RAM or stored in
ROM in the local-memory space. By moving protocols to the LAN subsystem, overall system performance is
increased. This is accomplished by the offloading of processing from the host system to the TI380C27, which
can also reduce LAN-subsystem-to-host communications. As other protocol software is developed, greater
differentiation of end products with enhanced system performance will be possible.
In addition, the TI380C27 includes hardware counters that provide real-time error detection and automatic
frame-buffer management. These counters control system-bus retries, control burst size, and track host and
LAN-subsystem buffer status. Previously, these counters needed to be maintained in software. By integrating
them into hardware, software overhead is removed and LAN-subsystem performance is improved.
The TI380C27 implements a TI-patented enhanced-address-copy-option (EACO) interface. This interface
supports external address-checking devices, such as the TMS380SRA source-routing accelerator. The
TI380C27 has a 128-word external I/O space in its memory to support external address-checker devices and
other hardware extensions to the TMS380 architecture.
The major blocks of the TI380C27 include the communications processor (CP), the system interface (SIF), the
memory interface (MIF), the protocol handler (PH), the clock generator (CG), and the adapter-support function
(ASF), as shown in the functional block diagram.
The TI380C27 is available in a 144-pin plastic thin quad flat package (PGE suffix) and is characterized for
operation from 0°C to 70°C.
PAL  is a registered trademark of Advanced Micro Devices, Inc. Other companies also manufacture programmable array logic devices.
POST OFFICE BOX 1443
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3
ADVANCE INFORMATION
The TI380C27 Ethernet capability conforms to ISO / IEC 8802 – 3 (ANSI / IEEE Std. 802.3 ) CSMA / CD standards
and the Ethernet Blue Book standard.
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
description (continued)
The TI380C27 has a bus interface to the host system, a bus interface to local memory, and an interface to the
physical-layer circuitry. Pin names starting with the letter S attach to the host-system bus and pin names starting
with the letter M attach to the local-memory bus. Active-low signals have names with overbars; e.g., SCS.
functional block diagram
SADH0
SADH7
SADL0
SADL7
ADVANCE INFORMATION
SPH
SPL
SBRLS
SINTR/SIRQ
SDDIR
SDBEN
SALE
SXAL
SOWN
SIACK
SBCLK
SRD/SUDS
SWR/SLDS
SRDY/SDTACK
SI/M
SHLDA/SBGR
SBHE/SRNW
SRAS/SAS
S8/SHALT
SRESET
SRS0
SRS1
SRS2/SBERR
SCS
SRSX
SHRQ/SBRQ
SBBSY
BTSTRP
PRTYEN
NSELOUT0
NSELOUT1
System
Interface
(SIF)
• DIO Control
• Bus Control
• DMA Control
Memory
Interface
(MIF)
• DRAM Refresh
• Local-Bus
Arbitrator
• Local-Bus
Control
• Local
Parity-Check /
Generator
Clock
Generator
(CG)
AdapterSupport
Function
(ASF)
Communications
Processor
• Interrupts
• Test Function
MADH0
MADH7
MADL0
MADL7
MRAS
MCAS
MAXPH
MAXPL
MW
MOE
MDDIR
MAL
MAX0
MAX2
MRESET
MROMEN
MBEN
MBRQ
MBGR
MACS
MBIAEN
MREF
OSCIN
OSCOUT
MBCLK1
MBCLK2
SYNCIN
CLKDIV
NMI
EXTINT0
EXTINT3
TEST0
TEST5
XMATCH
XFAIL
RCLK / RXC
REDY / CRS
WFLT / COLL
RCVR / RXD
PXTALIN / TXC
4
Protocol Handler (PH)
for Token-Ring and
Ethernet Interface
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FRAQ / TXD
NSRT / LPBK
WRAP / TXEN
DRVR
DRVR
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions
PIN
NAME
BTSTRP
NO.
42
I/O †
I
DESCRIPTION
Bootstrap. The value on BTSTRP is loaded into the BOOT bit of the SIFACL register at reset (i.e., when
SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value. BTSTRP
indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters are RAM,
the TI380C27 is denied access to the local-memory bus until the CPHALT bit in the SIFACL register
is cleared.
H = Chapters 0 and 31 of local memory are RAM based (see Note 1).
L = Chapters 0 and 31 of local memory are ROM based.
Clock divider select (see Note 2)
38
I
EXTINT0
EXTINT1
EXTINT2
EXTINT3
32
31
30
29
I/O
MACS
132
I
MADH0
MADH1
MADH2
MADH3
MADH4
MADH5
MADH6
MADH7
15
14
13
12
8
7
6
5
MADL0
MADL1
MADL2
MADL3
MADL4
MADL5
MADL6
MADL7
28
27
26
25
24
23
22
21
MAL
131
I/O
H = 64-MHz OSCIN for 4-MHz local bus
L = 32-MHz OSCIN for 4-MHz local bus or 48-MHz OSCIN for 6-MHz local bus
Reserved; must be pulled high (see Note 3)
Reserved; must be tied low (see Note 4)
Local-memory address, data, and status bus — high byte. For the first quarter of the local-memory
cycle, these bus lines carry address bits AX4 and A0 to A6; for the second quarter, they carry status
bits; and for the third and fourth quarters, they carry data bits 0 to 7. The most significant bit is MADH0
and the least significant bit is MADH7.
Signal
I/O
1Q
AX4, A0 – A6
Memory Cycle
2Q
3Q
Status
D0 – D7
4Q
D0 – D7
Local-memory address, data, and status bus — low byte. For the first quarter of the local-memory
cycle, these bus lines carry address bits A7 to A14; for the second quarter, they carry address bits AX4
and A0 to A6; and for the third and fourth quarters, they carry data bits 8 to 15. The most significant
bit is MADL0 and the least significant bit is MADL7.
Signal
O
ADVANCE INFORMATION
CLKDIV
1Q
A7 – A14
Memory Cycle
2Q
3Q
AX4, A0 – A6
D8 – D15
4Q
D8 – D15
Memory-address latch. MAL is a strobe signal for sampling the address at the start of the memory
cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH,
MAX2, MAXPL, MADH0 – MADH7, and MADL0 – MADL7. Three 8-bit transparent latches can be used
to retain a 20-bit static address throughout the cycle.
Rising edge = No signal latching
Falling edge = Allows the above address signals to be latched
Local-memory-extended address bit. MAX0 drives AX0 at row-address time and drives A12 at
column-address and data-valid times for all cycles. This signal can be latched by MRAS. Driving A12
eases interfacing to a BIA ROM.
MAX0
139
I/O
Signal
1Q
AX0
Memory Cycle
2Q
3Q
A12
A12
4Q
A12
† I = input, O = output
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
2. The TI380FPA and TMS380SRA are currently supported only with the 4-MHz local bus in either CLKDIV state. Expansion to support
the 6-MHz local bus is under development.
3. Each pin must be individually tied to VCC with a 1-kΩ pullup resistor.
4. Pin should be connected to ground.
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5
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
MAX2
MAXPH
ADVANCE INFORMATION
MAXPL
NO.
140
16
20
I/O †
DESCRIPTION
I/O
Local-memory-extended address bit. MAX2 drives AX2 at row-address time, which can be latched by
MRAS, and drives A14 at column-address and data-valid times for all cycles. Driving A14 eases
interfacing to a BIA ROM.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX2
A14
A14
A14
I/O
Local-memory-extended address and parity — high byte. For the first quarter of a memory cycle,
MAXPH carries the extended-address bit AX1; for the second quarter of a memory cycle, it carries the
extended-address bit AX0; and for the last half of the memory cycle, it carries the parity bit for the
high-data byte.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX1
AX0
Parity
Parity
I/O
Local-memory-extended address and parity — low byte. For the first quarter of a memory cycle,
MAXPL carries the extended-address bit AX3; for the second quarter of a memory cycle, it carries
extended-address bit AX2; and for the last half of the memory cycle, it carries the parity bit for the
low-data byte.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX3
AX2
Parity
Parity
Local-bus clock 1 and local-bus clock 2. These signals are referenced for all local-bus transfers.
MBCLK2 lags MBCLK1 by a quarter of a cycle. These clocks operate according to:
MBCLK1
MBCLK2
MBEN
123
124
4
O
O
MBCLK[1:2]
8 MHz
8 MHz
12 MHz
OSCIN
64 MHz
32 MHz
48 MHz
CLKDIV
H
L
L
Buffer enable. MBEN enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL, and
MADL buses during the data phase. This signal is used in conjunction with MDDIR, which selects the
buffer output direction.
H = Buffer output disabled
L = Buffer output enabled
MBGR
18
I/O
Reserved; must be left unconnected.
Burned-in address enable. MBIAEN is an output signal used to provide an output enable for the ROM
containing the adapter’s burned-in address (BIA).
MBIAEN
127
O
H = This signal is driven high for any write accesses to the addresses between > 00.0000 and
> 00.000F, or any accesses (read/write) to any other address.
L = This signal is driven low for any read from addresses between > 00.0000 and > 00.000F.
MBRQ
17
I/O
Reserved; must be pulled high (see Note 3).
† I = input, O = output
NOTE 3: Each pin must be individually tied to VCC with a 1-kΩ pullup resistor.
6
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O †
DESCRIPTION
Column-address strobe for DRAMs. MCAS is valid for the 3/16 of the memory cycle following the
row-address portion of the cycle. MCAS is driven low every memory cycle while the column address
is valid on MADL0 – MADL7, MAXPH, and MAXPL, except when one of the following
conditions occurs:
MCAS
141
O
1)
2)
3)
When the address accessed is in the BIA ROM (> 00.0000 – > 00.000F)
When the address accessed is in the EPROM memory map (i.e., when the BOOT bit in
the SIFACL register is zero and an access is made between > 00.0010 – > 00.FFFF
or > 1F.0000 – > 1F.FFFF)
When the cycle is a refresh cycle, in which case MCAS is driven at the start of the cycle before
MRAS (for DRAMs that have CAS-before-RAS refresh). For DRAMs that do not support CASbefore-RAS refresh, it may be necessary to disable MCAS with MREF during the refresh
cycle.
Data direction. MDDIR is used as a direction control for bidirectional bus drivers. This signal becomes
valid before MBEN becomes active.
138
I/O
ADVANCE INFORMATION
MDDIR
H = TI380C27 memory-bus write
L = TI380C27 memory-bus read
Memory output enable. MOE is used to enable the outputs of the DRAM memory during a read cycle.
This signal is high for EPROM or BIA ROM read cycles.
MOE
3
O
H = Disable DRAM outputs
L = Enable DRAM outputs
MRAS
143
O
Row-address strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle. MRAS
is driven low every memory cycle while the row address is valid on MADL0 – MADL7, MAXPH, and
MAXPL for both RAM and ROM cycles. It is also driven low during refresh cycles when the refresh
address is valid on MADL0 – MADL7.
DRAM refresh cycle in progress. MREF is used to indicate that a DRAM refresh cycle is occurring. It
is also used for disabling MCAS to all DRAMs that do not use a CAS-before-RAS refresh.
MREF
130
O
H = DRAM refresh cycle in process
L = Not a DRAM refresh cycle
Memory-bus reset. MRESET is a reset signal generated when either the ARESET bit in the SIFACL
register is set or SRESET is asserted. This signal is used for resetting external local-bus glue logic.
MRESET
125
O
H = External logic not reset
L = External logic reset
MROMEN
133
O
ROM enable. During the first 5/16 of the memory cycle, MROMEN is used to provide a chip select for
ROMs when the BOOT bit of the SIFACL register is zero (i.e., when code is resident in ROM, not RAM).
It can be latched by MAL. It goes low for any read from addresses > 00.0010 – > 00.FFFF or > 1F.0000
– > 1F.FFFF when the BOOT bit in the SIFACL register is zero. MROMEN stays high for writes to these
addresses, accesses of other addresses, or accesses of any address when the BOOT bit is 1. During
the final three quarters of the memory cycle, MROMEN outputs the A13 address signal for interfacing
to a BIA ROM. This means MBIAEN, MAX0, ROMEN, and MAX2 together form a glueless interface
for the BIA ROM.
H = ROM disabled
L = ROM enabled
† I = input, O = output
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7
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
MW
NO.
142
I/O †
O
DESCRIPTION
Local-memory write. MW is used to specify a write cycle on the local-memory bus. The data on the
MADH0 – MADH7 and MADL0 – MADL7 buses is valid while MW is low. DRAMs latch data on the falling
edge of MW, while SRAMs latch data on the rising edge of MW.
H = Not a local-memory write cycle
L = Local-memory write cycle
NMI
33
I
Nonmaskable interrupt request. NMI must be left unconnected.
External oscillator input. OSCIN provides the clock frequency to the TI380C27 for a 4-MHz or 6-MHz
internal bus (see Note 5 and Note 6).
OSCIN
135
I
CLKDIV
H
L
OSCIN
64 MHz for a 4-MHz local bus
32 MHz for a 4-MHz local bus or 48 MHz for a 6-MHz local bus
OSCOUT
122
O
CLKDIV
L
H
PRTYEN
41
I
OSCOUT
OSCIN / 4 (if OSCIN = 32 MHz, OSCOUT = 8 MHz; if OSCIN = 48 MHz,
OSCOUT = 12 MHz
OSCIN / 8 (if OSCIN = 64 MHz, then OSCOUT = 8 MHz)
Parity enable. The value on PRTYEN is loaded into the PEN bit of the SIFACL register at reset (i.e.,
when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value.
PRTYEN enables parity checking for the local memory.
H = Local-memory data bus checked for parity (see Note 1)
L = Local-memory data bus not checked for parity
Network selection outputs. NSELOUT0 and NSELOUT1 are controlled by the host through the
corresponding bits of the SIFACL register. The value of these bits/signals can be changed only while
the TI380C27 is reset.
NSELOUT0
NSELOUT1
40
119
SADH0
SADH1
SADH2
SADH3
SADH4
SADH5
SADH6
SADH7
97
96
95
94
93
92
86
85
O
NSELOUT0
L
L
H
H
NSELOUT1
L
H
L
H
DESCRIPTION
Full-duplex Ethernet
16-Mbps token ring
Half-duplex Ethernet
4-Mbps token ring
System address/data bus — high byte (see Note 1).These lines make up the most significant byte of
each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is
SADH0, and the least significant bit is SADH7.
I/O
Address multiplexing: Bits 31 – 24 and bits 15 – 8
Data multiplexing: Bits 15 – 8
SADL0
76
System address/data bus — low byte (see Note 1). These lines make up the least significant byte of
SADL1
75
each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is
SADL2
74
SADL0, and the least significant bit is SADL7.
SADL3
70
I/O
SADL4
69
Address multiplexing: Bits 23 – 16 and bits 7 – 0
SADL5
68
Data multiplexing : Bits 7 – 0
SADL6
67
SADL7
66
† I = input, O = output
NOTES: 1 Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch or loads).
5. Pin has an expanded input voltage specification.
6. A maximum of two TI380C27 devices may be connected to any one oscillator.
8
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ADVANCE INFORMATION
Oscillator output
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
SALE
NO.
64
I/O †
DESCRIPTION
O
System address-latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of the
address from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle. Systems
that implement address parity can also externally latch the parity bits (SPH and SPL) for the latched
address.
System bus busy. The TI380C27 samples the value on SBBSY during arbitration (see Note 1). The
sample has one of two values:
SBBSY
50
I
H = Not busy. The TI380C27 can become bus master if the grant condition is met.
L = Busy. The TI380C27 cannot become bus master.
SBCLK
65
I
System bus clock. The TI380C27 requires SBCLK to synchronize its bus timings for all DMA transfers.
Valid frequencies are 2 MHz – 33 MHz.
SBHE is used for system byte high enable. SBHE is a 3-state output driven during DMA;
it is an input at all other times.
Intel Mode
79
I/O
Motorola
Mode
ADVANCE INFORMATION
SBHE/SRNW
H = System byte high not enabled (see Note 1)
L = System byte high enabled
SRNW is used for system read not write. SRNW serves as a control signal to indicate
a read or write cycle.
H = Read cycle (see Note 1)
L = Write cycle
System bus release. SBRLS indicates to the TI380C27 that a higher-priority device requires the system
bus. The value on SBRLS is ignored when the TI380C27 is not perfoming DMA. SBRLS is internally
synchronized to SBCLK.
SBRLS
49
I
H = The TI380C27 can hold onto the system bus (see Note 1).
L = The TI380C27 should release the system bus upon completion of current DMA cycle. If the
DMA transfer is not yet complete, the SIF rearbitrates for the system bus.
System chip select. SCS activates the system interface of the TI380C27 for a DIO read or write.
SCS
48
I
H = Not selected (see Note 1)
L = Selected
System data-bus enable. SDBEN signals to the external data buffers to begin driving data. SDBEN is
activated during both DIO and DMA.
SDBEN
80
O
H = Keep external data buffers in the high-impedance state
L = Cause external data buffers to begin driving data
System data direction. SDDIR provides to the external data buffers a signal indicating the direction the
data is moving. During DIO writes and DMA reads, SDDIR is low (data direction is into the TI380C27).
During DIO reads and DMA writes, SDDIR is high (data direction is out from the TI380C27). When the
system interface is not involved in a DIO or DMA operation, SDDIR is high by default.
SDDIR
59
O
SDDIR
H
L
DATA
DIRECTION
output
input
DIO
read
write
DMA
write
read
† I = input, O = output
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
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9
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O †
DESCRIPTION
Intel Mode
SHLDA/SBGR
58
SHLDA is used for system hold acknowledge. SHLDA indicates that the system DMA
hold request has been acknowledged. It is internally synchronized to SBCLK
(see Note 1).
H = Hold request acknowledged
L = Hold request not acknowledged
I
Motorola
Mode
SBGR is used for system bus grant. SBGR is an active-low bus grant, as defined in the
standard 68xxx interface, and is internally synchronized to SBCLK (see Note 1).
H = System bus not granted
L = System bus granted
SHRQ is used for system hold request. SHRQ is used to request control of the system
bus in preparation for a DMA transfer. SHRQ is internally synchronized to SBCLK.
Intel Mode
ADVANCE INFORMATION
SHRQ/SBRQ
78
H = System bus requested
L = System bus not requested
O
Motorola
Mode
SBRQ is used for system bus request. SBRQ is used to request control of the system
bus in preparation for a DMA transfer. SBRQ is internally synchronized to SBCLK.
H = System bus not requested
L = System bus requested
System interrupt acknowledge. SIACK is from the host processor to acknowledge the interrupt request
from the TI380C27.
SIACK
43
I
H = System interrupt not acknowledged (see Note 1)
L = System interrupt acknowledged: The TI380C27 places its interrupt vector onto the system
bus.
System Intel/Motorola mode select. The value on SI/M specifies the system-interface mode.
SI/M
56
I
H = Intel-compatible interface mode selected. Intel interface can be 8-bit or 16-bit mode
(see S8/SHALT description and Note 1).
L = Motorola-compatible interface mode selected. Motorola interface mode is always 16 bits.
SINTR is used for system-interrupt request. TI380C27 activates SINTR to signal an
interrupt request to the host processor.
Intel Mode
SINTR/SIRQ
57
H = Interrupt request by TI380C27
L = No interrupt request
O
Motorola
Mode
SOWN
81
O
SIRQ is used for system-interrupt request. TI380C27 activates SIRQ to signal an
interrupt request to the host processor.
H = No interrupt request
L = Interrupt request by TI380C27
System bus owned. SOWN indicates to external devices that TI380C27 has control of the system bus.
SOWN drives the enable signal of the bus transceiver chips that drive the address and bus-control
signals.
H = TI380C27 does not have control of the system bus.
L = TI380C27 has control of the system bus.
SPH
84
I/O
System parity high. The optional odd-parity bit for each address or data byte transmitted over
SADH0 – SADH7 (see Note 1).
SPL
77
I/O
System parity low. The optional odd-parity bit for each address or data byte transmitted over
SADL0 – SADL7 (see Note 1).
† I = input, O = output
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
10
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
NAME
NO.
I/O †
DESCRIPTION
Intel Mode
SRAS/SAS
60
SRAS is used for system memory-address strobe (see Note 7). SRAS is used to latch
the SCS and SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is
tied to the SALE output of the system bus. The latching capability can be defeated since
the internal latch for these inputs remains transparent as long as SRAS remains high.
This permits SRAS to be pulled high and the signals at SCS, SRSX – SRS2, and SBHE
to be applied independently of the SALE strobe from the system bus. During DMA, SRAS
remains an input.
H
L
Falling edge
I/O
Motorola
Mode
= Transparent mode
= Holds latched values of SCS, SRSX – SRS2, and SBHE
= Latches SCS, SRSX – SRS2, and SBHE
SAS is used for sytem-memory address strobe (see Note 7). SAS is an active-low
address strobe that is an input during DIO (although ignored as an address strobe) and
an output during DMA.
H = Address is not valid.
L = Address is valid and a transfer operation is in progress.
SRD is used for system read strobe (see Note 7). SRD is the active-low strobe indicating
that a read cycle is performed on the system bus. SRD is an input during DIO and an
output during DMA.
Intel Mode
SRD/SUDS
83
H = Read cycle is not occurring.
L = If DMA, host provides data to system bus.
If DIO, SIF provides data to system bus.
I/O
Motorola
Mode
Intel Mode
SRDY/SDTACK
82
SUDS is used for upper-data strobe (see Note 7). SUDS is the active-low upper-data
strobe. SUDS is an input during DIO and an output during DMA.
H = Not valid data on SADH0 – SADH7 lines
L = Valid data on SADH0 – SADH7 lines
SRDY is used for system bus ready (see Note 7). SRDY indicates to the bus master that
a data transfer is complete. SRDY is asynchronous but during DMA and pseudo-DMA
cycles, it is internally synchronized to SBCLK. During DMA cycles, SRDY must be
asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state.
SRDY is an output when the TI380C27 is selected for DIO; otherwise, it is an input.
H = System bus is not ready.
L = Data transfer is complete; system bus is ready.
I/O
Motorola
Mode
SDTACK is used for system data-transfer acknowledge (see Note 7). The purpose of
SDTACK is to indicate to the bus master that a data transfer is complete. SDTACK is
internally synchronized to SBCLK. During DMA cycles, SDTACK must be asserted
before the falling edge of SBCLK in state T2 in order to prevent a wait state. SDTACK
is an output when the TI380C27 is selected for DIO; otherwise, it is an input.
H = System bus is not ready.
L = Data transfer is complete; system bus is ready.
System reset. SRESET is activated to place the TI380C27 into a known initial state. Hardware reset
puts most of the TI380C27 outputs into the high-impedance state and place all blocks into the reset
state. The Intel mode DMA bus-width selection (S8) is latched on the rising edge of SRESET.
SRESET
44
I
H
= No system reset
L
= System reset
Rising edge = Latch bus width for DMA operations (for Intel-mode applications)
† I = input, O = output
NOTE 7: Pin should be tied to VCC with a 4.7-kΩ pullup resistor.
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11
ADVANCE INFORMATION
PIN
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O †
DESCRIPTION
Intel Mode
SRSX and SRS0 – SRS2 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
SRSX and the least significant bit is SRS2 (see Note 1).
MSb
Register selected = SRSX
SRSX
SRS0
SRS1
SRS2/SBERR
47
46
45
54
SRS0
SRS1
LSb
SRS2/SBERR
SRSX, SRS0 and SRS1 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
SRSX and the least significant bit is SRS1 (see Note 1).
I
Motorola
Mode
Register selected
MSb
= SRSX
SRS0
LSb
SRS1
ADVANCE INFORMATION
SBERR is used for bus error. SBERR corresponds to the bus-error signal of the 68xxx
microprocessor. SBERR is internally synchronized to SBCLK. This input is driven low
during a DMA cycle to indicate to the TI380C27 that the cycle must be terminated, (see
Section 3.4.5.3 of the TMS380 Second-Generation Token Ring User’s Guide
(SPWU005) for more information).
SWR is used for system-write strobe (see Note 7). SWR is an active-low write strobe that
is an input during DIO and an output during DMA.
Intel Mode
SWR/SLDS
61
I/O
Motorola
Mode
H = Write cycle is not occurring.
L = If DMA, data to be driven from SIF to host bus.
If DIO, on the rising edge, the data is latched and written to the selected register.
SLDS is used for lower-data strobe (see Note 7). SLDS is an input during DIO and an
output during DMA.
H = Not valid data on SADL0 – SADL7 lines
L = Valid data on SADL0 – SADL7 lines
SXAL
63
O
System-extended-address latch. SXAL provides the enable pulse used to externally latch the most
significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle
of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address
counter causes a carry out of the lower 16 bits). Systems that implement parity on addresses can use
SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.
SYNCIN
136
I
Reserved. SYNCIN must be left unconnected (see Note 1).
Intel Mode
S8/SHALT
51
S8 is used for system 8/16-bit bus select. S8 selects the bus width used for
communications through the system interface. On the rising edge of SRESET, the
TI380C27 latches the DMA bus width; otherwise, the value on S8 dynamically selects
the DIO bus width.
H = Selects 8-bit mode (see Note 1)
L = Selects 16-bit mode
I
Motorola
Mode
SHALT is used for system halt/bus error retry. If SHALT is asserted along with SBERR,
the adapter retries the last DMA cycle. This is the rerun operation as defined in the 68xxx
specification. The BERETRY counter is not decremented by SBERR when SHALT is
asserted (see Section 3.4.5.3 of the TMS380 Second-Generation Token Ring User’s
Guide (SPWU005) for more information).
† I = input, O = output
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
7. Pin should be tied to VCC with a 4.7-kΩ pullup resistor.
12
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
Network Media Interface — Token-Ring Mode ( TEST1 = H, TEST2 = H)
PIN
NAME
DRVR
DRVR
NO.
115
114
I/O †
DESCRIPTION
O
Differential-driver data output. DRVR and DRVR are the differential outputs that send the TI380C27
transmit data to the TMS38054 for driving onto the ring-transmit-signal pair.
Frequency-acquisition control. FRAQ determines the use of frequency- or phase-acquisition mode in
the TMS38054.
FRAQ
111
O
H = Wide range. Frequency centering to PXTALIN by TMS38054.
L = Narrow range. Phase lock onto the incoming data (RCVINA and RCVINB) by the TMS38054.
Insert-control signal to the TMS38054. NSRT enables the phantom-driver outputs (PHOUTA and
PHOUTB) of the TMS38054, through the watchdog timer, for insertion onto the token ring.
NSRT
112
O
PXTALIN
118
I
Ring-interface clock-frequency control (see Note 5). At 16-Mbps ring speed, PXTALIN must be
supplied a 32-MHz signal. At 4-Mbps ring speed, PXTALIN must be 8 MHz and can be the output from
OSCOUT.
RCLK
120
I
Ring-interface recovered clock (see Note 5). RCLK is the clock recovered by the TMS38054 from the
token-ring received data. For 16-Mbps operation, RCLK is a 32-MHz clock; for 4-Mbps operation,
RCLK is an 8-MHz clock.
RCVR
121
I
Ring-interface received data (see Note 5). RCVR contains the data received by the TMS38054 from
the token ring.
= Inactive, phantom current removed (due to watchdog timer)
= Inactive, phantom current removed (due to watchdog timer)
= Active, current output on PHOUTA and PHOUTB
Ring-interface ready. REDY indicates the presence of received data as monitored by the TMS38054
energy-detect capacitor.
REDY
110
I
H = Not ready. Ignore received data.
L = Ready. Received data.
Wire-fault detect. WFLT is an input to the TI380C27 driven by the TMS38054. WFLT indicates a current
imbalance of the TMS38054 PHOUTA and PHOUTB pins.
WFLT
113
I
H = No wire fault detected
L = Wire fault detected
WRAP
116
O
Internal wrap select. WRAP is an output from the TI380C27 to the ring interface to activate an internal
attenuated feedback path from the transmitted data (DRVR) to receive data (RCVR) signals for
bring-up diagnostic testing. When active, the TMS38054 also cuts off the current drive to the
transmission pair.
H = Normal ring operation
L = Transmit data drives receive data (loopback)
† I = input, O = output
NOTE 5: Pin has an expanded input voltage specification.
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13
ADVANCE INFORMATION
Static high
Static low
NSRT low and pulsed high
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
Network-Media Interface — Ethernet Mode (TEST1 = L, TEST2 = H)
PIN
NAME
NO.
I/O †
DESCRIPTION
DRVR
DRVR
115
114
O
DRVR and DRVR have no Ethernet function and should be left unconnected.
TXD
111
O
Ethernet transmit data. TXD provides the Ethernet PHY-layer circuitry with a bit-rate from the
TI380C27. Data is output synchronously TXC. TXD is normally connected to TXD of an Ethernet serial
network interface (SNI) chip.
Loopback. LPBK enables loopback of Ethernet transmit data through the Ethernet (SNI) device to
receive data.
LPBK
112
O
H = Wrap through the front-end device
L = Normal operation
TXC
118
I
Ethernet transmit clock. TXC is a 10-MHz clock input used to synchronize transmit data from the
TI380C27 to the Ethernet PHY layer circuitry. TXC is a continuously running clock and is normally
connected to the TXC output of an Ethernet SNI chip (see Note 5).
ADVANCE INFORMATION
RXC
120
I
Ethernet receive clock. RXC is a 10-MHz clock input used to synchronize received data from the
Ethernet PHY-layer circuitry to the TI380C27. RXC must be present whenever CRS is active (although
it can be held low for a maximum of 16 clock cycles after the rising edge of CRS). When CRS is inactive,
it is permissible to hold RXC low and is normally connected to the RXC output of an Ethernet SNI chip.
The TI380C27 requires RXC to be maintained in the low state when CRS is not asserted (see Note
5).
RXD
121
I
Ethernet received data. RXD signal provides the TI380C27 with bit-rate network data from the Ethernet
front-end device. Data must be synchronous with RXC and is normally connected to RXD of an
Ethernet SNI chip (see Note 5).
CRS
110
I
Ethernet carrier sense. CRS indicates to the TI380C27 that the Ethernet PHY-layer circuitry has
network data present on RXD. CRS is asserted (high) when the first bit of the frame is received and
is deasserted after the last bit of the frame is received.
H = Receiving data
L = No data on network
COLL
113
I
Ethernet collision detect. COLL indicates to the TI380C27 that the Ethernet PHY-layer circuitry has
detected a network collision. COLL must be present for at least two TXC clock cycles to ensure it is
accepted by the TI380C27 and is normally connected to COLL of an Ethernet SNI chip. COLL can also
be an indication of the SQE test signal.
H = COLL detected by the SNI device
L = Normal operation
TXEN
116
O
Ethernet transmit enable. TXEN indicates to the Ethernet PHY-layer circuitry that bit-rate data is
present on TXD. TXEN is output synchronously to TXC and is normally connected to TXE of an
Ethernet SNI chip.
H = Data line currently contains data to be transmitted
L = No valid data on TXEN
† I = input, O = output
NOTE 5: Pin has an expanded input voltage specification.
14
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O †
DESCRIPTION
Network select inputs. TEST0 – TEST2 are used to select the network speed and type to be used by
the TI380C27. These inputs should be changed only during adapter reset. Connect TEST2 to VDDL.
103
102
101
I
TEST3
TEST4
TEST5
100
99
98
I
XFAIL
104
I
TEST0
L
L
H
H
X
TEST1
L
H
L
H
X
TEST2
H
H
H
H
L
DESCRIPTION
Full-duplex Ethernet
16-Mbps token ring
Half-duplex Ethernet
4-Mbps token ring
Reserved
Test inputs. TEST3 – TEST5 should be left unconnected (see Note 1). Module-in-place test mode is
achieved by tying TEST3 and TEST4 to ground. In this mode, all TI380C27 outputs are in the
high-impedance state. Internal pullups on all TI380C27 inputs are disabled (except TEST3 – TEST5).
External fail-to-match signal. An enhanced-address-copy-option (EACO) device uses XFAIL to
indicate to the TI380C27 that it should not copy the frame nor set the ARI/FCI bits in a token-ring frame
due to an external address match.The ARI/FCI bits in a token-ring frame can be set due to an internal
address-matched frame. If an EACO device is not used, XFAIL must be left unconnected. XFAIL is
ignored when CAF mode is enabled [see table in XMATCH description (see Note 1)].
H = No address match by external address checker
L = External address-checker-armed state
External match signal. An enhanced-address-copy-option (EACO) device uses XMATCH to indicate
to the TI380C27 to copy the frame and set the ARI/FCI bits in a token-ring frame. If an EACO device
is not used, XMATCH must be left unconnected. XMATCH is ignored when CAF mode is enabled
(see Note 1).
XMATCH
105
I
H = Address match recognized by external address checker
L = External address-checker-armed state
XMATCH
0
0
1
1
Hi-Z
XFAIL
0
1
0
1
Hi-Z
FUNCTION
Armed (processing frame data)
Do not externally match the frame (XFAIL takes precedence).
Copy the frame
Do not externally match the frame (XFAIL takes precedence).
Reset state (adapter not initialized)
VDDL
37
55
126
I
Positive-supply voltage for digital logic. All VDDL pins must be attached to the common-system
power-supply plane.
VDD
106
137
9
34
72
89
I
Positive-supply voltage for output buffers. All VDD pins must be attached to the common-system
power-supply plane.
VSSC
39
87
117
144
I
Ground reference for output buffers (clean ground). All VSSC pins must be attached to the
common-system ground plane.
† I = input, O = output
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
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15
ADVANCE INFORMATION
TEST0
TEST1
TEST2
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Pin Functions (Continued)
PIN
I/O †
DESCRIPTION
VSSL
2
36
52
53
73
108
128
129
I
Ground reference for input buffers. All VSSL pins must be attached to the common-system ground
plane.
VSS
11
19
62
91
134
I
Ground connections for output buffers. All VSS pins must be attached to system ground plane.
NC
1
10
35
71
88
90
107
109
NAME
NO.
ADVANCE INFORMATION
These pins should be left unconnected.
† I = input, O = output
16
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
architecture
The major blocks of the TI380C27 include the communications processor (CP), system interface (SIF), memory
interface (MIF), protocol handler (PH), clock generator (CG), and adapter support function (ASF). The
functionality of each block is described in the following sections.
communications processor (CP)
The CP performs the control and monitoring of the other functional blocks in the TI380C27. The control and
monitoring protocols are specified by the software (downloaded or ROM based) in local memory. Available
protocols include:
•
•
•
Media access control (MAC) software
Logical link control (LLC) software (token-ring mode only)
Copy all frames (CAF) software
system interface (SIF)
The SIF performs the interfacing of the LAN subsystem to the host system. This interface may require additional
logic depending on the application. The system interface can transfer information/data using any of these three
methods:
•
•
•
Direct memory access (DMA)
Direct input / output (DIO)
Pseudo-direct memory access (PDMA)
DMA (or PDMA) is used to transfer all data to/from host memory from/to local memory. The main uses of DIO
are for loading the software to local memory and for initializing the TI380C27. DIO also allows command/status
interrupts to occur to and from the TI380C27.
The system interface can be hardware selected for either of two modes by use of SI/M. The mode selected
determines the memory organizations and control signals used. These modes are:
•
•
The Intel 80x8x families: 8-, 16-, and 32-bit bus devices
The Motorola 68xxx microprocessor family: 16- and 32-bit bus devices
The system interface supports host-system memory addressing up to 32 bits (32-bit reach into the host-system
memory). This allows greater flexibility in using/accessing host-system memory. System designers are allowed
to customize the system interface to their particular bus by:
•
•
Programmable burst transfers or cycle-steal DMA operations
Optional parity protection
These features are implemented in hardware to reduce system overhead, facilitate automatic rearbitration of
the bus after a burst, or repeat a cycle when errors occur (parity or bus). Bus retries are also supported.
The system-interface hardware also includes features to enhance the integrity of the TI380C27 and the data.
These features include the following:
•
•
•
Always internally maintain odd-byte parity regardless of parity being disabled
Monitor for the presence of a clock failure
Switchable SIF speeds of 2 MHz to 33 MHz
On every cycle, the system interface compares all the system clocks to a reference clock. If any of the clocks
become invalid, the TI380C27 enters the slow-clock mode, which prevents latch-up of the TI380C27. If the
SBCLK is invalid, any DMA cycle is terminated immediately; otherwise, the DMA cycle is completed and the
TI380C27 is placed in the slow-clock mode.
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ADVANCE INFORMATION
The CP is a proprietary 16-bit central processing unit (CPU) with data cache and a single prefetch pipe for
pipelining of instructions. These features enhance the TI380C27’s maximum performance capability to about
8 million instructions per second (MIPS), with an average of about 5 MIPS.
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
system interface (SIF) (continued)
When the TI380C27 enters the slow-clock mode, the clock that failed is replaced by a slow free-running clock
and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the
TI380C27 must be reinitialized.
For DMA with a 16-MHz clock, a continuous transfer rate of 64 megabits per second (8 Mbps) can be obtained.
For DMA with a 25-MHz clock, a continuous transfer rate of 96 megabits per second (12 Mbps) can be obtained.
For DMA with a 33 MHz clock, a continuous transfer rate of 128 megabits per second ( 16 Mbps ) can be
obtained.For 8-bit and 16-bit pseudo-DMA, the following data rates can be obtained:
LOCAL BUS SPEED
8-BIT PDMA
16-BIT PDMA
4 MHz
48 Mbps
64 Mbps
6 MHz
72 Mbps
96 Mbps
Since the main purpose of DIO is for downloading and initialization, the DIO transfer rate is not a significant
issue.
ADVANCE INFORMATION
memory interface (MIF)
The MIF performs the memory management to allow the TI380C27 to address 2M bytes in local memory.
Hardware in the MIF allows the TI380C27 to be directly connected to DRAMs without additional circuitry. This
glueless DRAM connection includes the DRAM refresh controller. The MIF also handles all internal bus
arbitration between these blocks. When required, the MIF then arbitrates for the external bus.
The MIF is responsible for the memory mapping of the CPU of a task. The memory map of DRAMs, EPROMs,
burned-in addresses (BIA), and external devices are appropriately addressed when required by the system
interface, protocol handler, or for a DMA transfer.
The memory interface is capable of a 64-Mbps continuous transfer rate when using a 4-MHz local bus ( 64-MHz
device crystal ) and a 96-Mbps continuous transfer rate when using a 6-MHz local bus.
protocol handler (PH)
The PH performs the hardware-based real-time protocol functions for a token-ring or an Ethernet LAN. Network
type is determined by TEST0 – TEST2. Token-ring network is determined by software and can be either 16 Mbps
or 4 Mbps. The Ethernet network can be either full duplex or half duplex. These speeds are not fixed by the
hardware but by the software.
The PH converts the parallel-transmit data to serial-network data of the appropriate coding and converts the
received serial data to parallel data. The PH data-management state machines direct the
transmission/reception of data to / from local memory through the MIF. The PH’s buffer-management state
machines automatically oversee this process, directly sending/receiving linked lists of frames without CPU
intervention.
The protocol handler contains many state machines that provide the following features:
•
•
•
•
•
•
•
•
•
18
Transmit and receive frames
Capture tokens (token ring)
Provide token-priority controls (token ring)
Automatic retry of frame transmissions after collisions ( Ethernet)
Implement the random exponential backoff algorithm ( Ethernet)
Manage the TI380C27 buffer memory
Provide frame-address recognition (group, specific, functional, and multicast)
Provide internal parity protection
Control and verify the PHY-layer circuitry-interface signals
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
protocol handler (PH) (continued)
Integrity of the transmitted and received data is assured by cyclic redundancy checks (CRC), detection of
network data violations, and parity on internal data paths. All data paths and registers are optionally parity
protected to assure functional integrity.
adapter support function (ASF)
The ASF performs support functions not contained in the other blocks. The features are:
•
•
•
•
The TI380C27 base timer
Identification, management, and service of internal and external interrupts
Test-pin mode control, including the unit-in-place mode for board testing
Checks for illegal states, such as illegal opcodes and parity
The CG performs the generation of all the clocks required by the other functional blocks, including the local
memory-bus clocks (MBCLK1, MBCLK2). The CG also generates the reference timer used to sample all input
clocks (SBCLK, OSCIN, RCLK, and PXTALIN). If no transition is detected within the period of the reference timer
on any input clock signal, the CG places the TI380C27 into slow-clock mode. The frequency of the reference
timer is in the range of 10 kHz – 100 kHz.
user-accessible hardware registers and TI380C27-internal pointers
The following tables show how to access internal data via pointers and how to address the registers in the host
interface. The SIFACL register, which directly controls device operation, is described in detail. The
adapter-internal pointers table on the following page is defined only after TI380C27 initialization and until the
OPEN command is issued. These pointers are defined by the TI380C27 software (microcode), and this table
describes the release 1.xx and 2.x software.
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19
ADVANCE INFORMATION
clock generator (CG)
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Adapter-Internal Pointers for Token Ring †
ADDRESS
DESCRIPTION
> 00.FFF8‡
> 00.FFFA‡
Pointer to software raw microcode level in chapter 0
Pointer to starting location of copyright notices. Copyright notices are separated by a > 0A character and
terminated by a > 00 character in chapter 0.
> 01.0A00
Pointer to burned-in address in chapter 1
> 01.0A02
Pointer to software level in chapter 1
> 01.0A04
Pointer to TI380C27 addresses in chapter 1:
Pointer + 0 node address
Pointer + 6 group address
Pointer + 10 functional address
> 01.0A06
ADVANCE INFORMATION
Pointer to TI380C27 parameters in chapter 1:
Pointer + 0 physical-drop number
Pointer + 4 upstream neighbor address
Pointer + 10 upstream physical-drop number
Pointer + 14 last ring-poll address
Pointer + 20 reserved
Pointer + 22 transmit access priority
Pointer + 24 source class authorization
Pointer + 26 last attention code
Pointer + 28 source address of the last received frame
Pointer + 34 last beacon type
Pointer + 36 last major vector
Pointer + 38 ring status
Pointer + 40 soft-error timer value
Pointer + 42 ring-interface error counter
Pointer + 44 local ring number
Pointer + 46 monitor error code
Pointer + 48 last beacon-transmit type
Pointer + 50 last beacon-receive type
Pointer + 52 last MAC frame correlator
Pointer + 54 last beaconing-station UNA
Pointer + 60 reserved
Pointer + 64 last beaconing-station physical-drop number
> 01.0A08
Pointer to MAC buffer (a special buffer used by the software to transmit adapter generated MAC frames) in chapter 1
> 01.0A0A
Pointer to LLC counters in chapter 1:
Pointer + 0 MAX_SAPs
Pointer + 1 open SAPs
Pointer + 2 MAX_STATIONs
Pointer + 3 open stations
Pointer + 4 available stations
Pointer + 5 reserved
> 01.0A0C
Pointer to 4-/16-Mbps word flag. If zero, the adapter is set to run at 4 Mbps. If nonzero, the adapter is set to run at 16 Mbps.
> 01.0A0E
Pointer to total TI380C27 RAM found in 1K bytes in RAM allocation test in chapter 1
† This table describes the pointers for release 2.x of the TI380C27 software.
‡ This address valid only for microcode release 2.x
20
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
Adapter-Internal Pointers for Ethernet †
ADDRESS
DESCRIPTION
> 00.FFF8‡
> 00.FFFA‡
Software raw-microcode level in chapter 0
> 01.0A00
Pointer to burned-in address in chapter 1
> 01.0A02
Pointer to software level in chapter 1
> 01.0A04
Pointer to TI380C27 addresses in chapter 1:
Pointer + 0 node address
Pointer + 6 group address
Pointer + 10 functional address
> 01.0A08
Pointer to MAC buffer (a special buffer used by the software to transmit adapter generated MAC frames) in chapter 1
> 01.0A0A
Pointer to LLC counters in chapter 1:
Pointer + 0 MAX_SAPs
Pointer + 1 open SAPs
Pointer + 2 MAX_STATIONs
Pointer + 3 open stations
Pointer + 4 available stations
Pointer + 5 reserved
> 01.0A0C
Pointer to 4-/16-Mbps word flag. If zero, the adapter is set to run at 4 Mbps. If nonzero, the adapter is set to run at 16 Mbps.
> 01.0A0E
Pointer to total TI380C27 RAM found in 1K bytes in RAM allocation test in chapter 1
† This table describes the pointers for release 2.x of the TI380C27 software.
‡ This address valid only for microcode release 2.x
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21
ADVANCE INFORMATION
Pointer to starting location of copyright notices. Copyright notices are separated by a > 0A character and
terminated by a > 00 character in chapter 0.
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
User-Access Hardware Registers
80x8x 16-BIT MODE: (SI/M = 1, S8/SHALT = 0)†
NORMAL MODE
SBHE = 0
SRS2 = 0
WORD TRANSFERS
BYTE TRANSFERS
SRSX
SRS0
SRS1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PSEUDO-DMA MODE ACTIVE
SBHE = 0
SRS2 = 0
SBHE = 0
SRS2 = 1
SBHE = 1
SRS2 = 0
SBHE = 0
SRS2 = 1
SBHE = 1
SRS2 = 0
SIFDAT MSB
SIFDAT/INC MSB
SIFADR MSB
SIFCMD
SIFACL MSB
SIFADR MSB
SIFADX MSB
DMALEN MSB
SIFDAT LSB
SIFDAT/INC LSB
SIFADR LSB
SIFSTS
SIFACL LSB
SIFADR LSB
SIFADX LSB
DMALEN LSB
SDMADAT MSB
DMALEN MSB
SDMAADR MSB
SDMAADX MSB
SIFACL MSB
SIFADR MSB
SIFADX MSB
DMALEN MSB
SDMADAT LSB
DMALEN LSB
SDMAADR LSB
SDMAADX LSB
SIFACL LSB
SIFADR LSB
SIFADX LSB
DMALEN LSB
† SBHE = 1 and SRS2 = 1 are not defined.
ADVANCE INFORMATION
80x8x 8-BIT MODE: (SI/M = 1, S8/SHALT = 1)
SRSX
SRS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SRS1
NORMAL MODE
SBHE = X
SRS2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PSEUDO-DMA MODE ACTIVE
SBHE = X
SIFDAT LSB
SIFDAT MSB
SIFDAT/INC LSB
SIFDAT/INC MSB
SIFADR LSB
SIFADR MSB
SIFSTS
SIFCMD
SIFACL LSB
SIFACL MSB
SIFADR LSB
SIFADR MSB
SIFADX LSB
SIFADX MSB
DMALEN LSB
DMALEN MSB
SDMADAT LSB
SDMADAT MSB
DMALEN LSB
DMALEN MSB
SDMAADR LSB
SDMAADR MSB
SDMAADX LSB
SDMAADX MSB
SIFACL LSB
SIFACL MSB
SIFADR LSB
SIFADR MSB
SIFADX LSB
SIFADX MSB
DMALEN LSB
DMALEN MSB
68xxx MODE: (SI/M = 0)‡
NORMAL MODE
SUDS = 0
SLDS = 0
WORD TRANSFERS
BYTE TRANSFERS
SRSX
SRS0
SRS1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PSEUDO-DMA MODE ACTIVE
SUDS = 0
SLDS = 0
SUDS = 0
SLDS = 1
SUDS = 1
SLDS = 0
SUDS = 0
SLDS = 1
SUDS = 1
SLDS = 0
SIFDAT MSB
SIFDAT/INC MSB
SIFADR MSB
SIFCMD
SIFACL MSB
SIFADR MSB
SIFADX MSB
DMALEN MSB
SIFDAT LSB
SIFDAT/INC LSB
SIFADR LSB
SIFSTS
SIFACL LSB
SIFADR LSB
SIFADX LSB
DMALEN LSB
SDMADAT MSB
DMALEN MSB
SDMAADR MSB
SDMAADX MSB
SIFACL MSB
SIFADR MSB
SIFADX MSB
DMALEN MSB
SDMADAT LSB
DMALEN LSB
SDMAADR LSB
SDMAADX LSB
SIFACL LSB
SIFADR LSB
SIFADX LSB
DMALEN LSB
‡ 68xxx mode is always 16 bit.
22
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SIF adapter-control register (SIFACL)
The SIFACL register allows the host processor to control and to some extent reconfigure the TI380C27 under
software control.
Bit #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
E
S
T
0
T
E
S
T
1
T
E
S
T
2
—
SWHLDA
SWDDIR
SWHRQ
PSDMAEN
ARESET
CPHALT
BOOT
LBP
SINTEN
PEN
NSEL
OUT0
NSEL
OUT1
RP – 0
R –u
R –0
RS – 0
RW – 0
RP – b
RP – b
RW – 0
RW – 1
RP – p
RP – 0
RP – 1
R R R
Legend:
R
=
W =
P
=
S
=
–n =
b
=
p
=
u
=
Read
Write
Write during ARESET = 1 only
Set only
Value after reset
Value on BTSTRP
Value on PRTYEN
Indeterminate
Bits 0 – 2:
Value on TEST0 – TEST2 pins
These bits are read only and always reflect the value on the corresponding device pins. This
allows the host S/W to determine the network type and speed configuration. If the network speed
and type are software configurable, these bits can be used to determine which configurations
are supported by the network hardware.
TEST0
TEST1
TEST2
L
L
H
H
X
L
H
L
H
X
H
H
H
H
L
Description
Full-duplex Ethernet
16-Mbps token ring
Half-duplex Ethernet
4-Mbps token ring
Reserved
Bit 3:
Reserved. Read data is indeterminate.
Bit 4:
SWHLDA — Software Hold Acknowledge
This bit allows the function of SHLDA / SBGR to be emulated from software control for
pseudo-DMA mode.
PSDMAEN
SWHLDA
SWHRQ
0†
X
X
SWHLDA value in the SIFACL register cannot be set to a one.
RESULT
1†
0
0
No pseudo-DMA request pending
1†
0
1
Indicates a pseudo-DMA request interrupt
1†
1
X
Pseudo-DMA process in progress
† The value on SHLDA / SBGR is ignored.
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23
ADVANCE INFORMATION
SIFACL Register
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SIF adapter-control register (SIFACL) (continued)
Bit 5:
SWDDIR — Current SDDIR Signal Value
This bit contains the current value of the pseudo-DMA direction. This enables the host to easily
determine the direction of DMA transfers, which allows system DMA to be controlled by system
software.
0 = Pseudo DMA from host system to TI380C27
1 = Pseudo DMA from TI380C27 to host system
Bit 6:
SWHRQ — Current SHRQ Signal Value
0
1
Bit 7:
INTEL MODE (SI/M = H)
= System bus not requested
= System bus requested
MOTOROLA MODE (SI/M = L)
System bus not requested
System bus requested
PSDMAEN — Pseudo-System-DMA Enable
This bit enables pseudo-DMA operation.
0 = Normal bus-master DMA operation is possible.
1 = Pseudo-DMA operation selected. Operation dependent on the values of SWHLDA and
SWHRQ bits in the SIFACL register.
Bit 8:
ARESET — Adapter Reset
This bit is a hardware reset of the TI380C27. This bit has the same effect as SRESET except
that the DIO interface to the SIFACL register is maintained. This bit is set to 1 if a clock failure
is detected (OSCIN, PXTALIN, RCLK, or SBCLK not valid).
0 = The TI380C27 operates normally.
1 = The TI380C27 is held in the reset condition.
Bit 9:
CPHALT — Communications-Processor Halt
This bit controls TI380C27’s processor access to the internal TI380C27 buses. This prevents the
TI380C27 from executing instructions before the microcode has been downloaded.
0 = The TI380C27 processor can access the internal TI380C27 buses.
1 = The TI380C27 processor is prevented from accessing the internal adapter buses.
Bit 10:
BOOT — Bootstrap CP Code
This bit indicates whether the memory in chapters 0 and 31 of the local-memory space is RAM
or ROM/PROM/EPROM. This bit controls the operation of MCAS and MROMEN.
0 = ROM/PROM/EPROM memory in chapters 0 and 31
1 = RAM memory in chapters 0 and 31
24
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ADVANCE INFORMATION
This bit contains the current value on SHRQ/SBRQ when in Intel mode, and the inverse of the
value on SHRQ/SBRQ in Motorola mode. This enables the host to easily determine if a
pseudo-DMA transfer is requested.
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SIF adapter-control register (SIFACL) (continued)
Bit 11:
LBP – Local-Bus Priority
This bit controls the priority levels of devices on the local bus.
0 = No external devices (such as the TI380FPA) are used with the TI380C27.
1 = An external device (such as the TI380FPA) is used with the TI380C27. This allows the
external bus master to operate at the necessary priorities on the local bus.
If the system uses the TMS380SRA only, the bit must be set to 0. If the system uses both the
TMS380SRA and the TI380FPA, this bit must be set to 1.
SINTEN — System-Interrupt Enable
This bit allows the host processor to enable or disable system-interrupt requests from the
TI380C27. The system-interrupt request from the TI380C27 is on SINTR/SIRQ. The following
equation shows how SINTR/SIRQ is driven. The table also explains the results of the states.
SINTR/SIRQ = (PSDMAEN * SWHRQ * !SWHLDA) + (SINTEN * SYSTEM_INTERRUPT)
PSDMAEN
SWHRQ
SWHLDA
SINTEN
SYSTEM
INTERRUPT
(SIFSTS
REGISTER)
1†
1†
1
1
X
X
Pseudo DMA is active.
1
0
X
X
The TI380C27 generated a system interrupt for a pseudo DMA.
1†
0
0
X
X
Not a pseudo-DMA interrupt.
X
X
X
1
1
The TI380C27 generates a system interrupt.
0
X
X
1
0
The TI380C27 does not generate a system interrupt.
0
X
X
0
X
The TI380C27 cannot generate a system interrupt.
RESULT
† The value on SHLDA / SBGR is ignored.
Bit 13:
PEN — Parity Enable
This bit determines whether data transfers within the TI380C27 are checked for parity.
0 = Data transfers are not checked for parity.
1 = Data transfers are checked for correct odd parity.
Bit 14 – 15:
NSELOUT0, NSELOUT0 1 — Network-Selection Outputs
The values in these bits control NSELOUT0 and NSELOUT1. These bits can be modified only
while the ARESET bit is set.
These bits can be used to software configure a multiprotocol TI380C27 as follows: NSELOUT0
and NSELOUT1 should be connected to TEST0 and TEST1, respectively (TEST2 should be left
unconnected or tied high). NSELOUT0 is used to select network speed and NSELOUT1 is used
to select network type as shown in the table below:
NSELOUT0
NSELOUT1
SELECTION
0
0
Full-duplex Ethernet
0
1
16-Mbps token ring
1
0
Half-duplex Ethernet
1
1
4-Mbps token ring
At power up, these bits are set corresponding to 16-Mbps token ring (NSELOUT1 = 1,
NSELOUT0 = 0).
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25
ADVANCE INFORMATION
Bit 12:
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SIFACL control for pseudo-DMA operation
Pseudo DMA is software controlled by the use of five bits in the SIFACL register. The logic model for the SIFACL
register control of pseudo-DMA operation is shown in Figure 2.
Motorola Mode
Internal
Signals
Host
Interface
SYSTEM_INTERRUPT
(SIFSTS register)
DMA
Request
M
U
X
SINTR/SIRQ
M
U
X
SHRQ/SBRQ
SHLDA/SBGR
ADVANCE INFORMATION
M
U
X
DMA
Grant
SDDIR
DMADIR
...
SWHLDA
SWDDIR
SWHRQ
. . . PSDMAEN SINTEN
SIFACL Register
Figure 2. Pseudo-DMA Logic Related to SIFACL Bits
26
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...
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range (see Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 20 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 2 V to 7 V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 8: Voltage values are with respect to VSS.
VDD
VSS
Supply voltage
Supply voltage (see Note 9)
TTL-level signal
VIH
High-level input voltage
VIL
IOH
Low-level input voltage, TTL-level signal (see Note 10)
IOL
TA
Low-level output current (see Note 11)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0
0
0
V
2
OSCIN
2.4
RCLK, PXTALIN, RCVR
2.6
– 0.3
VDD + 0.3
VDD + 0.3
V
VDD + 0.3
0.8
V
High-level output current
Operating free-air temperature
0
– 400
µA
2
mA
70
°C
TC
Operating case temperature
100
°C
NOTES: 9. All VSS pins should be routed to minimize inductance to system ground.
10. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
11. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
VOH
VOL
High-level output voltage, TTL-level signal (see Note 12)
Low-level output voltage, TTL-level signal
IO
High impedance output current
High-impedance
II
IDD
Input current, any input or input / output
ISCM
Ci
Supply current, slow-clock mode
Supply current
VDD = MIN,
VDD = MIN,
IOH = MAX
IOL = MAX
VDD = MAX,
VDD = MAX,
VO = 2.4 V
VO = 0.4 V
TYP
MAX
2.4
20
– 20
V
µA
± 20
µA
160
mA
3
Others at 0 V
UNIT
V
0.6
VI = VSS to VDD
VDD = MAX
VDD = 5 V
f = 1 MHz,
Input capacitance, any input
MIN
mA
15
pF
Co
Output capacitance, any output or input / output
f = 1 MHz,
Others at 0 V
15
pF
‡ For conditions shown as MIN or MAX, use the appropriate value specified under the recommended operating conditions.
NOTE 12: The following signals require an external pullup resistor: SRAS/SAS, SRDY/SDTACK, SRD/SUDS, SWR/SLDS, EXTINT0 – EXTINT3,
and MBRQ.
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27
ADVANCE INFORMATION
recommended operating conditions
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
timing parameters
The timing parameters for all the signals of TI380C27 are shown in the following tables and are illustrated in
the accompanying figures. The purpose of these figures and tables is to quantify the timing relationships among
the various signals. The parameters are numbered for convenience.
static signals
The following table lists signals that are not allowed to change dynamically and therefore have no timing
associated with them. They should be strapped high, low, or left unconnected as required.
SIGNAL
FUNCTION
ADVANCE INFORMATION
SI/M
Host-processor select (Intel/Motorola)
CLKDIV
Reserved
BTSTRP
Default bootstrap mode (RAM/ROM)
PRTYEN
Default parity select (enabled/disabled)
TEST0
Test terminal indicates network type
TEST1
Test terminal indicates network type
TEST2
Test terminal indicates network type
TEST3
Test terminal for TI manufacturing test †
Test terminal for TI manufacturing test †
TEST4
TEST5
Test terminal for TI manufacturing test †
† For unit-in-place test
timing parameter symbology
Some timing parameter symbols have been created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, some of the signal names and other related terminology have been abbreviated as shown
below:
DR
DRVR
RS
SRESET
DRN
DRVR
VDD
VDDL, VDD
OSC
OSCIN
SCK
SBCLK
Lower case subscripts are defined as follows:
c
cycle time
r
d
delay time
sk
h
hold time
su
w
pulse duration (width)
rise time
skew
setup time
t
transition time
The following additional letters and phrases are defined as follows:
28
H
High
Z
L
Low
Falling edge
No longer high
V
Valid
Rising edge
No longer low
POST OFFICE BOX 1443
High impedance
• HOUSTON, TEXAS 77251–1443
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
PARAMETER MEASUREMENT INFORMATION
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels
are compatible with TTL devices.
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,
the level at which the signal is said to be no longer high is 2 V, and the level at which the signal is said to be low
is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level
at which the signal is said to be high is 2 V, as shown below.
The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically
1.5 ns.
2 V (high)
test measurement
The test-load circuit shown in Figure 3 represents the programmable load of the tester pin electronics that are
used to verify timing parameters of TI380C27 output signals.
Tester Pin
Electronics
IOL
Output
Under
Test
VLOAD
CT
IOH
Where: IOL
IOH
VLOAD
CT
= 2 mA, dc-level verification (all outputs)
= 400 µA (all outputs)
= 1.5 V, typical dc-level verification or
0.7 V, typical timing verification
= 65 pF, typical load-circuit capacitance
Figure 3. Test-Load Circuit
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29
ADVANCE INFORMATION
0.8 V (low)
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
power up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, and SRESET timing
NO.
100†
101†‡
102†‡
103
104
105
106†
107
108
109
MIN
NOM
MAX
UNIT
tr(VDD)
td(VDDH-SCKV)
Rise time, 1.2 V to minimum VDD-high level
1
ms
Delay time, minimum VDD-high level to first valid SBCLK no longer high
1
ms
td(VDDH-OSCV)
tc(SCK)
Delay time, minimum VDD-high level to first valid OSCIN high
1
ms
30.3
500
ns
tw(SCKH)
tw(SCKL)
Pulse duration, SBCLK high
13
500
ns
Pulse duration, SBCLK low
13
500
ns
tt(SCK)
tc(OSC)
Transition time, SBCLK
2
ns
tw(OSCH)
(
)
tw(OSCL)
(
)
Cycle time, SBCLK (see Note 13)
Cycle time, OSCIN (see Note 14)
1/OSCIN
Pulse duration, OSCIN high (see Note 15)
Pulse duration, OSCIN low (see Note 15)
OSCIN = 64 MHz
5.5
OSCIN = 48 MHz
8
OSCIN = 32 MHz
8
ADVANCE INFORMATION
OSCIN = 64 MHz
5.5
OSCIN = 48 MHz
8
OSCIN = 32 MHz
8
ns
ns
ns
110†
111†
tt(OSC)
td(OSCV-CKV)
Transition time, OSCIN
3
ns
Delay time, OSCIN valid to MBCLK1 and MBCLK2 valid
1
ms
117†
118†
th(VDDH-RSL)
tw(RSH)
Hold time, SRESET low after VDD reaches minimum high level
119†
288†
tw(RSL)
tsu(RST)
289†
th(RST)
tM
5
ms
Pulse duration, SRESET high
14
µs
Pulse duration, SRESET low
14
µs
Setup time, DMA size to SRESET high (Intel mode only)
10
ns
Hold time, DMA size from SRESET high (Intel mode only)
10
ns
2tc(OSC)
tc(OSC)
ns
One eighth of a local memory cycle
One-eighth
CLKDIV = H
CLKDIV = L
† This specification is provided as an aid to board design. It is not assured during manufacturing testing.
‡ If parameter 101 or 102 cannot be met, parameter 117 must be extended by the larger difference: real value of parameter 101 or 102 minus the
max value listed.
NOTES: 13. SBCLK can be any value between 2 MHz to 33 MHz. This data sheet describes the system interface ( SIF ) timing parameters for
the case of SBCLK at 25 MHz and at 33 MHz.
14. The value of OSCIN can be 64 MHz ± 1%, 32 MHz ± 1%, or 48 MHz ± 1%. If OSCIN is used to generate PXTALIN, the OSCIN
tolerance must be ± 0.01%.
15. This is to assure a ± 5% duty-cycle crystal, provided that OSCIN meets the recommended operating conditions for VIH and VIL .
30
POST OFFICE BOX 1443
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
100
Minimum VDD-High Level
VDD
103
106
106
104
101
105
SBCLK
102
107
110
108
OSCIN
110
109
MBCLK1
111
118
117
119
SRESET
288
289
S8/SHALT
NOTE A: In order to represent the information is one illustration, nonactual phase and timebase characteristics are shown. Refer to specified
parameters for precise information.
Figure 4. Timing for Power Up, System Clocks, SYNCIN, and SRESET
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31
ADVANCE INFORMATION
MBCLK2
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
memory-bus timing: local-memory clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS
tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
NO.
MIN
1
Period of MBCLK1 and MBCLK2
2
Pulse duration, clock high
3
Pulse duration, clock low
4
Hold time, MBCLK2 low after MBCLK1 high
5
Hold time, MBCLK1 high after MBCLK2 high
6
Hold time, MBCLK2 high after MBCLK1 low
7
Hold time, MBCLK1 low after MBCLK2 low
8
Setup time, address/enable on MAX0, MAX2, and MROMEN before MBCLK1 no longer high
MAX
UNIT
ADVANCE INFORMATION
4tM
2tM – 9
2tM – 9
ns
tM – 9
tM – 9
ns
tM – 9
tM – 9
ns
tM – 9
tM – 14
ns
tM – 14
13
ns
ns
ns
ns
ns
9
Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MBCLK1 no longer high
10
Setup time, address on MADH0 – MADH7 before MBCLK1 no longer high
11
Setup time, MAL high before MBCLK1 no longer high
12
Setup time, address on MAX0, MAX2, and MROMEN before MBCLK1 no longer low
0.5tM – 9
ns
13
Setup time, column address on MADL0 – MADL7, MAXPH, and MAXPL before MBCLK1 no
longer low
0.5tM – 9
ns
14
Setup time, status on MADH0 – MADH7 before MBCLK1 no longer low
ns
120
Setup time, NMI valid before MBCLK1 low
0.5tM – 9
30
121
Hold time, NMI valid after MBCLK1 low
0
126
Delay time, MBCLK1 no longer low to MRESET valid
0
129
Hold time, column address/status after MBCLK1 no longer low
Reference
4 Periods
8 Periods
tM – 7
12 Periods
16 Periods
ns
ns
ns
ns
20
ns
ns
20 Periods
OSCIN
(when CLKDIV = 1)
OSCIN
(when CLKDIV = 0)
OSCOUT
MBCLK1
See Note A
MBCLK2
See Note A
NOTE A: MBCLK1 and MBCLK2 have no timing relationship to OSCOUT. MBCLK1 and MBCLK2 can start on any OSCIN rising edge,
depending on when the memory cycle starts execution.
Figure 5. Clock Waveforms After Clock Stabilization
32
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
M8
M1
M2
M4
M3
M5
M6
M7
M8
M1
1
tM
3
MBCLK1
4
6
2
1
5
7
3
MBCLK2
8
2
12
ADD/EN
Address
9
MAXPH,
MAXPL,
MADL0 – MADL7
13
Row
Col
14
10
Address
MADH0 – MADH7
ADVANCE INFORMATION
MAX0,
MAX2,
MROMEN
Status
11
129
MAL
120
NMI
121
Valid
126
MRESET
Valid
Figure 6. Memory-Bus Timing: Local-Memory Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and
ADDRESS
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33
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
memory-bus timing: clocks, MRAS, MCAS, and MAL to ADDRESS
tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
NO.
ADVANCE INFORMATION
34
MIN
15
Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MRAS no longer
high
16
Hold time, row address on MADL0 – MADL7, MAXPH, and MAXPL after MRAS no longer high
17
Delay time, MRAS no longer high to MRAS no longer high in the next memory cycle
18
Pulse duration, MRAS low
19
1.5tM – 11.5
MAX
UNIT
ns
tM – 6.5
8tM
ns
ns
Pulse duration, MRAS high
4.5tM – 5
3.5tM – 5
20
Setup time, column address (MADL0 – MADL7, MAXPH, and MAXPL) and status
(MADH0 – MADH7) before MCAS no longer high
0.5tM – 9
ns
21
Hold time, column address (MADL0 – MADL7, MAXPH, and MAXPL) and status
(MADH0 – MADH7) after MCAS low
tM – 5
ns
22
Hold time, column address (MADL0 – MADL7, MAXPH, and MAXPL) and status
(MADH0 – MADH7) after MRAS no longer high
2.5tM – 6.5
ns
23
Pulse duration, MCAS low
ns
24
Pulse duration, MCAS high, refresh cycle follows read or write cycle
3tM – 9
2tM – 9
25
Hold time, row address on MAXL0 – MAXL7, MAXPH, and MAXPL after MAL low
ns
26
Setup time, row address on MAXL0 – MAXL7, MAXPH, and MAXPL before MAL no longer high
1.5tM – 9
tM – 9
27
Pulse duration, MAL high
Setup time, address/enable on MAX0, MAX2, and MROMEN before MAL no longer high
tM – 9
tM – 9
ns
28
29
Hold time, address/enable of MAX0, MAX2, and MROMEN after MAL low
Setup time, address on MADH0 – MADH7 before MAL no longer high
1.5tM – 9
tM – 9
ns
30
31
Hold time, address on MADH0 – MADH7 after MAL low
1.5tM – 9
ns
POST OFFICE BOX 1443
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ns
ns
ns
ns
ns
ns
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
MAXPH,
MAXPL,
MADL0 – MADL7
Row
Column
Column
Row
16
26
17
22
15
19
18
MRAS
21
20
24
23
MCAS
25
27
MAL
28
29
ADD/EN
Address
ADVANCE INFORMATION
MAX0,
MAX2,
MROMEN
21
30
31
20
MADH0 – MADH7
Address
Status
Address
Status
22
Figure 7. Memory-Bus Timing: Clocks, MRAS, MCAS, and MAL to ADDRESS
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35
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
memory-bus timing: read cycle
tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
NO.
MIN
ADVANCE INFORMATION
32
Access time, address / enable valid on MAX0, MAX2, and MROMEN to valid data /parity
33
Access time, address valid on MAXPH, MAXPL, MADH0 – MADH7, and MADL0 – MADL7 to
valid data / parity
35
Access time, MRAS low to valid data / parity
36
Hold time, valid data / parity after MRAS no longer low
37†
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7 and
MADL0 – MADL7 after MRAS high (see Note 16)
38
Access time, MCAS low to valid data / parity
39
Hold time, valid data / parity after MCAS no longer low
40†
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7, and
MADL0 – MADL7 after MCAS high (see Note 16)
41
Delay time, MCAS no longer high to MOE low
42†
Setup time, address / status in the high-impedance state on MAXPH, MAXPL,
MADL0 – MADL7, and MADH0 – MADH7 before MOE no longer high
43
Access time, MOE low to valid data / parity
44
Pulse duration, MOE low
45
Delay time, MCAS low to MOE no longer low
46
Hold time, valid data / parity in after MOE no longer low
47†
MAX
UNIT
6tM – 23
ns
6tM – 23
ns
4.5tM – 21.5
ns
0
ns
2tM – 10.5
ns
3tM – 23
ns
0
ns
2tM –13
ns
tM +13
0
ns
ns
2tM – 20
ns
2tM – 9
3tM – 9
ns
0
ns
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7, and
MADL0 – MADL7 after MOE high (see Note 16)
2tM – 15
ns
48†
Setup time, address / status in the high-impedance state on MAXPH, MAXPL,
MADL0 – MADL7, and MADH0 – MADH7, before MBEN no longer high
0
ns
48a†
Setup time, address / status in the high-impedance state on MAXPH, MAXPL,
MADL0 – MADL7, and MADH0 – MADH7 and before MBIAEN no longer high
0
ns
49
Access time, MBEN low to valid data / parity
49a
Access time, MBIAEN low to valid data / parity
50
Pulse duration, MBEN low
50a
Pulse duration, MBIAEN low
51
ns
2tM – 25
2tM – 25
ns
ns
2tM – 9
2tM – 9
ns
Hold time, valid data / parity after MBEN no longer low
0
ns
51a
Hold time, valid data / parity after MBIAEN no longer low
0
ns
52†
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7, and
MADL0 – MADL7 after MBEN high (see Note 16)
2tM – 15
ns
52a†
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 – MADH7, and
MADL0 – MADL7 after MBIAEN high
2tM – 15
ns
1.5tM – 12
3tM – 5
ns
53
Hold time, MDDIR high after MBEN high, read follows write cycle
54
Setup time, MDDIR low before MBEN no longer high
ns
ns
55
Hold time, MDDIR low after MBEN high, write follows read cycle
3tM – 12
ns
† This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTE 16: The data / parity that exists on the address lines will most likely reach the high-impedance state sometime later than the rising edge
of MRAS, MCAS, MOE, or MBEN (between MIN and MAX of timing parameter 36) and will be a function of the memory being read.
The MIN time given represents the time from the rising edge of MRAS, MCAS, MOE, or MBEN to the beginning of the next address,
and does not represent the actual high-impedance period on the address bus.
36
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
MAX0,
MAX2,
MROMEN
Address /
Enable
Address
Data / Parity
32
MAXPH, MAXPL,
MADH0 – MADH7,
MADL0 – MADL7
Address /
Status
Address
Address
33
36
37
35
MRAS
38
39
40
ADVANCE INFORMATION
MCAS
43
45
41
46
42
47
44
MOE
49a
48a
51a
52a
50a
MBIAEN
49
51
48
52
MBEN
50
53
54
55
MDDIR
Figure 8. Memory-Bus Timing: Read Cycle
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37
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
memory-bus timing: write cycle
tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
NO.
MIN
ADVANCE INFORMATION
58
Setup time, MW low before MRAS no longer low
60
Setup time, MW low before MCAS no longer low
63
Setup time, valid data / parity before MW no longer high
64
Pulse duration, MW low
65
Hold time, data / parity out valid after MW high
66
Setup time, address valid on MAX0, MAX2, and MROMEN before MW no longer low
67
Hold time, MRAS low to MW no longer low
69
Hold time, MCAS low to MW no longer low
70
Setup time, MBEN low before MW no longer high
71
Hold time, MBEN low after MW high
72
Setup time, MDDIR high before MBEN no longer high
73
Hold time, MDDIR high after MBEN high
MAX0,
MAX2,
MROMEN
MAXPH, MAXPL,
MADH0 – MADH7,
MADL0 – MADL7
Address /
Enable
ADD / STS
ns
2.5tM – 9
0.5tM – 10.5
7tM –11.5
ns
5.5tM – 9
4tM –11.5
ns
1.5tM – 13.5
0.5tM – 6.5
ns
2tM – 9
1.5tM – 12
ns
Data / Parity Out
MRAS
58
MCAS
60
65
63
64
MW
69
67
66
70
71
MBEN
72
73
MDDIR
Figure 9. Memory-Bus Timing: Write Cycle
38
POST OFFICE BOX 1443
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UNIT
tM
1.5tM – 6.5
5.1
Address
Address
MAX
ns
ns
ns
ns
ns
ns
ns
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
memory-bus timing: DRAM-refresh timing
tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
MIN
15
Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MRAS no longer high
16
Hold time, row address on MADL0 – MADL7, MAXPH, and MAXPL after MRAS no longer high
18
Pulse duration, MRAS low
19
Pulse duration, MRAS high
73a
Setup time, MCAS low before MRAS no longer high
73b
Hold time, MCAS low after MRAS low
73c
Setup time, MREF high before MCAS no longer high
73d
Hold time, MREF high after MCAS high
Refresh
Address
MADL0 – MADL7
MAX
UNIT
1.5tM – 11.5
tM – 6.5
ns
4.5tM – 5
3.5tM – 5
ns
1.5tM –11.5
4.5tM – 6.5
ns
ns
ns
ns
14
ns
tM – 9
ns
Address
16
19
15
18
MRAS
73a
73b
MCAS
73d
73c
MREF
Figure 10. Memory Bus Timing: DRAM-Refresh Cycle
XMATCH and XFAIL timing
tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
NO.
MIN
127
Delay time, status bit 7 high to XMATCH and XFAIL recognized
128
Pulse duration, XMATCH or XFAIL high
MADH7
7tM
50
MAX
UNIT
ns
ns
Status
Bit 7
127
128
XMATCH,
XFAIL
Figure 11. XMATCH and XFAIL Timing
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39
ADVANCE INFORMATION
NO.
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
token ring: ring-interface timing
NO.
153
MIN
4Mbps
Period of RCLK (see Note 17)
154L
Pulse duration
duration, RCLK low
154H
Pulse duration,
duration RCLK high
16 Mbps
ns
4 Mbps nominal: 62.5 ns
35
ns
8
ns
10
ns
4
ns
40
ns
16 Mbps
9
ns
4 Mbps
40
ns
16 Mbps
9
ns
4 Mbps
4 Mbps
ADVANCE INFORMATION
Period of OSCOUT and PXTALIN (see Note 17)
ns
ns
Hold time, RCVR valid after rising edge (1.8 V) of RCLK at 16 Mbps
165
31.25
15
Setup time, RCVR valid before rising edge (1.8 V) of RCLK at 16 Mbps
Pulse duration,
duration ring baud clock high
ns
16 Mbps nominal: 15.625 ns
156
158H
UNIT
46
16 Mbps nominal: 15.625 ns
duration ring baud clock low
Pulse duration,
MAX
125
4 Mbps nominal: 62.5 ns
155
158L
TYP
16 Mbps (for PXTALIN only)
125
ns
31.25
ns
± 0.01
Tolerance of PXTALIN input frequency (see Note 17)
NOTE 17: This parameter is not tested but is required by the IEEE 802.5 specification.
153
154H
RCLK
154L
156
155
Valid
RCVR
158H
158L
OSCOUT,
PXTALIN
1.5 V
165
Figure 12. Ring-Interface Timing
40
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%
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
token ring: transmitter timing
NO.
MIN
Delay from DRVR rising edge (1.8 V ) to DRVR falling edge (1 V ) or DRVR falling edge
(1 V ) to DRVR rising edge (1.8 V )
MAX
±2
UNIT
159
tsk(DR)
160
td(DR)H†
td(DR)L†
Delay from RCLK (or PXTALIN) falling edge (1 V ) to DRVR rising edge (1.8 V )
See Note 18
ns
Delay from RCLK (or PXTALIN) falling edge (1 V ) to DRVR falling edge (1 V )
See Note 18
ns
td(DRN)H†
t(DRN)L†
Delay from RCLK (or PXTALIN) falling edge (1 V ) to DRVR falling edge (1 V )
See Note 18
ns
Delay from RCLK (or PXTALIN) falling edge (1 V ) to DRVR rising edge (1.8 V )
See Note 18
ns
161
162
163
164
t d(DR)L
DRVR / DRVR
asymmetry
)t
d(DRN)H
2
–
t d(DR)H
)t
±1.5
d(DRN)L
2
ns
ns
RCLK or PXTALIN
2.6 V
1.5 V
0.6 V
DRVR
2.4 V
1.5 V
0.6 V
160
ADVANCE INFORMATION
† When in active-monitor mode, the clock source is PXTALIN; otherwise, the clock-source is either RCLK or PXTALIN.
NOTE 18: This parameter is not tested to a minimum or a maximum but is measured and used as a component required for parameter 164.
161
159
159
2.4 V
1.5 V
0.6 V
DRVR
162
163
Figure 13. Skew and Asymmetry From RCLK or PXTALIN to DRVR and DRVR
ethernet timing of clock signals
NO.
MIN
300
CLKPHS
Pulse duration, TXC
45
301
CLKPER
Cycle time, TXC
95
300
MAX
UNIT
ns
1000
ns
301
1.5 V
TXC
300
Figure 14. Ethernet Timing of TXC
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41
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
ethernet timing of XMIT signals: TXD
NO.
305
306
MIN
tXDHLD
tXDVLD
Hold time, TXD after TXC high
MAX
5
Delay time, TXC high to TXD valid and TXC high to TXEN high
UNIT
ns
40
ns
TXC
305
2.4 V
TXD
0.45 V
306
306
2.4 V
TXEN
0.45 V
ADVANCE INFORMATION
Figure 15. Ethernet Timing of XMIT Signals: TXD
ethernet timing of RCV signals: start of frame
NO.
MIN
310
RXDSET
Setup time, RXD before RXC no longer low
TYP
MAX
UNIT
20
ns
5
ns
20
ns
311
RXDHLD
Hold time, RXD after RXC high
312
CRSSET
Setup time, CRS high before RXC no longer low for first valid data sample
313
SAMDLY
Delay time, CRS internally recognized to first valid data sample (see Notes 19 and 20)
314
RXCHI
Pulse duration, RXC high
36
ns
315
RXCL0
Pulse duration, RXC low
36
ns
3
clock
cycles
NOTES: 19. For valid frame synchronization, one of the following data sequences must be received. Any other pattern delays frame
synchronization until after the next CRS rising edge.
a) 0 followed by n occurrences of 10 followed by 11, where n is on integer ≥ 3. For example, if n = 3, the data sequence is
010101011.
b) 10 followed by n occurrences of 10 followed by 11, where n is an integer ≥ 3. For example, if n = 3, the data sequence is
1010101011.
20. If a previous frame or frame fragment is completed without extra RXC clock cycles (XTRCVC = 0), SAMDLY = 2 clock cycles.
312
CRS
313
314
RXC
315
RXD
311
310
Figure 16. Ethernet Timing of RCV Signals: Start Of Frame
42
POST OFFICE BOX 1443
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
ethernet timing of RCV signals: end of frame
NO.
MIN
320
CRSSET
Setup time, CRS low before RXC no longer low to determine if last data bit seen on
previous RXC no longer low (see Note 21)
321
CRSHLD
322
XTRCYC
TYP
MAX
UNIT
20
ns
Hold time, CRS low after RXC no longer low to determine if last data bit seen on
previous RXC no longer low
0
ns
Number of extra RXC clock cycles after last data bit (CRS is low) (see Note 21)
0
5
cycle
NOTE 21: The TI380C27 operates correctly even with no extra RXC clock cycles, provided that CRS does not remain asserted longer than
2 µs (see timing spec NORXC). Provided no extra clocks affect receive-startup timing, see timing spec SAMDLY.
RXC
320
321
ADVANCE INFORMATION
CRS
322
RXD
Last
Data Bit
Figure 17. Ethernet Timing of RCV Signals: End of Frame
ethernet timing of RCV signals: no RXC
NO.
330
MIN
NORXC
Time with no clock pulse on RXC, when CRS is high (see Note 22)
MAX
2
UNIT
µs
NOTE 22: If NORXC is exceeded, local-clock-failure circuitry may become activated, resetting the device.
CRS
(high)
330
RXC
Figure 18. Ethernet Timing of RCV Signals: No RXC
POST OFFICE BOX 1443
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43
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
ethernet timing of XMIT signals: COLL
NO.
MIN
340
HBWIN
Delay time from TXC high of the last transmitted data bit ( TXEN is high) to COLL
sampled high, so not to generate a heart-beat error
341
COLPUL
Minimum pulse duration of COLL high for assured sample
342
COLSET
Setup of COLL high to TXC high
MAX
UNIT
47
cycles
20 ns + 1 cycle
ns
20
ns
TXC
340
341
COLL
342
ADVANCE INFORMATION
TXD
TXEN
Figure 19. Ethernet Timing of XMIT Signals: COLL
ethernet timing of XMIT signals: JAM
NO.
MIN
350
JAMTIM
Time from COLL sampled high (TXC high) to first transmitted JAM bit on TXD
(see Note 23)
351
COLSET
Setup time, COLL high before TXC high
352
COLPUL
Pulse duration, COLL high for assured sample, minimum
MAX
UNIT
4
cycles
20
ns
20 ns + 1 cycle
ns
NOTE 23: The JAM pattern is delayed until after the completion of the preamble pattern. The TI380C27 transmits a JAM pattern of all 1s.
350
TXC
TXD
Data
Data
Data
JAM
JAM
COLL
351
352
Figure 20. Ethernet Timing of XMIT Signals: JAM
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
JAM
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
80x8x DIO read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
MIN
MIN
MAX
MAX
UNIT
255
Delay time, SRDY low to either SCS or SRD high
15
15
ns
256
Pulse duration, SRAS high
30
30
ns
259†
Hold time, SAD in the high-impedance state after SRD low
(see Note 24)
0
0
ns
260
Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL
valid before SRDY low
0
0
ns
261†
Delay time, SRD or SCS high to SAD in the high-impedance
state (see Note 24)
261a
Hold time, output data valid after SRD or SCS high (see Note 24)
0
0
ns
264
Setup time, SRSX, SRS0 – SRS2, SCS, and SBHE valid to
SRAS no longer high (see Note 25)
30
30
ns
265
Hold time, SRSX, SRS0 – SRS2, SCS, and SBHE valid after
SRAS low
10
10
ns
266a
Setup time, SRAS high to SRD no longer high (see Note 25)
15
15
ns
267‡
Setup time, SRSX, SRS0 – SRS2 valid before SRD no longer
high (see Note 24)
15
15
ns
268
Hold time, SRSX, SRS0 – SRS2 valid after SRD no longer low
(see Note 25)
0
0
ns
272a
Setup time, SRD, SWR, and SIACK high from previous cycle to
SRD no longer high
tc(SCK)
tc(SCK)
ns
273a
Hold time, SRD, SWR, and SIACK high after SRD high
tc(SCK)
tc(SCK)
ns
275
Delay time, SRD and SWR, or SCS high to SRDY high
(see Note 24)
0
25
0
25
ns
279†
Delay time, SRD and SWR, high to SRDY in the high-impedance
state
0
tc(SCK)
0
tc(SCK)
ns
282a
Delay time, SDBEN low to SRDY low in a read cycle
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
ns
282R
Delay time, SRD low to SDBEN low (see TMS380 Second
Generation Token-Ring User’s Guide, SPWU005, subsection
3.4.1.1.1), provided previous cycle completed
0
tc(SCK) +3
0
tc(SCK) +3
ns
283R
Delay time, SRD high to SDBEN high (see Note 24)
286
Pulse duration, SRD high between DIO accesses (see Note 24)
35
35
ns
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
ns
tc(SCK)
tc(SCK)
ns
† This specification is provided as an aid to board design. It is not assured during manufacturing testing.
‡ It is the later of SRD and SWR or SCS low that indicates the start of the cycle.
NOTES: 24. The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge
cycles.
25. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
POST OFFICE BOX 1443
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45
ADVANCE INFORMATION
NO
NO.
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SCS, SRSX,
SRS0 – SRS2,
SBHE
Valid
Valid (see Note A)
264
268
265
SRAS
256
266a
267
SIACK
272a
273a
SWR
273a
272a
SRD
ADVANCE INFORMATION
273a
272a
286
High
SDDIR
279
282R
283R
SDBEN
275
282a
SRDY
(see Note B)
255
Hi-Z
261
260
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
(see Note C)
261a
259
Hi-Z
Hi-Z
Output Data Valid
Hi-Z
NOTES: A. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS
must meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters
266a and 264 are irrelevant and parameter 268 must be met.
B. When the TI380C27 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met
to the input of the data buffers.
C. In 8-bit 80x8x mode DIO reads, the SADH0 – SADH7 contain don’t care data.
Figure 21. 80x8x DIO Read-Cycle Timing
46
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
80x8x DIO write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
MIN
MIN
MAX
MAX
UNIT
255
Delay time, SRDY low to either SCS or SWR high
15
15
ns
256
Pulse duration, SRAS high
30
30
ns
262
Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL
valid before SCS or SWR no longer low
15
15
ns
263
Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL
valid after SCS or SWR high
15
15
ns
264
Setup time, SRSX, SRS0 – SRS2, SCS, and SBHE to SRAS no
longer high (see Note 25)
30
30
ns
265
Hold time, SRSX, SRS0 – SRS2, SCS, and SBHE after SRAS low
10
10
ns
266a
Setup time, SRAS high to SWR no longer high (see Note 25)
15
15
ns
267†
Setup time, SRSX, SRS0 – SRS2 before SWR no longer high
(see Note 24)
15
15
ns
268
Hold time, SRSX, SRS0 – SRS2 valid after SWR no longer low
(see Note 25)
0
0
ns
272a
Setup time, SRD, SWR, and SIACK high from previous cycle to
SWR no longer high
tc(SCK)
tc(SCK)
ns
273a
Hold time, SRD, SWR, and SIACK high after SWR high
tc(SCK)
tc(SCK)
ns
276‡
Delay time, SRDY low in the first DIO access to the SIF register
to SRDY low in the immediately following access to the SIF (see
TMS380 Second-Generation Token Ring User’s Guide,
SPWU005, subsection 3.4.1.1.1)
4000
275
279§
Delay time, SWR or SCS high to SRDY high (see Note 24)
0
Delay time, SWR high to SRDY in the high-impedance state
0
280
Delay time, SWR low to SDDIR low (see Note 24)
282b
Delay time, SDBEN low to SRDY low (see
TMS380 Second Generation Token
Token-Ring
Ring
User’s Guide, SPWU005, subsection
3.4.1.1.1)
0
ns
25
ns
0
0
tc(SCK)
tc(SCK) / 2 + 4
0
tc(SCK)
tc(SCK) / 2 + 4
If SIF register is
ready (no waiting
required)
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
If SIF register is
not ready (waiting
required)
0
4000
0
4000
tc(SCK) / 2 + 4
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
tc(SCK) / 2 + 4
ns
ns
ns
282W
Delay time, SDDIR low to SDBEN low
0
283W
Delay time, SCS or SWR high to SDBEN no longer low
0
286
25
4000
ADVANCE INFORMATION
NO
NO.
0
ns
ns
Pulse duration SWR high between DIO accesses (see Note 24)
tc(SCK)
tc(SCK)
ns
† It is the later of SRD and SWR or SCS low that indicates the start of the cycle.
‡ This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
§ This specification is provided as an aid to board design. It is not assured during manufacturing testing.
NOTES: 24. The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge
cycles.
25. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
47
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SCS, SRSX,
SRS0 – SRS2,
SBHE
Valid
264
268
265
SRAS
256
SIACK
266a
267
273a
272a
SWR
273a
286
272a
SRD
273a
272a
ADVANCE INFORMATION
280
SDDIR
282W
283W
SDBEN
(see Note A)
279
276
275
SRDY
282b
255
Hi-Z
Hi-Z
263
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
(see Note B)
262
Hi-Z
Data
Hi-Z
NOTES: A. When the TI380C27 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met
to the input of the data buffers.
B. In 8-bit 80x8x-mode DIO writes, the value placed on SADH0 – SADH7 is a don’t care.
Figure 22. 80x8x DIO Write-Cycle Timing
48
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TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
80x8x interrupt-acknowledge-cycle timing: first SIACK pulse
NO.
286
Pulse duration, SIACK high between DIO accesses (see Note 24)
287
Pulse duration, SIACK low on first pulse of two pulses
25-MHz
OPERATION
33-MHz
OPERATION
MIN
MIN
MAX
tc(SCK)
tc(SCK)
UNIT
MAX
tc(SCK)
tc(SCK)
ns
ns
NOTE 24: The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles.
SRD, SWR,
SCS
286
287
First
SIACK
Second
ADVANCE INFORMATION
Figure 23. 80x8x Interrupt-Acknowledge-Cycle Timing: First SIACK Pulse
80x8x interrupt-acknowledge-cycle timing: second SIACK pulse
NO
NO.
255
Delay time, SRDY low to SCS high
259†
25-MHz OPERATION
33-MHz OPERATION
MIN
MIN
MAX
MAX
UNIT
15
15
ns
Hold time, SAD in the high-impedance state after SIACK low
(see Note 24)
0
0
ns
260
Setup time, output data valid before SRDY low
0
0
ns
261†
Delay time, SIACK high to SAD in the high-impedance state
(see Note 24)
261a
Hold time, output data valid after SIACK high (see Note 24)
272a
Setup time, inactive data strobe high to SIACK no longer high
273a
Hold time, inactive data strobe high after SIACK high
275
Delay time, SIACK high to SRDY high (see Note 24)
276‡
Delay time, SRDY low in the first DIO access to the SIF register
to SRDY low in the immediately following access to the SIF
279†
Delay time, SIACK high to SRDY in the high-impedance state
0
0
0
tc(SCK)
tc(SCK) / 2 + 4
ns
Delay time, SDBEN low to SRDY low in a read cycle
tc(SCK)
tc(SCK) / 2 + 4
0
282a
282R
Delay time, SIACK low to SDBEN low (see TMS380 Second
Generation Token-Ring User’s Guide, SPWU005, subsection
3.4.1.1.1), provided previous cycle completed
0
tc(SCK) + 3
0
tc(SCK) + 3
ns
35
0
35
0
tc(SCK)
tc(SCK)
ns
tc(SCK)
tc(SCK)
0
25
0
4000
ns
ns
ns
25
ns
4000
ns
ns
283R
Delay time, SIACK high to SDBEN high (see Note 24)
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
ns
† This specification is provided as an aid to board design. It is not assured during manufacturing testing.
‡ This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTE 24: The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
49
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SCS, SRSX,
SRS0 – SRS2,
SBHE
Only SCS needs to be inactive.
All others are don’t care.
SIACK
272a
273a
272a
273a
272a
273a
SWR
SRD
SDDIR
High
279
ADVANCE INFORMATION
282R
283R
SDBEN
275
276
SRDY
(see Note A)
282a
Hi-Z
255
Hi-Z
261
259
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
(see Note B)
260
261a
Output Data Valid
Hi-Z
Hi-Z
NOTES: A. SRDY is an active-low bus ready signal. It must be asserted before data output.
B. In 8-bit 80x8x mode DIO writes, the value placed on SADH0 – SADH7 is a don’t care.
Figure 24. 80x8x Interrupt-Acknowledge-Cycle Timing: Second SIACK Pulse
50
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
80x8x-mode bus-arbitration timing, SIF takes control
MIN
33-MHz
OPERATION
MAX
MIN
UNIT
MAX
208a
Setup time, asynchronous signal SBBSY and SHLDA before SBCLK no
longer high to assure recognition on that cycle
10
10
ns
208b
Hold time, asynchronous signal SBBSY and SHLDA after SBCLK low to
assure recognition on that cycle
10
10
ns
212
Delay time, SBCLK low to SADH0 – SADH7, SADL0 – SADL7, SPH, and
SPL valid
224a
Delay time, SBCLK low in cycle I2 to SOWN low
224c
Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read
230
Delay time, SBCLK high to SHRQ high
241
Delay time, SBCLK high in TX cycle to SRD and SWR high, bus acquisition
241a†
Hold time, SRD and SWR in the high-impedance state after SOWN low,
bus acquisition
20
0
tc(SCK) – 15
20
ns
15
ns
28
23
ns
20
20
ns
25
25
ns
20
0
tc(SCK) – 15
ns
ADVANCE INFORMATION
25-MHz
OPERATION
NO.
† This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
POST OFFICE BOX 1443
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51
ADVANCE INFORMATION
SIF Inputs:
SIF Master
I1
I2
TX
T1
SBCLK
208a
SBBSY,
SHLDA
SIF Outputs:
208b
230
SHRQ
241
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SRD, SWR
241a
212
SBHE
212
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
Address Valid
224c
Write
SDDIR
Read
224a
SOWN
(see Note A)
NOTE A: While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
Figure 25. 80x8x-Mode Bus-Arbitration Timing, SIF Takes Control
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
Bus Exchange
(T4)
SPWS014A – APRIL 1994 – REVISED MARCH 1995
52
User Master
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
80x8x-mode DMA read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
MIN
MIN
MAX
MAX
UNIT
205
Setup time, SADL0 – SADL7, SADH0 – SADH7, SPH,
and SPL valid before SBCLK in T3 cycle no longer
high
10
10
ns
206
Hold time, SADL0 – SADL7, SADH0 – SADH7, SPH,
and SPL valid after SBCLK low in T4 cycle if
parameters 207a and 207b not met
10
10
ns
207a
Hold time, SADL0 – SADL7, SADH0 – SADH7, SPH,
and SPL valid after SRD high
0
0
ns
207b
Hold time, SADL0 – SADL7, SADH0 – SADH7, SPH,
and SPL valid after SDBEN no longer low
0
0
ns
208a
Setup time, asynchronous signal SRDY before
SBCLK no longer high to assure recognition on this
cycle
10
10
ns
208b
Hold time, asynchronous signal SRDY after SBCLK
low to assure recognition on this cycle
10
10
ns
212
Delay time, SBCLK low to address valid
20
20
ns
214†
Delay time, SBCLK low in T1 cycle to
SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL in
the high-impedance state
20
15
ns
216
Delay time, SBCLK high to SALE or SXAL high
20
ns
216a
Hold time, SALE or SXAL low after SRD high
0
217
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
0
218
Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH,
and SPL valid after SALE or SXAL low
223R
Delay time, SBCLK low in T4 cycle to SRD high
(see Note 26)
225R
Delay time, SBCLK low in T4 cycle to SDBEN high
226†
Delay time, SADH0 – SADH7, SADL0 – SADL7, SPH,
and SPL in the high-impedance state to SRD low
0
227R
Delay time, SBCLK low in T2 cycle to SRD low
0
229†
Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH,
and SPL in the high-impedance state after SBCLK
low in T1 cycle
0
0
ns
231
Pulse duration, SRD low
2tc(SCK) – 25
2tc(SCK) – 25
ns
233
Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH,
and SPL valid before SALE, SXAL no longer high
10
10
ns
237R
Delay time, SBCLK high in the T2 cyle to SDBEN low
247
Setup time, data valid before SRDY low if parameter
208a not met
20
tw(SCKH) – 15
0
0
25
tc(SCK) / 2 – 4
16
0
tw(SCKH) – 15
0
16
ns
25
tc(SCK) / 2 – 4
0
16
0
ns
ns
11
ns
ns
15
11
0
ns
11
0
15
ADVANCE INFORMATION
NO
NO.
ns
ns
ns
† This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTE 26: While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
53
ADVANCE INFORMATION
TWAIT
V
T2
T1
T3
T4
T1
SBCLK
Hi-Z
SRAS
212
SBHE
(see Note A)
Valid
High
SWR
227R
SRD
(see Note B)
223R
218
217
216
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
217
SXAL
226
216
216a
SALE
212
233
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
(see Note C)
214
218
212
Address
Extended
Address
207a
205
233
206
Data
229
Address
247
218
208a
(see Note D)
207b
SRDY
237R
208b
225R
SDBEN
(see Note B)
SDDIR
Low
NOTES: A. In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA.
B. Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
C. In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 21; i.e., held
after T4 high.
D. If parameter 208a is not met, valid data must be present before SRDY goes low.
Figure 26. 80x8x-Mode DMA Read-Cycle Timing
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
TX
SPWS014A – APRIL 1994 – REVISED MARCH 1995
54
T4
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
80x8x-mode DMA write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
MIN
MIN
MAX
MAX
UNIT
208a
Setup time, asynchronous signal SRDY before
SBCLK no longer high to assure recognition on that
cycle
10
10
ns
208b
Hold time, asynchronous signal SRDY after SBCLK
low to assure recognition on that cycle
10
10
ns
212
Delay time, SBCLK low to SADH0 – SADH7,
SADL0 – SADL7, SPH, and SPL valid
20
20
ns
216
Delay time, SBCLK high to SALE or SXAL high
20
20
ns
216a
Hold time, SALE or SXAL low after SWR high
0
217
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
0
218
Hold time, address valid after SALE, SXAL low
219
Delay time, SBCLK low in T2 cycle to output data and
parity valid
221
Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH,
and SPL valid after SWR high
223W
Delay time, SBCLK low to SWR high
225W
Delay time, SBCLK high in T4 cycle to SDBEN high
225WH
Hold time, SDBEN low after SWR, SUDS, and SLDS
high
227W
Delay time, SBCLK low in T2 cycle to SWR low
233
Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH,
and SPL valid before SALE, SXAL no longer high
237W
Delay time, SBCLK high in T1 cycle to SDBEN low
tw(SCKH) – 15
0
25
tc(SCK) / 2 – 4
0
tw(SCKH) – 15
29
tc(SCK) – 12
0
tc(SCK) / 2 – 4
tc(SCK) – 12
16
tc(SCK) / 2 – 7
POST OFFICE BOX 1443
25
29
0
16
0
ns
10
0
• HOUSTON, TEXAS 77251–1443
ns
11
ns
11
ns
ns
15
10
16
ns
ns
tc(SCK) / 2 – 7
20
ns
ADVANCE INFORMATION
NO
NO.
ns
ns
11
ns
55
ADVANCE INFORMATION
T1
T2
T3
T4
T1
SBCLK
212
SBHE
(see Note A)
Valid
High
SRD
223W
227W
SWR
217
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
216
217
SXAL
216
216a
SALE
212
233
SADL0 –
SADH7,
SADH0 –
SADL7,
SPH, SPL
(see Note B)
212
218
233
218
221
219
Address
Output Data
Extended Address
208a
SRDY
225W
237W
208b
SDBEN
SDDIR
225WH
High
NOTES: A. In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA.
B. In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 21;
i.e., held after T4 high.
Figure 27. 80x8x-Mode DMA Write-Cycle Timing
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
TX
SPWS014A – APRIL 1994 – REVISED MARCH 1995
TWAIT
V
56
T4
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
80x8x-mode bus-arbitration timing, SIF returns control
25-MHz
OPERATION
NO.
MIN
33-MHz
OPERATION
MAX
MIN
UNIT
MAX
220†
Delay time, SBCLK low in I1 cycle to SADH0 – SADH7, SADL0 – SADL7, SPL, SPH,
SRD, and SWR in the high-impedance state
35
35
ns
223b†
Delay time, SBCLK low in I1 cycle to SBHE in the high-impedance state
45
45
ns
224b
Delay time, SBCLK low in cycle I2 to SOWN high
15
ns
224d
Delay time, SBCLK low in cycle I2 to SDDIR high
27
22
ns
230
Delay time, SBCLK high in cycle I1 to SHRQ low
20
15
ns
240†
Setup time, SRD, SWR, and SBHE in the high-impedance state before SOWN no longer
low
0
20
0
0
0
ns
† This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
T3
Bus Exchange
T4
I1
User Master
I2
(T1)
ADVANCE INFORMATION
SIF Master
(T2)
SBCLK
SHLDA
SIF Outputs:
230
SHRQ
(see Note A)
220
SRD, SWR
Hi-Z
240
223b
SBHE
SIF
Hi-Z
240
220
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
Hi-Z
SIF
224d
Write
SDDIR
Read
224b
SOWN
(see Note B)
NOTES: A. In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus
transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system
bus transfer it controls.
B. While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
Figure 28. 80x8x-Mode Bus-Arbitration Timing, SIF Returns Control
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
57
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
80x8x-mode bus-release timing
25-MHz
OPERATION
NO.
MIN
MAX
33-MHz
OPERATION
MIN
UNIT
MAX
208a
Setup time, asynchronous input SBRLS low before SBCLK no longer high to assure
recognition
10
10
ns
208b
Hold time, asynchronous input SBRLS low after SBCLK low to assure recognition
10
10
ns
208c
Hold time, SBRLS low after SOWN high
0
0
ns
T(W or 2)
T3
T4
T1
T2
SBCLK
208a
SBRLS
(see Note A)
208b
ADVANCE INFORMATION
SOWN
208c
NOTES: A. The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus when it detects the
assertion of SBRLS, it completes any internally started DMA cycle and relinquishes control of the bus. If no DMA transfer has
internally started, the system interface releases the bus before starting another.
B. If SBERR is asserted when the system interface controls the system bus, the current bus transfer is completed regardless of the
value of SRDY. If the BERETRY register is non zero, the cycle is retried. If the BERETRY register is zero, the system interface
releases control of the system bus. The system interface ignores the assertion of SBERR if it is not performing a DMA bus cycle
on the system bus. When SBERR is properly asserted and BERETRY is zero, however, the system interface releases the bus upon
completion of the current bus transfer and halts all further DMA on the system side. The error is synchronized to the local bus and
DMA stops on the local sides. The value of the SDMAADR, SDMADDRX, and SDMALEN registers in the system interface are not
defined after a system-bus error.
C. In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer
and whenever the increment of the DMA address register carries beyond the least significant 16 bits.
D. SDTACK is not sampled to verify that it is deasserted.
E. Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid,
the signal is also specified to hold its previous value (including high impedance) until the start of that SBCLK transition.
Figure 29. 80x8x-Mode Bus-Release Timing
58
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx DIO read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
MIN
MIN
MAX
MAX
UNIT
255
Delay time, SDTACK low to either SCS, SUDS, or SLDS high
15
15
ns
259†
Hold time, SAD in the high-impedance state after SUDS or SLDS
low (see Note 24)
0
0
ns
260
Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL
valid before SDTACK low
0
0
ns
261†
Delay time, SCS, SUDS, or SLDS high to SADH0 – SADH7,
SADL0 – SADL7, SPH, and SPL in the high-impedance state
(see Note 24)
261a
Hold time, output data valid after SUDS or SLDS no longer low
(see Note 24)
0
0
ns
267
Setup time, register address before SUDS or SLDS no longer
high (see Note 24)
15
15
ns
268
Hold time, register address valid after SUDS or SLDS no longer
low (see Note 25)
0
0
ns
272
Setup time, SRNW before SUDS or SLDS no longer high
(see Note 24)
12
12
ns
273
Hold time, SRNW after SUDS or SLDS high
0
ns
273a
Hold time, SIACK high after SUDS or SLDS high
275
Delay time, SCS, SUDS, or SLDS high to SDTACK high
(see Note 24)
276‡
Delay time, SDTACK low in the first DIO access to the SIF
register to SDTACK low in the immediately following access to
the SIF
279†
Delay time, SUDS or SLDS high to SDTACK in the
high-impedance state
0
tc(SCK)
0
tc(SCK)
ns
282a
Delay time, SDBEN low to SDTACK low
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
ns
282R
Delay time, SUDS or SLDS low to SDBEN low (see TMS380
Second Generation Token-Ring User’s Guide, SPWU005,
subsection 3.4.1.1.1) provided the previous cycle completed
0
tc(SCK) + 3
0
tc(SCK) + 3
ns
283R
Delay time, SUDS or SLDS high to SDBEN high (see Note 24)
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
ns
286
Pulse duration, SUDS or SLDS high between DIO accesses
(see Note 24)
35
0
tc(SCK)
0
35
tc(SCK)
25
0
4000
tc(SCK)
tc(SCK)
ns
ADVANCE INFORMATION
NO
NO.
ns
25
ns
4000
ns
ns
† This specification is provided as an aid to board design. It is not assured during manufacturing testing.
‡ This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTES: 24. The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge
cycles.
25. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
59
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SCS, SRSX,
SRS0, SRS1
Valid
267
268
SIACK
273a
SRNW
272
273
SUDS,
SLDS
286
SDDIR
High
279
282R
ADVANCE INFORMATION
283R
SDBEN
276
SDTACK
(see Note A)
Hi-Z
275
282a
255
Hi-Z
261
259
260
261a
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
Output Data Valid
Hi-Z
NOTE A: SDTACK is an active-low bus ready signal. It must be asserted before data output.
Figure 30. 68xxx DIO Read-Cycle Timing
60
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Hi-Z
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx DIO write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
MIN
MIN
MAX
MAX
UNIT
255
Delay time, SDTACK low to either SCS, SUDS or SLDS high
15
15
ns
262
Setup time, write data valid before SUDS or SLDS no longer low
15
15
ns
263
Hold time, write data valid after SUDS or SLDS high
15
15
ns
267§
Setup time, register address before SUDS or SLDS no longer
high (see Note 24)
15
15
ns
268
Hold time, register address valid after SUDS or SLDS no longer
low (see Note 25)
0
0
ns
272
Setup time, SRNW before SUDS or SLDS no longer high
(see Note 24)
12
12
ns
272a
Setup time, inactive SUDS or SLDS high to active data strobe
no longer high
tc(SCK)
tc(SCK)
ns
273
Hold time, SRNW after SUDS or SLDS high
273a
Hold time, inactive SUDS or SLDS high after active data strobe
high
275
Delay time, SCS, SUDS or SLDS high to SDTACK high
(see Note 24)
276‡
Delay time, SDTACK low in the first DIO access to the SIF
register to SDTACK low in the immediately following access to
the SIF
279†
Delay time, SUDS or SLDS high to SDTACK in the
high-impedance state
0
tc(SCK)
0
tc(SCK)
ns
280
Delay time, SUDS or SLDS low to SDDIR low (see Note 24)
ns
282b
Delay time, SDBEN low to SDTACK low
((see TMS380 Second Generation TokenRing User’s Guide, SPWU005, subsection
3.4.1.1.1)
0
0
tc(SCK)
0
ns
tc(SCK)
25
0
4000
ns
25
ns
4000
ns
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
If SIF register is
ready (no waiting
required)
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
If SIF register is
not ready (waiting
required)
0
4000
0
4000
tc(SCK) / 2 + 4
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
tc(SCK) / 2 + 4
ADVANCE INFORMATION
NO
NO.
ns
282W
Delay time, SDDIR low to SDBEN low
0
283W
Delay time, SUDS or SLDS high to SDBEN no longer low
0
286
Pulse duration, SUDS or SLDS high between DIO accesses
(see Note 24)
tc(SCK)
0
tc(SCK)
ns
ns
ns
† This specification is provided as an aid to board design. It is not assured during manufacturing testing.
‡ This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
§ It is the later of SRD and SWR or SCS low that indicates the start of the cycle.
NOTES: 24. The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge
cycles.
25. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
61
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SCS SRSX,
SRS0, SRS1
Valid
267
268
SIACK
273a
272
273
SRNW
286
272a
SUDS,
SLDS
(see Note A)
273a
280
SDDIR
High
ADVANCE INFORMATION
282W
283W
SDBEN
(see Note B)
279
276
275
255
SDTACK
(see Note C)
Hi-Z
Hi-Z
282b
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
Hi-Z
263
262
Data
See Note C
Hi-Z
NOTES: A. For 68xxx mode, skew between SLDS and SUDS must not exceed 10 ns. Provided this limitation is observed, all events
referenced to a data-strobe edge use the later occurring edge. Events defined by two data strobes edges, such as parameter
286, are measured between latest and earlier edges.
B. When the TI380C27 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be
met to the input of the data buffers.
C. SDTACK is an active-low bus ready signal. It must be asserted before data output.
Figure 31. 68xxx DIO Write-Cycle Timing
62
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx interrupt-acknowledge-cycle timing
25-MHz OPERATION
33-MHz OPERATION
MIN
MIN
MAX
MAX
UNIT
255
Delay time, SDTACK low to either SCS or SUDS, or SIACK high
15
15
ns
259†
Hold time, SAD in the high-impedance state after SIACK no longer
high (see Note 24)
0
0
ns
260
Setup time, output data valid before SDTACK no longer high
0
0
ns
261†
Delay time, SIACK high to SAD in the high-impedance state
(see Note 24)
261a
Hold time, output data valid after SCS or SIACK no longer low
(see Note 24)
267§
Setup time, register address before SIACK no longer high
(see Note 24)
272a
Setup time, inactive high SIACK to active data strobe no longer
high
273a
Hold time, inactive SRNW high after active data strobe high
275
Delay time, SCS or SRNW high to SDTACK high (see Note 24)
276‡
Delay time, SDTACK low in the first DIO access to the SIF register
to SDTACK low in the immediately following access to the SIF
0
4000
279†
Delay time, SIACK high to SDTACK in the high-impedance state
0
282a
Delay time, SDBEN low to SDTACK low in a read cycle
282R
Delay time, SIACK low to SDBEN low (see TMS380 Second
Generation Token-Ring User’s Guide, SPWU005, subsection
3.4.1.1.1) provided the previous cycle completed
283R
Delay time, SIACK high to SDBEN high (see Note 24)
286
Pulse duration, SIACK high between DIO accesses (see Note 24)
35
35
ns
0
0
ns
15
15
ns
tc(SCK)
tc(SCK)
ns
tc(SCK)
0
25
tc(SCK)
0
ns
25
ns
0
4000
ns
0
0
tc(SCK)
tc(SCK) / 2 + 4
ns
0
tc(SCK)
tc(SCK) / 2 + 4
0
tc(SCK) + 3
0
tc(SCK) + 3
ns
ns
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4
ns
tc(SCK)
tc(SCK)
ns
† This specification is provided as an aid to board design. It is not assured during manufacturing testing.
‡ This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
§ It is the later of SRD and SRD or SCS low that indicates the start of the cycle.
NOTE 24: The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
63
ADVANCE INFORMATION
NO
NO.
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
SCS, SRSX,
SRS0, SRS1,
SBHE
Only SCS needs to be Inactive.
All others are don’t care.
267
SIACK
286
272a
SRNW
273a
SLDS
286
SDDIR
High
279
282R
ADVANCE INFORMATION
283R
SDBEN
275
276
282a
Hi-Z
SDTACK
(see Note A)
259
255
Hi-Z
261
260
261a
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
(see Note B)
Hi-Z
Output Data Valid
Hi-Z
NOTES: A. SDTACK is an active-low bus ready signal. It must be asserted before data output.
B. Internal logic drives SDTACK high and verifies that it has reached a valid high level before making it a 3-state signal.
Figure 32. 68xxx Interrupt-Acknowledge-Cycle Timing
64
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx-mode bus-arbitration timing, SIF takes control
NO.
25-MHz
OPERATION
33-MHz
OPERATION
MIN
MIN
MAX
UNIT
MAX
208a
Setup time, asynchronous input SBGR before SBCLK no longer high to
assure recognition on this cycle
10
10
ns
208b
Hold time, asynchronous input SBGR after SBCLK low to assure
recognition on this cycle
10
10
ns
212
Delay time, SBCLK low to address valid
0
20
0
20
ns
224a
Delay time, SBCLK low in cycle I2 to SOWN low (see Note 27)
0
20
0
15
ns
224c
Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read
28
23
ns
230
Delay time, SBCLK high to either SHRQ low or SBRQ high
20
15
ns
241
Delay time, SBCLK high in TX cycle to SUDS and SLDS high
25
25
ns
241a†
Hold time, SUDS, SLDS, SRNW, and SAS in the high-impedance state
after SOWN low, bus acquisition
tc(SCK) – 15
tc(SCK) – 15
ns
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ADVANCE INFORMATION
† This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTE 27: Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
65
ADVANCE INFORMATION
(T4)
I1
SIF Master
I2
TX
T1
T2
SBCLK
208b
208a
SBGR
SBERR,
SDTACK,
SBBSY
SIF Outputs:
230
230
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SBRQ
(see Note A)
208a
208b
SAS, SLDS,
SUDS
241
Output
Input
241
Read
SRNW
Write
SADH0 –
SADH7,
SADL0 –
SADL7,
SPH, SPL
212
Hi-Z
SIF
224c
Write
SDDIR
Read
224a
SOWN
(see Note B)
241a
NOTES: A. In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode,
the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.
B. While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled.
Figure 33. 68xxx-Mode Bus-Arbitration Timing, SIF Takes Control
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SIF Inputs:
Bus Exchange
SPWS014A – APRIL 1994 – REVISED MARCH 1995
66
User Master
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx-mode DMA read-cycle timing
MIN
MAX
33-MHz OPERATION
MIN
MAX
UNIT
205
Setup time, input data valid before SBCLK in T3
cycle no longer high
10
10
ns
206
Hold time, input data valid after SBCLK low in T4
cycle if parameters 207a and 207b not met
10
10
ns
207a
Hold time, input data valid after data strobe no longer
low
0
0
ns
207b
Hold time, input data valid after SDBEN no longer low
0
0
ns
208a
Setup time, asynchronous input SDTACK before
SBCLK no longer high to assure recognition on this
cycle
10
10
ns
208b
Hold time, asynchronous input SDTACK after
SBCLK low to assure recognition on this cycle
10
10
ns
209
Pulse duration, SAS, SUDS, and SLDS high
210
Delay time, SBCLK high in T2 cycle to SUDS and
SLDS active
16
11
ns
212
Delay time, SBCLK low to address valid
20
20
ns
214†
Delay time, SBCLK low in T2 cycle to SAD in the
high-impedance state
20
15
ns
216
Delay time, SBCLK high to SALE or SXAL high
20
20
ns
216a
Hold time, SALE or SXAL low after SUDS and SAS
high
0
217
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
0
218
Hold time, address valid after SALE, SXAL low
222
Delay time, SBCLK high to SAS low
223R
Delay time, SBCLK low in T4 cycle to SUDS, SLDS,
and SAS high (see Note 28)
225R
Delay time, SBCLK low in T4 cycle to SDBEN high
229†
Hold time, SAD in the high-impedance state after
SBCLK low in T4 cycle
0
0
ns
233
Setup time, address valid before SALE or SXAL no
longer high
10
10
ns
233a
Setup time, address valid before SAS no longer high
237R
Delay time, SBCLK high in the T2 cycle to SDBEN
low
247
Setup time, data valid before SDTACK low if
parameter 208a not met
tc(SCK)+
tw(SCKL) – 18
tw(SCKH) – 15
0
tc(SCK)+
tw(SCKL) – 18
ns
0
25
tc(SCK) / 2 – 4
20
16
0
tw(SCKH) – 15
0
16
tw(SCKL) – 15
ns
25
tc(SCK) / 2 – 4
15
0
ns
ns
ns
11
ns
ns
11
0
ns
11
tw(SCKL) – 15
16
ADVANCE INFORMATION
25-MHz OPERATION
NO
NO.
ns
ns
† This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTE 28: While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
67
ADVANCE INFORMATION
TX
T1
S1
T2
S2
S3
T3
S4
S5
T4
S6
T1
S7
SBCLK
222
239
SAS
(see Note A)
209
223R
210
SUDS,
SLDS
209
218
217
High
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SRNW
217
216
SXAL
216
218
216a
SALE
229
212
233a
212
233
SADL0 – SADH7,
SADH0 – SADL7,
SPH, SPL
233
206
214
Address
205
207a
Data In
See Note D
247
208a
Extended Address
SDTACK
(see Notes B and C)
Hi-Z
207b
208b
SDDIR
237R
225R
SDBEN
(see Note A)
NOTES: A. Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
B. All VSS pins should be routed to minimize inductance to system ground.
C. On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data can be removed when either the read strobe or SDBEN
becomes no longer active.
D. If parameter 208a is not met, valid data must be present before SDTACK goes low.
Figure 34. 68xxx-Mode DMA Read-Cycle Timing
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
T4
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68
TWAIT
V
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx-mode DMA write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
MIN
MIN
MAX
MAX
UNIT
208a
Setup time, asynchronous input SDTACK before
SBCLK no longer high to assure recognition on this
cycle
10
10
ns
208b
Hold time, asynchronous input SDTACK after SBCLK
low to assure recognition on this cycle
10
10
ns
209
Pulse duration, SAS, SUDS, and SLDS high
211
Delay time, SBCLK high in T2 cycle to SUDS and
SLDS active
211a
Delay time, output data valid to SUDS and SLDS no
longer high
212
Delay time, SBCLK low to address valid
20
20
ns
216
Delay time, SBCLK high to SALE or SXAL high
20
20
ns
216a
Hold time, SALE or SXAL low after SUDS and SAS
high
0
217
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
0
218
Hold time, address valid after SALE, SXAL low
219
Delay time, SBCLK low in T2 cycle to output data and
parity valid
221
Hold time, output data, parity valid after SUDS and
SLDS high
222
Delay time, SBCLK high to SAS low
223W
Delay time, SBCLK low to SUDS, SLDS, and SAS
high
225W
Delay time, SBCLK high in T4 cycle to SDBEN high
225WH
Hold time, SDBEN low after SUDS and SLDS high
233
Setup time, address valid before SALE or SXAL no
longer high
233a
Setup time, address valid before SAS no longer high
237W
Delay time, SBCLK high in T1 cycle to SDBEN low
tc(SCK)+
tw(SCKL) – 18
tc(SCK)+
tw(SCKL) – 18
25
tw(SCKL) – 15
tw(SCKH) – 15
25
tw(SCKL) – 15
25
tc(SCK) / 2 – 4
0
tw(SCKH) – 15
tc(SCK) – 12
25
tc(SCK) / 2 – 4
tc(SCK) – 12
16
0
16
tc(SCK) / 2 – 7
• HOUSTON, TEXAS 77251–1443
ns
ns
11
ns
11
ns
ns
ns
tw(SCKL) – 15
16
ns
15
10
tw(SCKL) – 15
ns
ns
tc(SCK) / 2 – 7
10
POST OFFICE BOX 1443
ns
29
20
ns
ns
0
29
0
ns
ADVANCE INFORMATION
NO
NO.
ns
11
ns
69
ADVANCE INFORMATION
TX
T1
T2
T3
T4
T1
SBCLK
222
211
223W
SAS
209
233a
SUDS,
SLDS
218
216
211a
217
SRNW
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Low
217
218
SXAL
216
216a
SALE
212
212
233
233
221
219
SADL0 – SADH7,
SADH0 – SADL7,
SPL, SPH
Address
Output Data
Extended Address
208a
SDTACK
(see Notes
A and B)
208b
225W
SDDIR
237W
225WH
SDBEN
NOTES: E. All VSS pins should be routed to minimize inductance to system ground.
F. On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data can be removed when either the read strobe
or SDBEN becomes no longer active.
Figure 35. 68xxx-Mode DMA Write-Cycle Timing
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
T4
SPWS014A – APRIL 1994 – REVISED MARCH 1995
70
TWAIT
V
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx-mode bus arbitration timing, SIF returns control
25-MHz
OPERATION
NO.
MIN
MAX
33-MHz
OPERATION
MIN
UNIT
MAX
220†
Delay time, SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS, and SLDS in the
high-impedance state, bus release
35
35
ns
223b†
Delay time, SBCLK low in I1 cycle to SBHE/SRNW in the high-impedance state
45
45
ns
224b
Delay time, SBCLK low in cycle I2 to SOWN high
15
ns
224d
Delay time, SBCLK low in cycle I2 to SDDIR high
27
22
ns
230
Delay time, SBCLK high to either SHRQ low or SBRQ high
20
15
ns
240†
Setup from, SUDS, SLDS, SRNW, and SAS control signals in the high-impedance state
before SOWN no longer low
0
0
20
0
0
ns
ADVANCE INFORMATION
† This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
71
ADVANCE INFORMATION
Bus Exchange
I1
T4
User
T1
I2
SBCLK
SBGR
SDTACK
SIF Outputs:
230
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SBRQ
(see Note A)
220
240
SAS, SUDS,
SLDS
240
223b
Read
Hi-Z
SRNW
Write
220
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
SIF
Hi-Z
224d
Write
SDDIR
Read
224b
SOWN
NOTE A: In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode,
the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.
Figure 36. 68xxx-Mode Bus-Arbitration Timing, SIF Returns Control
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
T3
SPWS014A – APRIL 1994 – REVISED MARCH 1995
72
SIF Master
T2
SIF Inputs:
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
68xxx-mode bus-release and error timing
25-MHz
OPERATION
NO.
MIN
MAX
33-MHz
OPERATION
MIN
UNIT
MAX
208a
Setup time, asynchronous input before SBCLK no longer high to assure recognition
10
10
ns
208b
Hold time, asynchronous input SBRLS, SOWN, or SBERR after SBCLK low to assure
recognition
10
10
ns
208c
Hold time, SBRLS low after SOWN high
0
0
ns
236
Setup time, SBERR low before SDTACK no longer high if parameter 208a not met
30
30
ns
T(W or 2)
T3
T4
T1
T2
SBCLK
208a
208b
SOWN
208c
208a
SBERR
(see Note B)
236
SDTACK
NOTES: A. The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus when it detects the
assertion of SBRLS, it completes any internally started DMA cycle and relinquishes control of the bus. If no DMA transfer has
internally started, the system interface releases the bus before starting another.
B. If SBERR is asserted when the system interface controls the system bus, the current bus transfer is completed, regardless of the
value of SDTACK. If the BERETRY register is nonzero, the cycle is retried. If the BERETRY register is zero, the system interface
then releases control of the system bus. The system interface ignores the assertion of SBERR if it is not performing a DMA bus
cycle on the system bus. When SBERR is properly asserted and BERETRY is zero, however, the system interface releases the
bus upon completion of the current bus transfer and halts all further DMA on the system side. The error is synchronized to the local
bus and DMA stops on the local sides. The value of the SDMAADR, SDMADDRX, and SDMALEN registers in the system interface
are not defined after a system-bus error.
C. In cycle-steal mode, state TX is present on every system-bus transfer. In burst mode, state TX is present on the first bus transfer
and whenever the increment of the DMA address register carries beyond the least significant 16 bits.
D. SDTACK is not sampled to verify that it is deasserted.
E. Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid,
the signal is also specified to hold its previous value (including high impedance) until the start of that SBCLK transition.
Figure 37. 68xxx-Mode Bus-Release and Error Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
73
ADVANCE INFORMATION
208b
SBRLS
(see Note A)
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
T1
T(W or 2)
T3
TH
T4
T1
SBCLK
SDTACK
SBERR
SHALT
NOTE A: Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement may vary from waveforms
shown.
Figure 38. 68xxx-Mode Bus-Halt and Retry, Normal Completion With Delayed Start
ADVANCE INFORMATION
T1
T2
T3
T4
THB
THE
T1
SBCLK
SDTACK
SBERR
SHALT
SOWN
NOTE A: Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement may vary from waveforms
shown.
Figure 39. 68xxx-Mode Bus-Halt and Retry, Rerun Cycle With Delayed Start
74
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
APPLICATION INFORMATION
Figure 40 shows the TI380C27 connected to a LEVEL ONE LXT901 universal Ethernet interface adapter. The
LXT901 provides all of the active circuitry for interfacing the TI380C27 to the 10 Base-T twisted-pair network.
To 10 BASE-T
Twisted-Pair
Network
RJ45
Texas Instruments TI380C27
Dual-Protocol
Comprocessor
20 pF
FRAQ / TXD
WRAP / TXEN
PXTALIN / TXC
RCLK / RXC
RCVR / RXD
REDY / CRS
WFLT / COLL
NSRT / LPBK
TXD
TEN
TCLK
RCLK
RXD
CD
COL
LBK
20 MHz
CLKI
0.1 µF
20 pF
CLKO
1
TPIN
1:1
16
50 Ω
50 Ω
3
TPIP
14
1N914
TEST0
NSELOUT0
LEDC
See
Note
A
TPONB
TPONA
10 kΩ
AUTOSEL
NTH
MD0
MD1
UTP
Programming
Options
TPOPA
TPOPB
LI
Line Status
330 Ω
Green
330 Ω
Red
330 Ω
Red
Level One LXT901
RJAB
CIN
RLD
CIP
RCMPT
DON
JAB
DOP
PLR
DIN
PAUI
DIP
LEDR
LEDT/PDN
LADL
VCC1
RBISA
5V
VCC2
1:√2
6
11
37.5 Ω ± 1%
10
10 kΩ
Remote
Status
75 Ω ± 1%
➇
➆
➅
➄
➃
➂
➁
➀
ADVANCE INFORMATION
See Note D
GND1
8
9
37.5 Ω ± 1%
18 pF
75 Ω ± 1%
See Note B
12.4 kΩ ± 1%
See Note C
GND2
NOTES: A. Half/full duplex selection controlled by TI380C27 pins TEST0 and NSELOUT0.
NSELOUT0 = L (full duplex)
NSELOUT0 = H (half duplex)
For half-duplex operation, diode 1N914 and associate 10-kΩ resistor are not needed: these components can be
removed.
B. Suitable TP transformers include the Fil-Mag 23Z128, and SM23Z128; Valor PT4069 and ST7011; Pulse
Engineering PE65994 and PE65745; Belfuse S553-0716 and A553-0716; and Halo Electronics TD42-2006Q
and TD42-2006W1.
C. RBIAS should be located close to the pin and isolated from other signals.
D. Suitable crystals include the MTRON MP-1 and MP-2.
Figure 40. Typical Schematic for Full-Duplex Operation With the TI380C27
LEVEL ONE LTXT901 is a registered trademark of LEVEL ONE Communications, Inc.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
75
TI380C27
DUAL-PROTOCOL COMMPROCESSOR
SPWS014A – APRIL 1994 – REVISED MARCH 1995
MECHANICAL DATA
PGE/S-PQFP-G144
PLASTIC QUAD FLATPACK
0,27
TYP
0,17
0,50 TYP
108
73
ADVANCE INFORMATION
109
72
144
37
1
0,127 TYP
36
17,50 TYP
1,45
1,35
20,10 SQ
19,90
22,10 SQ
21,90
0,05 MIN
Seating Plane
0,08
0°–7°
0,70
0,30
1,60 MAX
4040147/A–10/93
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
76
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
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Copyright  1998, Texas Instruments Incorporated