TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 D D D D D D D D D D D D D D Single-Chip Token-Ring Solution IBM Token-Ring Network Compatible Compatible With ISO/IEC IEEE Std 802.5:1992 Token-Ring Access-Method and Physical-Layer Specifications Compatible With TI380FPA PacketBlaster Glueless Memory Interface Digital Phase-Locked Loop (PLL) – Precise Control of Bandwidths – Improved Jitter Tolerance – Minimizes Accumulated Phase Slope Phantom Drive for Physical Insertion Onto Ring Differential Line Receiver With Level-Dependent Frequency Equalization Low-Impedance Differential Line Driver to Ease Transmit-Filter Design On-Chip Watchdog Timer Internal Crystal Oscillator for Reference-Clock Generation D D D D D Expandable LAN-Subsystem Memory up to 2M Bytes D 32-Bit Host Address Bus 80x8x or 68xxx-Type Bus and Memory Organization Dual-Port Direct Memory Access (DMA) and Direct Input/Output Transfers to Host Bus Supports 8- or 16-Bit Pseudo-Direct Memory Access (PDMA) Operation Electrostatic Discharge (ESD) Protection Exceeds 2 kV (All Pins) 0.8-µm CMOS Technology Token-Ring Features – 16- or 4-Megabit-Per-Second (Mbit/s) Data Rates – Supports up to 18K-Byte Frame Size (16 Mbit/s Only) – Supports Universal and Local Addressing – Early Token-Release Option (16 Mbit/s Only) – Built-In Real-Time Error Detection – Automatic Frame-Buffer Management – 2-MHz to 33-MHz System-Bus Clock – Slow-Clock Low-Power Mode 176-Pin Thin Quad Flat Package LAN Subsystem Attached System Bus (2 MHz to 33 MHz) Transmit To Network TI380C30A Receive Memory Figure 1. Network-Commprocessor Applications Diagram Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel is a trademark of Intel Corporation. IBM and Token-Ring Network are trademarks of International Business Machines Corporation. Motorola is a trademark of Motorola, Inc. PacketBlaster and TI are trademarks of Texas Instruments Incorporated. PAL is a registered trademark of Advanced Micro Devices, Inc. Other companies also manufacture programmable array logic devices. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Table 1. Abbreviations and Acronyms 2 APS Accumulated Phase Slope ASF Adapter-Support Function ARI/FCI Address-Recognize Indicator/Frame-Copied Indicator BIA Burn-In Address CAF Copy All Frames CG Clock Generator CP Communications Processor CPU Central Processing Unit CRC Cyclic Redundancy Check DIO Direct Input/Output DMA Direct Memory Access ESD Electrostatic Discharge EACO Enhanced-Address-Copy Option LLC Logical Link Control LSB Least Significant Bit MAC Media-Access Control Mbit/s Megabits Per Second Mbit/s Megabytes Per Second MIF Memory Interface MIPS Million Instructions Per Second MOSFET Metal Oxide Semiconductor Field-Effect Transistor MSB Most Significant Bit PDMA Pseudo-Direct Memory Access PH Protocol Handler PHY Physical-Layer Interface PLL Phase-Locked Loop SIF System Interface SIFACL SIF Adapter Control Register S/W Software TCU Trunk-Coupling Unit UNA Upstream Neighbor Address POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 135 134 133 139 138 137 136 143 142 141 140 147 146 145 144 151 150 149 148 155 154 153 152 159 158 157 156 163 162 161 160 167 166 165 164 171 170 169 168 88 80 81 82 83 76 77 78 79 72 73 74 75 68 69 70 71 64 65 66 67 60 61 62 63 56 57 58 59 52 53 54 55 48 49 50 51 XT2 VSSO XT1 VDDA2 ATEST VSSA2 IREF VSSA3 REDY VDDA3 FRAQ NSRT VSSL VDD XMATCH XFAIL TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 VSS VDD VSSC SADH6 SADH7 SPH SRD/SUDS SRDY/SDTACK SOWN SDBEN SBHE/SRNW SHRQ/SBRQ SPL SADL0 SADL1 SADL2 VDD V SSL V DDL MADL2 MADL1 MADL0 EXTINT3 EXTINT2 EXTINT1 EXTINT0 NMI CLKDIV V SSC NSELOUT0 PRTYEN BTSTRP SIACK SRESET SRS1 SRS0 SRSX SCS SBRLS SBBSY S8 / SHALT SRS2 / SBERR V DDL SI / M SINTR / SIRQ SHLDA / SBGR SDDIR SRAS / SAS SWR / SLDS V SS SXAL SALE SBCLK SADL7 SADL6 SADL5 SADL4 SADL3 VDD V SSL 84 85 86 87 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 MREF MAL MACS MROMEN OSC32 OSCIN TCLK TMS TRST VSSC VSS SYNCIN VDDL VDD MDDIR MAX0 MAX2 MCAS MW MRAS VSSC VSSL MOE MBEN MADH7 MADH6 MADH5 MADH4 VDD VSS MADH3 MADH2 MADH1 MADH0 MAXPH MBRQ MBGR VSS MAXPL MADL7 MADL6 MADL5 MADL4 MADL3 175 174 173 172 176 MBIAEN MRESET MBCLK2 MBCLK1 OSCOUT NSELOUT1 WRAP DRVR+ DRVR – WFLT NC TDI TDO PXTAL RCVR RCLK V SSC1 V SSD RATER V DDD NABL S4 / 16 PWRDN VSSL1 EQ+ EQ – V SSA1 RCV+ V DDA1 RCV– V DDL1 V DDX XMT– XMT+ V SSX PHOUTB V SSP PHOUTA V DDP RES V SSL1 NC V DDL1 V DDO PGF PACKAGE (TOP VIEW) NC = No internal connection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 description The TI380C30A is a single-chip token-ring solution, combining the commprocessor and the physical-layer (PHY) interface onto a single device. The TI380C30A supports 16 Mbit/s and 4 Mbit/s of operation, conforms to ISO 8802–5/IEEE Std 802.5–1992 standards, and has been verified to be completely IBM Token-Ring Network compatible. The TI380C30A provides a high degree of integration as it combines the functions of the TI380C25 and the TI380C60A onto a single chip. Additional information on the PHY section can be found in the TI380C60A data sheet, literature number SPWS033. With the TI380C30A, only local memory and minimal additional components such as PAL devices and crystal oscillators need to be added to complete the LAN-subsystem design. The TI380C30A provides a 32-bit system-memory address reach with a high-speed bus-master direct memory access (DMA) interface that supports rapid communications with the host system. In addition, the TI380C30A supports direct I/O and a low-cost 8-bit or 16-bit pseudo-DMA interface that requires only a chip-select to work directly on an 80x8x 8-bit slave I/O interface. Selectable 80x8x or 68xxx-type host-system bus and memory organization add to design flexibility. The TI380C30A supports addressing for up to 2M bytes of local memory. This expanded memory capacity can improve LAN-subsystem performance by minimizing the frequency of host LAN-subsystem communications by allowing larger blocks of information to be transferred at one time. The support of large local memory is important in applications that require large data transfers (such as graphics or database transfers) and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host. The proprietary central processing unit (CPU) used in the TI380C30A allows protocol software to be downloaded into RAM or stored in ROM in the local-memory space. By moving protocols [such as logical link control (LLC)] to the LAN-subsystem, overall system performance is increased. This is accomplished by offloading processing from the host-system to the TI380C30A, which also can reduce LAN-subsystem-to-host communications. As other protocol software is developed, greater differentiation of end products with enhanced system performance is possible. The TI380C30A includes hardware counters that provide real-time error detection and automatic frame-buffer management. These counters control system-bus retries and burst size, and track host- and LAN-subsystem-buffer status. Previously, these counters were maintained in software. By integrating them into hardware, software overhead is reduced and LAN-subsystem performance is improved. The TI380C30A implements a Texas Instruments (TI)-patented enhanced-address-copy-option (EACO) interface. This interface supports external address-checking devices, such as the TMS380SRA source-routing accelerator. The TI380C30A has a 128-word external I/O space in its memory to support external address-checker devices and other hardware extensions to the TMS380 architecture. At the PHY, the Manchester-encoded data stream is received and phase-aligned using an on-chip dual-digital phase-locked loop (PLL). Both the recovered clock and data are passed to the protocol-handling circuits on the TI380C30A for serial-to-parallel conversion and data processing. On transmit, the TI380C30A buffers the output from the protocol-handling circuit and drives the media by way of suitable isolation and waveform-shaping components. The TI380C30A uses CMOS technology to reduce power consumption to PCMCIA-compatible levels. Power-management features are incorporated to support Green PC compatibility. In addition to the PLL, all other functions required to interface to an IEEE Std 802.5 token ring are provided. These functions include the phantom drive to control the relays within a trunk-coupling unit and wire-fault detection circuits; an internal-wrap function for self-test; and a watchdog timer to provide fail-safe deinsertion from the ring in the event of a station, microcode, or commprocessor failure. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 description (continued) The major blocks of the TI380C30A include the communications processor (CP), the system interface (SIF), the memory interface (MIF), the protocol handler (PH), the clock generator (CG), the adapter-support function (ASF), and the PHY, as shown in the functional block diagram. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 functional block diagram SADH0 MADH0 SIF SADH7 SADL0 SADL7 SPH SPL SBRLS SINTR/SIRQ SDDIR SDBEN SALE SXAL SOWN SIACK SBCLK SRD/SUDS SWR/SLDS SRDY/SDTACK SI/M SHLDA/SBGR SBHE/SRNW SRAS/SAS S8/SHALT SRESET SRS0 SRS1 SRS2/SBERR SCS SRSX SHRQ/SBRQ SBBSY BTSTRP PRTYEN NSELOUT0 NSELOUT1 MIF • DIO Control • Bus Control • DMA Control • DRAM Refresh • Local-Bus Arbitrator • Local-Bus Control • Local Parity-Check/ Generator CG MADL7 MRAS MCAS MAXPH MAXPL MW MOE MDDIR MAL MAX0 MAX2 MRESET MROMEN MBEN MBRQ MBGR MACS MBIAEN MREF OSCIN OSCOUT MBCLK1 MBCLK2 SYNCIN CLKDIV NMI EXTINT0 ASF • Interrupts • Test Function Communications Processor RCLK† REDY† WFLT† RCVR† PXTAL† OSC32 TCLK TMS TRST ATEST XT1 XT2 PHOUTA PHOUTB EQ– EQ+ EXTINT3 TEST0 TEST5 Token-Ring PH XMATCH XFAIL PHY Interface Test Port FRAQ† NSRT† WRAP† DRVR+† DRVR–† PHY = Analog Signal † Signals are provided for test-monitoring purposes. 6 MADH7 MADL0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 XMT+ XMT– RCV+ RCV– PWRDN S4/16 NABL RATER TDO TDI TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions TERMINAL NAME ATEST BTSTRP NO. 128 60 I/O/E† E I DESCRIPTION Analog test. ATEST must be left unconnected. Bootstrap. The value on BTSTRP is loaded into the BOOT bit of the SIFACL register at reset (that is, when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value. BTSTRP indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters are RAM, the TI380C30A is denied access to the local-memory bus until the CPHALT bit in the SIFACL register is cleared. H = Chapters 0 and 31 of local memory are RAM based (see Note 1). L = Chapters 0 and 31 of local memory are ROM based. Clock divider select (see Note 2) CLKDIV 56 I DRVR+ DRVR– 169 168 O O Differential-driver data outputs (reserved) EQ+ EQ– 152 151 E E Equalization/gain points. Connections to allow frequency tuning of equalization circuit. EXTINT0 EXTINT1 EXTINT2 EXTINT3 54 53 52 51 I/O FRAQ 122 To be resolved IREF 126 E Internal reference. IREF allows the internal bias current of analog circuitry to be set by way of an external resistor. MACS 3 I Reserved. MACS must be tied low (see Note 4). MADH0 MADH1 MADH2 MADH3 MADH4 MADH5 MADH6 MADH7 34 33 32 31 28 27 26 25 MADL0 MADL1 MADL2 MADL3 MADL4 MADL5 MADL6 MADL7 50 49 48 44 43 42 41 40 MAL 2 I/O H = 64-MHz OSCIN for 4-MHz local bus L = 32-MHz OSCIN for 4-MHz local bus or 48-MHz OSCIN for 6-MHz local bus Reserved. EXTINT0–EXTINT3 must be pulled high (see Note 3). Frequency-acquisition control H = Clock recovery PLL is initialized L = Normal operation Local-memory address, data, and status bus – high byte. For the first quarter of the local-memory cycle, these bus lines carry address bits AX4 and A0–A6; for the second quarter, they carry status bits; and for the third and fourth quarters, they carry data bits D0–D7. The most significant bit is MADH0 and the least significant bit is MADH7. Signal I/O Memory Cycle 2Q 3Q Status D0–D7 4Q D0–D7 Local-memory address, data, and status bus — low byte. For the first quarter of the local-memory cycle, these bus lines carry address bits A7–A14; for the second quarter, they carry address bits AX4 and A0–A6; and for the third and fourth quarters, they carry data bits D8–D15. The most significant bit is MADL0 and the least significant bit is MADL7. Signal O 1Q AX4, A0–A6 1Q A7–A14 Memory Cycle 2Q 3Q AX4, A0–A6 D8–D15 4Q D8–D15 Memory-address latch. MAL is a strobe signal for sampling the address at the start of the memory cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH, MAX2, MAXPL, MADH0–MADH7, and MADL0–MADL7. Three 8-bit transparent latches can be used to retain a 20-bit static address throughout the cycle. Rising edge = No signal latching Falling edge = Allows the above address signals to be latched † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTES: 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 2. The TMS380SRA is supported only with the 4-MHz local bus in either CLKDIV state. 3. Each terminal must be tied individually to VDD with a 1-kΩ pullup resistor. 4. Terminal should be connected to ground. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL NAME MAX0 NO. 16 I/O/E† I/O DESCRIPTION Local-memory extended-address bit. MAX0 drives AX0 at row-address time and A12 at column-address and data-valid times for all cycles. MAX0 can be latched by MRAS. Driving A12 eases interfacing to a burn-in address (BIA) ROM. Signal MAX2 17 I/O 35 I/O 39 I/O Memory Cycle 2Q 3Q A14 A14 1Q AX2 4Q A14 Local-memory extended address and parity — high byte. For the first quarter of a memory cycle, MAXPH carries the extended-address bit AX1; for the second quarter of a memory cycle, MAXPH carries the extended-address bit AX0; and for the last half of the memory cycle, MAXPH carries the parity bit for the high data byte. Memory Cycle 2Q 3Q AX0 Parity 1Q AX1 Signal MAXPL 4Q A12 Local-memory extended-address bit. MAX2 drives AX2 at row-address time, which can be latched by MRAS, and A14 at column-address and data-valid times for all cycles. Driving A14 eases interfacing to a BIA ROM. Signal MAXPH Memory Cycle 2Q 3Q A12 A12 1Q AX0 4Q Parity Local-memory extended address and parity — low byte. For the first quarter of a memory cycle, MAXPL carries the extended-address bit AX3; for the second quarter of a memory cycle, MAXPL carries extended-address bit AX2; and for the last half of the memory cycle, MAXPL carries the parity bit for the low data byte. Memory Cycle 2Q 3Q AX2 Parity 1Q AX3 Signal 4Q Parity Local-bus clock 1 and local-bus clock 2. MBCLK1 and MBCLK2 are referenced for all local-bus transfers. MBCLK2 lags MBCLK1 by a quarter of a cycle. MBCLK1 and MBCLK2 operate according to: MBCLK1 MBCLK2 173 174 O MBEN 24 O MBGR 37 I/O MBCLK1– MBCLK2 8 MHz 8 MHz 12 MHz OSCIN CLKDIV 64 MHz 32 MHz 48 MHz H L L (4-MHz local bus) (4-MHz local bus) (6-MHz local bus) Buffer enable. MBEN enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL, and MADL buses during the data phase. MBEN is used with MDDIR, which selects the buffer-output direction. H = Buffer output disabled L = Buffer output enabled Reserved. MBGR must be left unconnected. Burned-in address enable. MBIAEN is an output signal used to provide an output enable for the ROM containing the adapter’s BIA. MBIAEN 176 O H = MBIAEN is driven high for any write accesses to the addresses between >00.0000 and >00.000F, or any accesses (read/write) to any other address. L = MBIAEN is driven low for any read from addresses between >00.0000 and >00.000F. MBRQ 36 I/O Reserved. MBRQ must be pulled high (see Note 3) † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTE 3. Each terminal must be tied individually to VDD with a 1-kΩ pullup resistor. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL NAME NO. I/O/E† DESCRIPTION Column-address strobe for DRAMs. The column address is valid for 3/16ths of the memory cycle following the row-address portion of the cycle. MCAS is driven low every memory cycle while the column address is valid on MADL0–MADL7, MAXPH, and MAXPL, except when one of the following conditions occurs: MCAS MDDIR MOE MRAS MREF MRESET MROMEN 18 15 23 20 1 175 4 O I/O O O O O O – When the address accessed is in the BIA ROM (>00.0000–>00.000F) – When the address accessed is in the EPROM memory map (that is, when the BOOT bit in the SIFACL register is 0 and an access is made between >00.0010 and >00.FFFF or >1F.0000 and >1F.FFFF) – When the cycle is a refresh cycle, in which case MCAS is driven low at the start of the cycle before MRAS [for DRAMs that have CAS-before-RAS refresh]. For DRAMs that do not support CAS-before-RAS refresh, it may be necessary to disable MCAS with MREF during the refresh cycle. Data direction. MDDIR is used as a direction control for bidirectional bus drivers. MDDIR becomes valid before MBEN becomes active. H = TI380C30A memory-bus write L = TI380C30A memory-bus read Memory-output enable. MOE enables the outputs of the DRAM memory during a read cycle. MOE is high for EPROM or BIA ROM read cycles. H = Disable DRAM outputs L = Enable DRAM outputs Row-address strobe for DRAMs. The row address lasts for the first 5/16ths of the memory cycle. MRAS is driven low every memory cycle while the row address is valid on MADL0–MADL7, MAXPH, and MAXPL for both RAM and ROM cycles. MRAS is also driven low during refresh cycles when the refresh address is valid on MADL0–MADL7. DRAM refresh cycle in progress. MREF indicates that a DRAM refresh cycle is occurring. It is also used for disabling MCAS to all DRAMs that do not use a CAS-before-RAS refresh. H = DRAM refresh cycle in process L = Not a DRAM refresh cycle Memory-bus reset. MRESET is a reset signal generated when either the ARESET bit in the SIFACL register is set or SRESET is asserted. MRESET is used for resetting external local-bus glue logic. H = External logic not reset L = External logic reset ROM enable. During the first 5/16ths of the memory cycle, MROMEN is used to provide a chip select for ROMs when the BOOT bit of the SIFACL is 0 (that is, when code is resident in ROM, and not RAM). MROMEN can be latched by MAL. MROMEN goes low for any read from addresses >00.0010–>00.FFFF or >1F.0000–>1F.FFFF when the BOOT bit in the SIFACL register is 0. MROMEN stays high for writes to these addresses, accesses of other addresses, or accesses of any address when the BOOT bit is 1. During the final three-fourths of the memory cycle, MROMEN outputs the A13 address signal for interfacing to a BIA ROM. This means MBIAEN, MAX0, MROMEN, and MAX2 form a glueless interface for the BIA ROM. H = ROM disabled L = ROM enabled MW 19 O Local-memory write. MW is used to specify a write cycle on the local-memory bus. The data on the MADH and MADL buses is valid while MW is low. DRAMs latch data on the falling edge of MW, while SRAMs latch data on the rising edge of MW. H = Not a local-memory write cycle L = Local-memory write cycle NABL 156 NC 135 166 I Output-enable control. NABL is used in the physical-layer circuitry (see Note 1). These NC pins must be left unconnected. NMI 55 I Nonmaskable interrupt request. NMI must be left unconnected. † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTE 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL NAME NSELOUT0 NSELOUT1 NO. 58 171 I/O/E† O DESCRIPTION Network selection outputs. NSELOUT0 and NSELOUT1 are controlled by the host through the corresponding bits of the SIFACL register. The value of NSELOUT0 and NSELOUT1 can be changed only while the TI380C30A is reset. NSELOUT0 L H NSELOUT1 H H Description 16-Mbit/s token ring 4-Mbit/s token ring Insert control. NSRT enables the phantom-driver outputs (PHOUTA and PHOUTB) through the watchdog timer for insertion onto the token ring. NSRT 121 O OSC32 5 O Static high = Inactive, phantom current removed (due to watchdog timer) Static low = Inactive, phantom current removed (due to watchdog timer) Falling edge = Active, current output on PHOUTA and PHOUTB Oscillator output. OSC32 provides a 32-MHz clock output and can be used to drive OSCIN and one other TTL load. External oscillator input. OSCIN provides the clock frequency to the TI380C30A for a 4-MHz or 6-MHz internal bus (see Notes 5, 6, and 8). OSCIN 6 I CLKDIV H L OSCIN 64 MHz for a 4-MHz local bus 32 MHz for a 4-MHz local bus or 48 MHz for a 6-MHz local bus Oscillator output OSCOUT PHOUTA PHOUTB PRTYEN 172 139 141 59 O O I CLKDIV L OSCOUT OSCIN ÷ 4 H OSCIN ÷ 8 (if OSCIN = 32 MHz, OSCOUT = 8 MHz) (if OSCIN = 48 MHz, OSCOUT = 12 MHz) (if OSCIN = 64 MHz, OSCOUT = 8 MHz) Phantom-driver outputs A and B. PHOUTA and PHOUTB cause insertion onto the token ring. PHOUTA and PHOUTB should be connected to the center tap of the transmit transformer secondary winding for phantom-drive generation. Parity enable. The value on PRTYEN is loaded into the PEN bit of the SIFACL register at reset (that is, when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value. PRTYEN enables parity checking for the local memory. H = Local-memory data bus checked for parity (see Note 1) L = Local-memory data bus not checked for parity. Power-down control (see Note 7) H = Normal operation L = TI380C30A physical-layer circuitry is placed into a power-down state. All TTL outputs of the physical layer are driven to the high-impedance state. PWRDN 154 I PXTAL 163 O Reference-clock output. PXTAL is synthesized from the 8-MHz crystal oscillator used for XT1 and XT2. For 16 Mbit/s, it is a 32-MHz clock; for 4 Mbit/s, it is an 8-MHz clock (see Note 8). RATER 158 O RATER indicates that there are transitions on the RCV+/RCV– input pair (DRVR+/DRVR– if WRAP is asserted low) but that the transition rate is not consistent with the ring speed selected by the S4/16 pin. RCLK 161 O Recovered clock. RCLK is the clock recovered from the token-ring received data. For 16-Mbit/s operation, it is a 32-MHz clock. For 4-Mbit/s operation, it is an 8-MHz clock. RCV+ RCV– 149 147 I Receiver. RCV+ and RCV– are differential inputs that receive the token-ring data by way of isolation transformers. RCVR 162 O Recovered data. RCVR contains the data recovered from the token ring. † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTES: 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 5. Terminal has an expanded input voltage specification. 6. A maximum of two TI380C30A devices can be connected to any one oscillator. 7. Terminal should be tied to VDD with a 4.7-kΩ pullup resistor. 8. A BUD 35 failure can occur if the rising edge of PXTAL occurs 5 ns to 9 ns after the rising edge of OSCIN. It is a BUD problem only, and does not affect normal operation. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL NAME NO. I/O/E† DESCRIPTION PLL ready. REDY is normally asserted (active) low. It is cleared following the assertion of FRAQ and reasserted after the data recovery PLL has been reinitialized. REDY 124 O H = Received data not valid (or signal not present) L = Received data valid The signal loss indication is in lieu of ring status (SSB_CMD = 0X0001, ring_status bit 0) signal loss indication. RES 137 SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 110 109 108 107 106 105 101 100 — Reserved. RES should be left unconnected. I/O System address/data bus – high byte (see Note 1). These lines make up the most significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit (MSB) is SADH0, and the least significant bit (LSB) is SADH7. Address multiplexing: Bits 31–24 and bits 15–8‡ Data multiplexing: Bits 15–8‡ SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7 91 90 89 86 85 84 83 82 I/O System address/data bus – low byte (see Note 1). These lines make up the least significant byte of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is SADL0, and the least significant bit is SADL7. Address multiplexing: Bits 23–16 and bits 7–0‡ Data multiplexing: Bits 7–0‡ SALE 80 O System address-latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of the address from the SADH and SADL buses at the start of the DMA cycle. Systems that implement address parity can also externally latch the parity bits (SPH and SPL) for the latched address. SBBSY 68 I SBCLK 81 I System bus busy. The TI380C30A samples the value on SBBSY during arbitration (see Note 1). The sample has one of two values: H = Not busy. The TI380C30A can become bus master if the grant condition is met. L = Busy. The TI380C30A cannot become bus master. System bus clock. The TI380C30A requires the external clock to synchronize its bus timings for all DMA transfers. Valid frequencies are 2 MHz–33 MHz. Intel mode SBHE/SRNW 94 I/O Motorola mode SBRLS 67 I SBHE is used for system-byte-high enable. SBHE is a 3-state output driven during DMA; it is an input at all other times. H = System byte high not enabled (see Note 1) L = System byte high enabled SRNW is used for system read, not write. SRNW serves as a control signal to indicate a read or write cycle. H = Read cycle (see Note 1) L = Write cycle System-bus release. SBRLS indicates to the TI380C30A that a higher-priority device requires the system bus. The value on SBRLS is ignored when the TI380C30A is not performing DMA. SBRLS is internally synchronized to SBCLK. H = The TI380C30A can hold onto the system bus (see Note 1) L = The TI380C30A should release the system bus upon completion of current DMA cycle. If the DMA transfer is not yet complete, the SIF rearbitrates for the system bus. † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning ‡ Typical bit ordering for Intel and Motorola processor buses NOTE 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL NAME NO. I/O/E† DESCRIPTION System-chip select. SCS activates the system interface of the TI380C30A for a DIO read or write. SCS SDBEN SDDIR 66 95 75 I O O H = Not selected (see Note 1) L = Selected System data-bus enable. SDBEN signals to the external data buffers to begin driving data. SDBEN is activated during both DIO and DMA. H = Keep external data buffers in the high-impedance state L = Cause external data buffers to begin driving data System data direction. SDDIR provides to the external data buffers a signal indicating the direction in which the data is moving. During DIO writes and DMA reads, SDDIR is low (data direction is into the TI380C30A). During DIO reads and DMA writes, SDDIR is high (data direction is out from the TI380C30A). When the system interface is not involved in a DIO or DMA operation, SDDIR is high by default. SDDIR H L Intel mode SHLDA/SBGR 74 I Motorola mode Intel mode SHRQ/SBRQ 93 O Motorola mode SIACK 61 I Data Direction Output Input DIO Read Write DMA Write Read SHLDA is used for system-hold acknowledge. SHLDA indicates that the system DMA-hold request has been acknowledged. SHLDA is internally synchronized to SBCLK (see Note 1). H = Hold request acknowledged L = Hold request not acknowledged SBGR is used for system bus grant. SBGR is an active-low bus grant, as defined in the standard 68xxx interface, and is internally synchronized to SBCLK (see Note 1). H = System bus not granted L = System bus granted SHRQ is used for system-hold request. SHRQ is used to request control of the system bus in preparation for a DMA transfer. SHRQ is internally synchronized to SBCLK. H = System bus requested L = System bus not requested SBRQ is used for system-bus request. SBRQ is used to request control of the system bus in preparation for a DMA transfer. SBRQ is internally synchronized to SBCLK. H = System bus not requested L = System bus requested System-interrupt acknowledge. SIACK is for the host processor to acknowledge the interrupt request from the TI380C30A. H = System interrupt not acknowledged (see Note 1) L = System interrupt acknowledged: The TI380C30A places its interrupt vector onto the system bus. System-Intel/Motorola mode select. The value on SI/M specifies the system-interface mode. SI/M 72 I H = Intel-compatible-interface mode selected. Intel-interface mode can be 8 bit or 16 bit (see S8/SHALT description and Note 1). L = Motorola-compatible-interface mode selected. Motorola-interface mode is always 16 bits. Intel mode SINTR/SIRQ 73 O Motorola mode SINTR is used for system-interrupt request. TI380C30A activates SINTR to signal an interrupt request to the host processor. H = Interrupt requested by TI380C30A L = No interrupt request SIRQ is used for system-interrupt request. TI380C30A activates SIRQ to signal an interrupt request to the host processor. H = No interrupt request L = Interrupt requested by TI380C30A † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTE 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL NAME SOWN NO. 96 I/O/E† DESCRIPTION O System bus owned. SOWN indicates to external devices that TI380C30A has control of the system bus. SOWN drives the enable signal of the bus-transceiver chips that drive the address and bus-control signals. H = TI380C30A does not have control of the system bus L = TI380C30A has control of the system bus SPH 99 I/O System parity high. SPH is the optional odd-parity bit for each address or data byte transmitted over SADH0–SADH7 (see Note 1). SPL 92 I/O System parity low. SPL is the optional odd-parity bit for each address or data byte transmitted over SADL0–SADL7 (see Note 1). Intel mode SRAS/SAS 76 H = Transparent mode L = Holds latched values of SCS, SRSX–SRS2, and SBHE Falling edge = Latches SCS, SRSX – SRS2, and SBHE I/O Motorola mode Intel mode SRD/SUDS 98 I/O Motorola mode Intel mode SRDY/SDTACK 97 SRAS is used for system memory-address strobe (see Note 7). SRAS is used to latch the SCS and SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is tied to the SALE output of the system bus. The latching capability can be defeated since the internal latch for these inputs remains transparent as long as SRAS remains high. This permits SRAS to be pulled high and the signals at SCS, SRSX – SRS2, and SBHE to be applied independently of the SALE strobe from the system bus. During DMA, SRAS remains an input. SAS is used for sytem-memory address strobe (see Note 7). SAS is an active-low address strobe that is an input during DIO (although ignored as an address strobe) and an output during DMA. H = Address is not valid L = Address is valid and a transfer operation is in progress SRD is used for system-read strobe (see Note 7). SRD is the active-low strobe indicating that a read cycle is performed on the system bus. SRD is an input during DIO and an output during DMA. H = Read cycle is not occurring L = If DMA, host provides data to system bus. If DIO, SIF provides data to system bus SUDS is used for upper-data strobe (see Note 7). SUDS is the active-low upper-data strobe. SUDS is an input during DIO and an output during DMA. H = Not valid data on SADH0–SADH7 lines L = Valid data on SADH0–SADH7 lines SRDY is used for system bus ready (see Note 7). SRDY indicates to the bus master that a data transfer is complete. SRDY is asynchronous, but during DMA and pseudo-DMA cycles, it is internally synchronized to SBCLK. During DMA cycles, SRDY must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state. SRDY is an output when the TI380C30A is selected for DIO; otherwise, it is an input. H = System bus is not ready L = Data transfer is complete; system bus is ready I/O Motorola mode SDTACK is used for system data-transfer acknowledge (see Note 7). The purpose of SDTACK is to indicate to the bus master that a data transfer is complete. SDTACK is internally synchronized to SBCLK. During DMA cycles, SDTACK must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state. SDTACK is an output when the TI380C30A is selected for DIO; otherwise, it is an input. H = System bus is not ready L = Data transfer is complete; system bus is ready † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTES: 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).123456 7. Terminal should be tied to VDD with a 4.7-kΩ pullup resistor. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL NAME SRESET NO. 62 I/O/E† I DESCRIPTION System reset. SRESET is activated to place the TI380C30A into a known initial state. Hardware reset puts most of the TI380C30A outputs into the high-impedance state and places all blocks into the reset state. The Intel-mode DMA bus-width selection (S8) is latched on the rising edge of SRESET. H = No system reset L = System reset Rising edge = Latch bus width for DMA operations (for Intel-mode applications) SRSX and SRS0–SRS2 are used for system-register select. These inputs select the word or byte to be transferred during a system DIO access. The MSB is SRSX and the LSB is SRS2 (see Note 1). Intel mode Register selected = SRSX SRS0 SRS1 SRS2/SBERR 65 64 63 70 I SRS1 LSB SRS2/SBERR Register selected = MSB SRSX SRS0 LSB SRS1 SBERR is used for bus error. SBERR corresponds to the bus-error signal of the 68xxx microprocessor. It is internally synchronized to SBCLK. SBERR is driven low during a DMA cycle to indicate to the TI380C30A that the cycle must be terminated (see section 3.4.5.3 of the TMS380 Second-Generation Token-Ring User’s Guide, literature number SPWU005, for more information). SWR is used for system-write strobe (see Note 7). SWR is an active-low write strobe that is an input during DIO and an output during DMA. Intel mode 77 SRS0 SRSX, SRS0, and SRS1 are used for system-register select. These inputs select the word or byte to be transferred during a system DIO access. The most significant bit is SRSX and the least significant bit is SRS1 (see Note 1). Motorola mode SWR/SLDS MSB SRSX H = Write cycle is not occurring L = If DMA, data to be driven from SIF to host bus. If DIO, on the rising edge, the data is latched and written to the selected register I/O Motorola mode SLDS is used for lower-data strobe (see Note 7). SLDS is an input during DIO and an output during DMA. H = Not valid data on SADL0–SADL7 lines L = Valid data on SADL0–SADL7 lines SXAL 79 O System extended-address latch. SXAL provides the enable pulse used to externally latch the most significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address counter causes a carry-out of the lower 16 bits). Systems that implement parity on addresses can use SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension. SYNCIN 12 I Reserved. SYNCIN must be left unconnected (see Note 1). S4/16 155 I H = 4-Mbit/s data rate L = 16-Mbit/s data rate Speed switch. S4/16 specifies the token-ring data rate for the physical layer (see Note 1). † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTES: 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).123456 7. Terminal should be tied to VDD with a 4.7-kΩ pullup resistor. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL NAME NO. I/O/E† DESCRIPTION Intel mode S8/SHALT 69 H = Selects 8-bit mode (see Note 1) L = Selects 16-bit mode I Motorola mode TCLK TMS TDI TDO 7 8 165 164 S8 is used for system 8-/16-bit bus select. S8 selects the bus width used for communications through the system interface. On the rising edge of SRESET, the TI380C30A latches the DMA bus width; otherwise, the value on S8 dynamically selects the DIO bus width. SHALT is used for system halt/bus error retry. If SHALT is asserted along with bus error (SBERR), the adapter retries the last DMA cycle. This is the rerun operation as defined in the 68xxx specification. The BERETRY counter is not decremented by SBERR when SHALT is asserted (see section 3.4.5.3 of the TMS380 Second-Generation Token-Ring User’s Guide, literature number SPWU005, for more information). I (see Note 1) I (see Note 1) I (see Note 1) O Test ports used during the production test of the device. TCLK, TMS, TDI, and TDO must be left unconnected. TEST0 TEST1 TEST2 116 115 114 I I I Network select inputs. TEST0–TEST2 are used to select the network speed and type to be used by the TI380C30A. These inputs should be changed only during adapter reset. Connect TEST2 to VDDL. TEST0 TEST1 TEST2 Description L NC H 16-Mbit/s token ring H NC H 4-Mbit/s token ring X X L Reserved TEST3 TEST4 TEST5 113 112 111 I I I Test inputs. TEST3–TEST5 should be left unconnected (see Note 1). Module-in-place test mode is achieved by tying TEST3 and TEST4 to ground. In this mode, all TI380C30A outputs are in the high-impedance state. Internal pullups on all TI380C30A inputs are disabled (except TEST3–TEST5). TRST 9 I VDD 14 29 45 87 103 119 — Positive-supply voltage for commprocessor output buffers. All VDD pins must be attached to the common-system power-supply plane. VDDA1 VDDA2 148 — Positive-supply voltage for receiver circuits 129 — Positive-supply voltage for data recovery PLL VDDA3 VDDD 123 Test-port reset. TRST should be tied to ground for normal operation of the TI380C30A (see Note 1). H = Reserved L = Test ports forced to an idle state Positive-supply voltage for the current-bias generator 157 — Positive-supply voltage for physical layer output buffers VDDL 13 47 71 — Positive-supply voltage for commprocessor digital logic. All VDDL pins must be attached to the common-system power-supply plane. VDDL1 134 146 — Positive-supply voltage for physical layer digital logic. All VDDL pins must be attached to the common-system power-supply plane. 133 — Positive-supply voltage for XTAL oscillator 138 — Positive-supply voltage for phantom drive VDDO VDDP VDDX 145 — Positive-supply voltage for transmit output † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTE 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL I/O/E† DESCRIPTION 11 30 38 78 104 — Ground connections for commprocessor output buffers. All VSS pins must be attached to system ground plane. VSSA1 VSSA2 150 — Ground reference for receiver circuits 127 — Ground reference for data-recovery PLL VSSA3 125 VSSC 10 21 57 102 NAME VSS VSSC1 VSSD NO. Ground reference for the current-bias generator — 160 Ground reference for commprocessor output buffers (clean ground). All VSSC pins must be attached to the common-system ground plane. Ground reference for physical layer output buffers 159 — Ground reference for physical layer output buffers VSSL 22 46 88 120 — Ground reference for digital logic. All VSSL pins must be attached to the common-system ground plane. VSSL1 136 153 — Ground reference for internal logic VSSO VSSP 131 — Ground reference for XTAL oscillator 140 — Ground reference for phantom drive VSSX 142 — Ground reference for transmit output WFLT WRAP XFAIL 167 170 117 O O I Phantom-wire fault. WFLT provides an indication of the presence of a short or open circuit on PHOUTA or PHOUTB. H = No fault L = Open or short. The DC fault condition is present in the phantom-drive lines. Internal wrap mode control. WRAP indicates the TI380C30A has placed the physical layer in the loopback-wrap mode for adapter self test. H = Normal ring operation L = Physical-layer wrap mode selected External fail-to-match signal. An EACO device uses XFAIL to indicate to the TI380C30A that it should not copy the frame nor set the address-recognize indicator/frame-copied indicator (ARI/FCI) bits in a token-ring frame due to an external address match.The ARI/FCI bits in a token-ring frame can be set due to an internal address-matched frame. If an EACO device is not used, XFAIL must be left unconnected. XFAIL is ignored when copy-all-frames (CAF) mode is enabled [see table in XMATCH description section (see Note 1)]. H = No address match by external address checker L = External address-checker-armed state External match signal. An EACO device uses XMATCH to indicate to the TI380C30A to copy the frame and set the ARI/FCI bits in a token-ring frame. If an EACO device is not used, XMATCH must be left unconnected. XMATCH is ignored when CAF mode is enabled (see Note 1). H = Address match recognized by external address checker L = External address-checker-armed state XMATCH 118 I XMATCH 0 0 1 1 Hi-Z XFAIL 0 1 0 1 Hi-Z Function Armed (processing frame data) Do not externally match the frame (XFAIL takes precedence) Copy the frame Do not externally match the frame (XFAIL takes precedence) Reset state (adapter not initialized) † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning NOTE 1. Terminal has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Terminal Functions (Continued) TERMINAL NAME NO. I/O/E† DESCRIPTION XMT+ XMT– 143 144 E Transmit differential outputs. XMT+ and XMT– provide a low-impedance differential source for line drive by way of filtering and transformer isolation. XT1 XT2 130 132 I E XTAL connection. An 8-MHz crystal network can be connected here to provide a reference clock for the TI380C30A. Alternatively, an 8-MHz TTL clock source can be connected to XT1. † I = input, O = output, E = provides external-component connection to the internal circuitry for tuning architecture The major blocks of the TI380C30A include the CP, SIF, MIF, PH, CG, ASF, and PHY. The functionality of each block is described in the following sections. communications processor (CP) The CP performs the control and monitoring of the other functional blocks in the TI380C30A. The control and monitoring protocols are specified by the software (downloaded or ROM-based) in local memory. Available protocols include: D D D Media access control (MAC) software Logical link control (LLC) software Copy all frames (CAF) software The CP is a proprietary 16-bit central processing unit (CPU) with data cache and a single prefetch pipe for pipelining of instructions. These features enhance the TI380C30A maximum performance capability to about 8 million instructions per second (MIPS), with an average of about 5 MIPS. system interface (SIF) The SIF performs the interfacing of the LAN subsystem to the host system. This interface can require additional logic depending on the application. The system interface can transfer information/data using any of these three methods: D D D Direct memory access (DMA) Direct input/output (DIO) Pseudo-direct memory access (PDMA) DMA (or PDMA) is used to transfer all data to/from host memory from/to local memory. The main uses of DIO are loading the software to local memory and initializing the TI380C30A. DIO also allows command/status interrupts to occur to and from the TI380C30A. The system interface can be hardware-selected for either of two modes by using SI/M. The mode selected determines the memory organizations and control signals used. These modes are: D D The Intel mode (80x8x families): 8-, 16-, and 32-bit bus devices The Motorola mode (68xxx microprocessor family): 16- and 32-bit bus devices The system interface supports host-system memory addressing up to 32 bits (32-bit reach into the host system memory). This allows greater flexibility in using/accessing host-system memory. System designers are allowed to customize the system interface to their particular bus by: D D Programmable burst transfers or cycle-steal DMA operations Optional parity protection These features are implemented in hardware to reduce system overhead, facilitate automatic rearbitration of the bus after a burst, or repeat a cycle when errors occur (parity or bus). Bus retries are also supported. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 system interface (SIF) (continued) The system-interface hardware also includes features to enhance the integrity of the TI380C30A operation and the data. These features include: D D D Always internally maintain odd-byte parity regardless of parity being disabled Monitor for the presence of a clock failure Provide switchable SIF speeds at 2 MHz to 33 MHz On every cycle, the system interface compares all the system clocks to a reference clock. If any of the clocks becomes invalid, the TI380C30A enters the slow-clock mode, which prevents latch-up of the TI380C30A. If the SBCLK is invalid, any DMA cycle is terminated immediately; otherwise, the DMA cycle is completed and the TI380C30A is placed in slow-clock mode. When the TI380C30A enters the slow-clock mode, the clock that failed is replaced by a slow free-running clock, and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the TI380C30A must be reinitialized. For DMA with a 16-MHz clock, a continuous transfer rate of 64 MBps [8 megabytes per second (MBps)] can be obtained. For DMA with a 25-MHz clock, a continuous transfer rate of 96 Mbit/s (12 MBps) can be obtained. For DMA with a 33-MHz clock, a continuous transfer rate of 128 Mbit/s (16 MBps) can be obtained. For 8-bit and 16-bit pseudo-DMA, the data rates in Table 2 can be obtained. Table 2. Pseudo-DMA Data Rates LOCAL BUS SPEED 8-BIT PDMA 16-BIT PDMA 4 MHz 48 Mbit/s 64 Mbit/s 6 MHz 72 Mbit/s 96 Mbit/s Since the main purpose of DIO is for downloading and initialization, the DIO transfer rate is not a significant issue. memory interface (MIF) The MIF performs memory management to allow the TI380C30A to address 2 Mbytes in local memory. Hardware in the MIF allows the TI380C30A to be connected directly to DRAMs without additional circuitry. This glueless-DRAM connection includes the DRAM-refresh controller. The MIF also handles all internal bus arbitration between these blocks. When required, the MIF arbitrates for the external bus. The MIF is responsible for the memory mapping of the CPU of a task. The memory maps of DRAMs, EPROMs, burned-in addresses (BIAs), and external devices are addressed appropriately when required by the system interface, the protocol handler, or for a DMA transfer. The memory interface is capable of a 64-Mbit/s continuous transfer rate when using a 4-MHz local bus (64-MHz device crystal) and a 96-Mbit/s continuous transfer rate when using a 6-MHz local bus. protocol handler (PH) The PH performs the hardware-based real-time protocol functions for a token-ring LAN. Network type is determined by TEST0–TEST2. The token-ring network speed is determined by software and can be either 16 Mbit/s or 4 Mbit/s. These speeds are fixed by the software, not by the hardware. The PH converts the parallel-transmit data to serial-network data of the appropriate coding and converts the received serial data to parallel data. The PH data-management state machines direct the transmission/reception of data to/from local memory through the MIF. The PH buffer-management state machines automatically oversee this process, directly sending/receiving linked lists of frames without CPU intervention. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 protocol handler (continued) The PH contains many state machines that perform the following functions: D D D D D D D Transmit and receive frames Capture tokens Provide token-priority controls Manage the TI380C30A buffer memory Provide frame-address recognition (group, specific, functional, and multicast) Provide internal parity protection Control and verify the physical-layer circuitry-interface signals Integrity of the transmitted and received data is controlled by cyclic-redundancy checks (CRC), detection of network-data violations, and parity on internal data paths. All data paths and registers are optionally parity-protected to maintain functional integrity. clock generator (CG) The CG performs the generation of all internal clocks required by the other functional blocks, including the local memory-bus clocks (MBCLK1, MBCLK2). The CG also generates the reference timer used to sample all input clocks (SBCLK, OSCIN, RCLK, and PXTAL). If no transition is detected within the period of the reference timer on any input clock signal, the CG places the TI380C30A into slow-clock mode. The frequency of the reference timer is in the range of 10 kHz–100 kHz. adapter-support function (ASF) The ASF performs support functions not contained in the other blocks. The features are: D D D D The TI380C30A base timer Identification, management, and service of internal and external interrupts Test-pin mode control, including the unit-in-place mode for board testing Checks for illegal states, such as illegal opcodes and parity physical-layer interface (PHY) The major blocks of the TI380C30A PHY include the receiver/equalizer, clock recovery PLL, wrap function, phantom drive with wire-fault detector, and watchdog timer. Figure 2 is the block diagram illustrating these major blocks, and the functionality of each block is described in the following sections. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 External Equalizer WRAP EQ+ EQ– XTAL 8 MHz XT1 S4/16 ATEST FRAQ XT2 OSC CKT RCV+ RCV– Receiver NABL PXTAL RCVR RCV Data Receiver Clock Recovery RCLK OSC32 FRAQ REDY DRVR+ DRVR– XMT+ Transmit XMT– WFLT PHOUTA Phantom Drive PHOUTB PWRDN Rate Error NSRT (internal) Bias Gen IREF RATER Watchdog Timer (22 ms) Test Port TDI TDO TCLK TMS TRST Figure 2. Functional Block Diagram of the PHY receiver Figure 3 shows the arrangement of the line-receiver/equalizer circuit. The differential-input pair, RCV+ and RCV–, are designed to be connected to a floating winding of an isolation transformer. Each is equipped with a bias circuit to center the operating point of the differential input at approximately VDD ÷ 2. The differential-input pair consists of a pair of metal oxide semiconductor field effect transistors (MOSFETs), each with an identical current source in its source terminal that is set to supply a nominal current of 1.5 mA. At low signal levels, the gain of this pair is inversely proportional to the impedance connected between their sources on EQ– and EQ+. A frequency-equalization network can be connected between EQ+ and EQ– to provide equalization for media-signal distortion. The internal-wrap mode is provided for self-test of the device. When selected by taking WRAP low, the normal input path is disabled by a multiplexer and a path is enabled from the DRVR+/DRVR– input pair. Receiver gain, thresholds, and equalization are unchanged in the internal-wrap mode. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 VDD LOAD LOAD Bias Network RCV– WRAP MUX RCV+ DATA External Equalizer EQ+ R1 R2 DATA EQ– WRAP IEQB From DRVR+/DRVR– C1 IEQB VSS Figure 3. Line Receiver/Equalizer receiver-clock recovery The clock and data recovery in the TI380C30A is performed by an advanced, digitally controlled PLL. In contrast to the TMS38054, the PLL of the TI380C30A is digitally controlled and the loop parameters are set by internally programmed digital constants. This results in precise control of loop parameters and requires no external loop-filter components. The TI380C30A implements an intelligent algorithm to determine the optimum phase position for data sampling and extracted-clock synthesis. The resulting action of the TI380C30A can be modeled as two cascaded PLLs as shown in Figure 4. RCLK RCV Data PLL1 PLL2 RCVR f3dB ≅ 680 kHz (see Note A) f3dB ≅ 162 kHz (see Note A) NOTE A: f3dB = 3-dB bandwidth of PLL Figure 4. Dual-PLL Arrangement POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 receiver-clock recovery (continued) PLL1 represents the algorithm to recover data from the incoming stream detected by the receiver. It has a relatively high bandwidth to provide good jitter tolerance. Data and embedded-clock-phase information are fed as digital values to PLL2, which generates the extracted clock (RCLK) for the commprocessor. The recovered data is sent to the commprocessor as the RCVR signal in synchronization with RCLK. In addition to sampling the RCVR signal, the commprocessor uses RCLK to retransmit data in most cases. The lower bandwidth of PLL2 greatly reduces the rate of accumulation of data-correlated phase jitter in a token-ring network and provides very good accumulated-phase-slope (APS) characteristics. In addition to RCLK, the token-ring reference clock (PXTAL) and a fixed-frequency 32-MHz clock (OSC32) are also synthesized from the 8-MHz crystal reference. line driver and wrap function The line-drive function of the TI380C30A is performed by XMT+/XMT–. Unlike the TMS38054, these pins are low-impedance outputs and require external-series resistance to provide line termination. These pins provide buffering of the differential signal from the PH on DRVR+/DRVR– with action to control skew and asymmetry, and with no retiming in the transmit path. The wrap function is designed to provide a signal path for system self-test diagnostics. When the PH drives WRAP low, the receiver inputs are ignored and the transmit signal is fed to the receiver input circuitry by way of a multiplexer. In the internal wrap mode, WRAP can be checked by observing the signal amplitude at the equalization pins, EQ+ and EQ–. Equalization is active at this signal level, although the signal does not exhibit the high-frequency attenuation effects for which equalization is intended to compensate. During wrap mode, both XMT+/XMT– are driven to a low state to prevent any dc current from flowing into the isolation transformer. phantom driver and wire-fault detection The phantom-drive circuit under control of NSRT generates a dc voltage on both of the phantom-drive outputs, PHOUTA and PHOUTB. To maintain the phantom drive, NSRT is toggled by the TI380C30A at least once every 20 ms. A watchdog timer is included in the TI380C30A to remove the phantom drive if NSRT does not have the required transitions. The watchdog timer normally is not allowed to expire because it is being reinitialized at least every 20 ms. If there is a problem in the TI380C30A or its microcode, resulting in failure to toggle NSRT, the timer expires in a maximum of 22 ms. If this happens, the phantom drive is deasserted and remains so until the next falling edge of NSRT. The watchdog timer requires no external-timing components. When the phantom drive is deasserted, the phantom-drive lines are actively pulled low, reaching a level of 1 V or less within 50 ms. The dc voltage from PHOUTA and PHOUTB is superimposed on the transmit-signal pair to the trunk-coupling unit (TCU) to request that the station be inserted into the ring. This is achieved by connecting the transmit-signal pair to the center of the secondary winding of the transmit-isolation transformer. Since PHOUTA and PHOUTB are connected to the media side of the isolation transformer, they require extensive protection against line surges. A capacitor is connected between the two phantom lines to provide an ac path for the transmit signal, while PHOUTA and PHOUTB independently drive the dc voltage on each of the transmit lines, allowing for independent wire-fault detection on each. The phantom voltage is detected by the TCU, causing the external wrap path from the transmitter outputs back to the receiver inputs to be broken and the ring to be broken. A signal connection is established from the ring to the receiver inputs and from the transmitter outputs to the ring. The return current from the dc-phantom voltage on the transmit pair is returned to the station by way of the receive pair. This provides some measure of wire-fault detection on the receive lines. The phantom-drive outputs are current limited to prevent damage if short-circuited. They detect either an abnormally high or an abnormally low load current at either output corresponding to a short or an open circuit in the ring or TCU wiring. Either type of fault results in the wire-fault indicator output (WFLT) being driven low. The logic state of WFLT is high when the phantom drive is not active. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 frequency acquisition and REDY Unlike its predecessors, the TMS3805x family, the data-recovery PLL of the TI380C30A physical layer does not require constant frequency monitoring; neither is it necessary to recenter its frequency by way of the FRAQ control line. When the commprocessor asserts FRAQ, it initiates a reset of the clock-recovery PLL. The REDY signal is deasserted for the duration of this action and reasserted low when it is complete (a maximum of 3 µs later). This low-going transition of REDY is required by the commprocessor following the setting of FRAQ high to indicate to the PH that any frequency error that it could have detected has been corrected. REDY is not asserted if no incoming transitions are detected by the rate-error function. rate error (RATER) function RATER provides an indication that incoming data transitions are present on the RCV+/RCV– pair, but that the rate of transitions is outside the range that is expected for the ring speed selected by S4/16. RATER is not asserted low if no incoming transitions are present. In wrap mode, the rate-error function monitors the transitions on the DRVR+/DRVR– pair. The rate-error function interprets 16 or more transitions in a 1.5-ms period as valid 16-Mbit/s data. It interprets 15 or fewer transitions in a 1.5-ms period as 4-Mbit/s data. One transition or less in a 1.5-ms period is interpreted as no incoming transitions, in which case, RATER and REDY are not asserted low. power-down control The TI380C30A PHY can be disabled by the PWRDN signal. If PWRDN is taken low, all outputs of the PHY are in the high-impedance state and all internal logic is powered down, bringing power consumption to a very low level. Upon taking PWRDN high, the device resets and initializes itself. This process could take up to 2 ms and care should be taken to ensure that the system does not require stable clocks during this period. user-accessible hardware registers and TI380C30A-internal pointers Table 3 and Table 4 show how to access internal data by way of pointers and how to address the registers in the host interface. The SIF adapter-control (SIFACL) register, which directly controls device operation, is described in detail. The adapter-internal pointers table is defined only after TI380C30A initialization and until the OPEN command is issued. These pointers are defined by the TI380C30A software (microcode), and this table describes the release 2.x software. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Table 3. Adapter-Internal Pointers for Token Ring† ADDRESS >00.FFF8‡ DESCRIPTION Pointer to software raw microcode level in chapter 0 >00.FFFA‡ Pointer to starting location of copyright notices. Copyright notices are separated by a >0A character and terminated by a >00 character in chapter 0. >01.0A00 Pointer to burned-in address in chapter 1 >01.0A02 Pointer to software level in chapter 1 >01.0A04 Pointer to TI380C30A addresses in chapter 1: Pointer + 0 node address Pointer + 6 group address Pointer + 10 functional address >01.0A06 Pointer to TI380C30A parameters in chapter 1: Pointer + 0 physical-drop number Pointer + 4 upstream neighbor address Pointer + 10 upstream physical-drop number Pointer + 14 last ring-poll address Pointer + 20 reserved Pointer + 22 transmit access priority Pointer + 24 source class authorization Pointer + 26 last attention code Pointer + 28 source address of the last received frame Pointer + 34 last beacon type Pointer + 36 last major vector Pointer + 38 ring status Pointer + 40 soft-error timer value Pointer + 42 ring-interface error counter Pointer + 44 local ring number Pointer + 46 monitor error code Pointer + 48 last beacon-transmit type Pointer + 50 last beacon-receive type Pointer + 52 last MAC-frame correlator Pointer + 54 last beaconing-station upstream neighbor address (UNA) Pointer + 60 reserved Pointer + 64 last beaconing-station physical-drop number >01.0A08 Pointer to MAC buffer (a special buffer used by the software to transmit adapter-generated MAC frames) in chapter 1 >01.0A0A Pointer to LLC counters in chapter 1: Pointer + 0 MAX_SAPs Pointer + 1 open SAPs Pointer + 2 MAX_STATIONs Pointer + 3 open stations Pointer + 4 available stations Pointer + 5 reserved >01.0A0C Pointer to 4-/16-Mbit/s word flag. If zero, the adapter is set to run at 4 Mbit/s. If nonzero, the adapter is set to run at 16 Mbit/s. >01.0A0E Pointer to total TI380C30A RAM found in 1K bytes in RAM allocation test in chapter 1. † This table describes the pointers for release 2.x of the TI380C30A software. ‡ This address valid only for microcode release 2.x 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Table 4. User-Access Hardware Registers 80x8x 16-BIT MODE (SI/M = 1, S8/SHALT = 0)† NORMAL MODE SBHE = 0, SRS2 = 0 WORD TRANSFERS BYTE TRANSFERS SBHE = 1, SRS2 = 0 SBHE = 0, SRS2 = 1 SBHE = 1, SRS2 = 0 SIFDAT MSB SIFDAT LSB SDMADAT MSB SDMADAT LSB SIFDAT/INC MSB SIFDAT/INC LSB DMALEN MSB DMALEN LSB SIFADR MSB SIFADR LSB SDMAADR MSB SDMAADR LSB SIFCMD SIFSTS SDMAADX MSB SDMAADX LSB 0 SIFACL MSB SIFACL LSB SIFACL MSB SIFACL LSB 0 1 SIFADR MSB SIFADR LSB SIFADR MSB SIFADR LSB 1 0 SIFADX MSB SIFADX LSB SIFADX MSB SIFADX LSB DMALEN LSB DMALEN MSB DMALEN LSB SRSX SRS0 SRS1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 1 SBHE = 0, SRS2 = 1 PSEUDO-DMA MODE ACTIVE SBHE = 0, SRS2 = 0 1 1 1 DMALEN MSB † SBHE = 1 and SRS2 = 1 are not defined. 80x8x 8-BIT MODE (SI/M = 1, S8/SHALT = 1) SRSX SRS0 SRS1 SRS2 NORMAL MODE SBHE = X PSEUDO-DMA MODE ACTIVE SBHE = X 0 0 0 0 SIFDAT LSB SDMADAT LSB 0 0 0 1 SIFDAT MSB SDMADAT MSB 0 0 1 0 SIFDAT MSB DMALEN LSB 0 0 1 1 SIFDAT MSB DMALEN MSB 0 1 0 0 SIFADR LSB SDMAADR LSB 0 1 0 1 SIFADR MSB SDMAADR MSB 0 1 1 0 SIFSTS SDMAADX LSB 0 1 1 1 SIFCMD SDMAADX MSB 1 0 0 0 SIFACL LSB SIFACL LSB 1 0 0 1 SIFACL MSB SIFACL MSB 1 0 1 0 SIFADR LSB SIFACL LSB 1 0 1 1 SIFADR MSB SIFACL MSB 1 1 0 0 SIFADX LSB SIFADX LSB 1 1 0 1 SIFADX MSB SIFADX MSB 1 1 1 0 DMALEN LSB DMALEN LSB 1 1 1 1 DMALEN LSB DMALEN MSB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Table 4. User-Access Hardware Registers (Continued) 68xxx MODE (SI/M = 0)† WORD TRANSFERS BYTE TRANSFERS NORMAL MODE SUDS = 0, SLDS = 0 SUDS = 1, SLDS = 0 SUDS = 0, SLDS = 1 SUDS = 1, SLDS = 0 SIFDAT MSB SIFDAT LSB SDMADAT MSB SDMADAT LSB SIFDAT/INC MSB SIFDAT/INC LSB DMALEN MSB DMALEN LSB SIFADR MSB SIFADR LSB SDMAADR MSB SDMAADR LSB SIFCMD SIFSTS SDMAADX MSB SDMAADX LSB 0 SIFACL MSB SIFACL LSB SIFACL MSB SIFACL LSB 0 1 SIFADR MSB SIFADR LSB SIFADR MSB SIFADR LSB 1 0 SIFADX MSB SIFADX LSB SIFADX MSB SIFADX LSB DMALEN LSB DMALEN MSB DMALEN LSB SRSX SRS0 SRS1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 1 SUDS = 0, SLDS = 1 1 1 1 DMALEN MSB † 68xxx mode is always a 16-bit mode. 26 PSEUDO-DMA MODE ACTIVE SUDS = 0, SLDS = 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 SIF adapter-control (SIFACL) register The SIFACL register allows the host processor to control, and to some extent, reconfigure the TI380C30A under software control (see Table 5). SIFACL Register Bit No. 0 1 2 T E S T 0 T E S T 1 T E S — SWHLDA T 2 R R R Legend: R = W = P = S = –n = b = p = u = 3 4 RW –0 5 6 7 8 9 10 11 12 13 14 15 SWDDIR SWHRQ PSDMAEN ARESET CPHALT BOOT LBP SINTEN PEN NSEL OUT0 NSEL OUT1 R –U R –0 RS –0 RW –0 RP –b RP –b RP –0 RW –1 RP –p RP –0 RP –1 Read Write Write during ARESET = 1 only Set only Value after reset Value on BTSTRP Value on PRTYEN Indeterminate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Table 5. SIFACL Bit Definitions BIT NAME 0–2 TEST0 TEST1 TEST2 3 Reserved FUNCTION Value on TEST0 and TEST2 pins. These bits are read-only bits and reflect the value on the corresponding device pins. This allows the host software (S/W) to determine speed configuration. If the network speed and type are software-configurable, these bits are used to determine the configurations that are supported by the network hardware. TEST0 L H X TEST1 NC NC X TEST2 H H L Description 16-Mbit/s token ring 4-Mbit/s token ring Reserved Read data should be 0. Software-hold acknowledge. Allows the function of SHLDA/SBGR to be emulated from software control for pseudo-DMA mode. 4 SWHLDA PSDMAEN 0† 1† 1† 1† SWHLDA X 0 0 1 SWHRQ X 0 1 X Result SWHLDA value in the SIFACL register cannot be set to a 1. No pseudo-DMA request pending Indicates a pseudo-DMA request interrupt Pseudo-DMA process in progress † The value on SHLDA/SBGR is ignored. 5 6 SWDDIR SWHRQ Current SDDIR signal value. Contains the current value of the pseudo-DMA direction. This enables the host to easily determine the direction of DMA transfers, which allows system DMA to be controlled by system software. 0 = Pseudo DMA from host system to TI380C30A 1 = Pseudo DMA from TI380C30A to host system Current SHRQ signal value. Contains the current value on SHRQ/SBRQ when in Intel mode and the inverse of the value on SHRQ/SBRQ in Motorola mode. This enables the host to easily determine if a pseudo-DMA transfer is requested. Intel Mode (SI/M = H) 0 = System bus not requested 1 = System bus requested Motorola Mode (SI/M = L) 1 = System bus not requested 0 = System bus requested Pseudo-system-DMA enable. Enables pseudo-DMA operation. 7 8 PSDMAEN ARESET 0 = Normal bus-master DMA operation is possible. 1 = Pseudo-DMA operation selected. Operations dependent on the values of the SWHLDA and SWHRQ bits in the SIFACL register. Adapter reset. ARESET is a hardware reset of the TI380C30A. This bit has the same effect as SRESET except that the DIO interface to the SIFACL register is maintained. This bit is set to 1 if a clock failure is detected (OSCIN, PXTAL, RCLK, or SBCLK not valid). 0 = TI380C30A operates normally. 1 = TI380C30A is held in the reset condition. 9 10 CPHALT BOOT Communications processor halt. Controls the TI380C30A processor access to the internal TI380C30A buses. This prevents the TI380C30A from executing instructions before the microcode is downloaded. 0 = TI380C30A processor can access the internal TI380C30A buses. 1 = TI380C30A processor cannot access the internal-adapter buses. Bootstrap CP code. Indicates whether the memory in chapters 0 and 31 of the local-memory space is RAM or ROM/PROM/EPROM. This bit controls the operation of MCAS and MROMEN. 0 = ROM/PROM/EPROM memory in chapters 0 and 31 1 = RAM memory in chapters 0 and 31 Local bus priority. Controls the priority levels of devices on the local bus. 11 LBP 0 = No external devices (such as TI380FPA) are used with the TI380C30A. 1 = An external device (such as TI380FPA) is used with the TI380C30A. This allows the external bus master to operate at the necessary priority on the local bus. If the system uses the TMS380SRA only, the bit must be set to 0. If the system uses both the TMS380SRA and the TI380FPA, the bit must be set to 1. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Table 5. SIFACL Bit Definitions (Continued) BIT NAME FUNCTION System-interrupt enable. Allows the host processor to enable or disable system-interrupt requests from the TI380C30A. The system-interrupt request from the TI380C30A is on SINTR/SIRQ. The following equation shows how SINTR/SIRQ is driven: SINTR/SIRQ = (PSDMAEN * SWHRQ * !SWHLDA) + (SINTEN * SYSTEM_INTERRUPT) Results of the states are: 12 SINTEN System Interrupt (SIFTS SINTEN Register) Result PSDMAEN 1† 1† SWHRQ SWHLDA 1 1 1 0 X X X X 1† X 0 0 X X 0 X X X 1 1 X 1 0 0 X 0 X X † The value on SHLDA/SBGR is ignored. Pseudo DMA is active. TI380C30A generates a system interrupt for a pseudo DMA. Not a pseudo-DMA interrupt TI380C30A generates a system interrupt. TI380C30A does not generate a system interrupt. TI380C30A cannot generate a system interrupt. Parity enable. Determines whether data transfers within the TI380C30A are checked for parity. 13 PEN 0 = Data transfers are not checked for parity. 1 = Data transfers are checked for correct odd parity. Network-selection outputs. Values control NSELOUT0 and NSELOUT1. These bits can be modified only while the ARESET bit is set. These bits can be used to software-configure a TI380C30A: NSELOUT0 should be connected to TEST0 (TEST1 should be left unconnected and TEST2 should be tied high). NSELOUT0 and NSELOUT1 are used to select network speed as follows: 14–15 NSELOUT0 NSELOUT1 NSELOUT0 0 0 1 1 NSELOUT1 0 1 0 1 Selection Reserved 16-Mbit/s token ring Reserved 4-Mbit/s token ring At power up, these bits are set corresponding to 16-Mbit/s token ring (NSELOUT1 = 1, NSELOUT0 = 0). New values are saved only if written in the same cycle that the ARESET bit is cleared. SIFACL control for pseudo-DMA operation Pseudo-DMA operation is software-controlled by using five bits in the SIFACL register. The logic model for the SIFACL control of pseudo-DMA operation is shown in Figure 5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 Motorola Mode Internal Signals Host Interface SYSTEM_INTERRUPT (SIFSTS register) DMA Request M U X SINTR/SIRQ M U X SHRQ/SBRQ SHLDA/SBGR M U X DMA Grant SDDIR DMADIR ... SWHLDA SWDDIR SWHRQ . . . PSDMAEN SINTEN ... SIFACL Register Figure 5. Pseudo-DMA Logic Related to SIFACL Bits absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range (see Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 W Operating case temperature, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 95°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 8: Voltage values are with respect to VSS, and all VSS pins should be routed so as to minimize inductance to system ground. 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 recommended operating conditions VDD Supply voltage VIH High-level input voltage VIL IOH Low-level input voltage, TTL-level signal (see Note 9) High-level output current TTL outputs IOL TC Low-level output current (see Note 10) TTL outputs TTL-level signal MIN NOM MAX UNIT 4.75 5 5.25 V VDD+0.3 VDD+0.3 V 2 OSCIN 2.4 RCLK, PXTAL, RCVR, XT1 2.6 –0.3 Operating case temperature VDD+0.3 0.8 V –400 µA 2 mA 95 °C 0 NOTES: 9. The algebraic convention, where the more-negative (less-positive) limit is designated as a minimum, is used for logic-voltage levels only. 10. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst case). electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) TEST CONDITIONS† PARAMETER VOH VOL High-level output voltage, TTL-level signal (see Note 11) Low-level output voltage, TTL-level signal IOZ High impedance output current High-impedance II Input current, any input or input/output ICC Supply current Ci Co Normal mode Power-down mode VDD = MIN, VDD = MIN, IOH = MAX IOL = MAX VDD = MAX, VDD = MAX, VO = 2.4 V VO = 0.4 V MIN TYP MAX 2.4 V 0.6 20 –20 ± 20 VI = VSS to VDD VDD = MAX UNIT 200 V µA µA mA Input capacitance, any input VDD = 5 V f = 1 MHz, 20 Others at 0 V 15 Output capacitance, any output or input/output f = 1 MHz, Others at 0 V 15 pF pF † For conditions shown as MIN/MAX, use the appropriate value specified under the recommended operating conditions. NOTE 11: The following signals require an external pullup resistor: SRAS/SAS, SRDY/SDTACK, SRD/SUDS, SWR/SLDS, EXTINT0–EXTINT3, and MBRQ. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) (continued) receiver input (RCV+ and RCV–) PARAMETER VB TEST CONDITIONS MIN MAX VSB–1 VSB+1 UNIT Receiver-input bias voltage See Note 12 VT+ Rising-input threshold voltage VICM = VSB, Rtst = 330 Ω, See Notes 12, 13, and Figure 6 VT– Falling-input threshold voltage VICM = VSB, Rtst = 330 Ω, See Notes 12, 13, and Figure 6 –50 VAT Asymmetry threshold voltage, (VT+ + VT–)/2 VICM = VSB, Rtst = 330 Ω, See Notes 12, 13, and Figure 6 –15 15 mV Vr(CM) Rising-input common-mode rejection [VT+ (@VSB + 0.5 V) – VT+ (@VSB – 0.5 V) ] See Notes 12, 13, and Figure 6 –30 30 mV Vf(CM) Falling-input common-mode rejection [VT+ (@VSB + 0.5 V) – VT+ (@VSB – 0.5 V) ] See Notes 12, 13, and Figure 6 –30 30 mV Both inputs at VSB, See Note 12 and Figure 6 –10 10 10 60 Rtst = 330 Ω, Input under test at VSB – 1 V, Other input at VSB + 1 V, See Note 12 –10 –60 RCV+ at 4 V, RCV– at 1 V or RCV+ at 1 V, RCV– at 4 V, See Figure 6 1.0 2.2 II(RCVR) IEQB Input under test at VSB + 1 V, Other input at VSB – 1 V, See Notes 12 and 13 and Figure 6 Receiver input current Equalizer bias current 50 V mV mV µA mA VEQW Equalizer wrap voltage WRAP = low, See Figure 6 300 700 mV NOTES: 12. VSB is the self-bias voltage of the input pair RCV+ and RCV–. It is defined as VSB = (VSB+ +VSB–) ÷2 (where VSB+ is the self-bias voltage of RCV+; VSB– is the self-bias voltage of RCV–). The self-bias voltage of both pins is approximately VDD÷2. 13. VICM is the common-mode voltage applied to RCV+ and RCV–. phantom driver (PHOUTA and PHOUTB) PARAMETER TEST CONDITIONS VOH High level output voltage High-level IOS IOL Short-circuit output current IOZH IOZL Off-state output current with high-level voltage applied Low-level output current Off-state output current with low-level voltage applied MIN IOH = –1 mA IOH = –2 mA 4.1 VO = 0 V VO = VDD –4 VO = VDD VO = 0 V MAX UNIT V 3.8 V –20 mA 1 10 mA –100 100 µA –100 100 µA MIN MAX UNIT 0.15 kΩ wire fault (WFLT) (see Notes 14 and 15) PARAMETER RLS Phantom load resistance detected as short circuit RLO Phantom load resistance detected as open circuit 50 kΩ RLN Phantom load resistance detected as normal 2.9 5.5 kΩ NOTES: 14. The wire-fault circuit recognizes a fault condition for any phantom-drive load resistance to ground of greater than RLO or any load resistance less than RLS. Any resistance in the range specified for RLN is not recognized as a wire fault. A fault condition on either PHOUTA or PHOUTB results in the WFLT signal being asserted (low). 15. Resistor (RLS, RLO, RLN) connected from output under test to ground, other output loaded with 4.1 Ω to ground. PLL characteristics PARAMETER VFILT 32 TEST CONDITIONS Reference PLL operating filter voltage POST OFFICE BOX 655303 tc(XT1) = 125 ns • DALLAS, TEXAS 75265 MIN MAX 1.8 4 UNIT V TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) (continued) crystal-oscillator characteristics PARAMETER VSB(XT1) IOH(XT2) Input self-bias voltage IOL(XT2) Output low-level current TEST CONDITIONS Output high-level current V(XT2) = VSB(XT1), V(XT2) = VSB(XT1), V(XT1) = VSB(XT1) + 0.5 V V(XT1) = VSB(XT1) – 0.5 V MIN MAX UNIT 1.8 4 –2.5 –6.5 mA V 0.4 1.3 mA timing parameters The timing parameters for the signals of TI380C30A are shown in the following tables and are illustrated in the accompanying figures. The purpose of these figures and tables is to quantify the timing relationships among the various signals. The parameters are numbered for convenience. static signals Table 6 lists signals that are not allowed to change dynamically and therefore have no timing associated with them. They should be strapped high, low, or left unconnected as required. Table 6. Static Signals and Functions SIGNAL FUNCTION SI/M Host-processor select (Intel/Motorola) CLKDIV Clock divider select BTSTRP Default-bootstrap mode (RAM/ROM) PRTYEN Default-parity select (enabled/disabled) TEST0 Test pin indicates network type TEST1 NC TEST2 Test pin indicates network type TEST3 TEST4 Test pin for TI manufacturing test† Test pin for TI manufacturing test† TEST5 Test pin for TI manufacturing test† † For unit-in-place test POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 timing parameter symbology Some timing parameter symbols have been created in accordance with JEDEC Standard 100-A. To shorten the symbols, some of the signal names and other related terminology have been abbreviated as: DR DRN OSC RS SCK VDD DRVR DRVR OSCIN SRESET SBCLK VDDL, VDD Lower-case subscripts are defined as: c d h r sk su t w Cycle time Delay time Hold time Rise time Skew Setup time Transition time Pulse duration The following additional letters and phrases are defined as: L H V Z Falling edge Rising edge 34 Low High Valid High impedance No longer high No longer low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 PARAMETER MEASUREMENT INFORMATION Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels are compatible with TTL devices. Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level at which the signal is said to be high is 2 V, as shown below. The rise and fall times are not specified but are assumed to be those of standard TTL devices, which typically are 1.5 ns. 2 V (high) 0.8 V (low) test measurement The test-load circuit shown in Figure 6 represents the programmable load of the tester pin electronics that are used to verify timing parameters of TI380C30A output signals. IOL Test Point Test Point TTL Output Under Test VLOAD 50 pF XMT+ 50 pF 330Ω Test Point XMT– 50 pF IOH (a) TTL-OUTPUT TEST LOAD (b) XMT+ and XMT– TEST LOAD IEQB EQ+ VLOAD VEQW 330Ω 180 Ω EQ– (c) Iref TEST CIRCUIT Where: VLOAD (d) EQUALIZER TEST CIRCUIT = 1.5 V, typical dc-level verification or 0.7 V, typical timing verification Figure 6. Test and Load Circuits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 switching characteristics over recommended range of supply voltage (unless otherwise noted) transmitter drive characteristics (see Figures 6 and 7) PARAMETER VPP(XMT) TEST CONDITIONS MIN VDD = 4.75 V VDD = 5.25 V 8.2 XMT+/XMT peak-to-peak XMT+/XMT– peak to peak voltage (see Note 16) MAX 10.3 UNIT V NOTE 16: VPP(XMT) is determined by: VOH(XMT+) + VOH(XMT–) – VOL(XMT+) – VOL(XMT–) transmitter switching characteristics (see Figures 6 and 7) PARAMETER TEST CONDITIONS MIN MAX XMT+/XMT skew (see Note 17) XMT+/XMT– tsk(DRV) = – 1 ns tsk(DRV) = + 1 ns –3 3 –3 3 XMT+/XMT asymmetry (see Note 18) XMT+/XMT– tsk(DRV) = –1 ns tsk(DRV) = + 1 ns –2 2 –2 2 NOTES: 17. XMT+/XMT– skew is determined by: td(XMT + H) – td(XMT – L) or td(XMT + L) – td(XMT – H) 18. XMT+/XMT– asymmetry is determined by: t d(XMT)L) )t 2 d(XMT *H) * td(XMT)H) ) td(XMT*L) 2 DRVR+ 2.4 V 1.5 V 0.45 V DRVR– 2.4 V 1.5 V 0.45 V tsk(DRV) tsk(DRV) XMT+ td(XMT+H) td(XMT+L) VOH(XMT–) V50(XMT–) VOL(XMT–) XMT– td(XMT– H) td(XMT– L) Figure 7. Transmitter 36 VOH(XMT+) V50(XMT+) VOL(XMT+) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 clock and data switching characteristics over recommended range of supply voltage, tc(XT1) = 125 ns (see Figure 8) PARAMETER TEST CONDITIONS MIN TYP UNIT Cycle time of clock applied to XT1 Pulse duration, OSC32 high 10 ns tw(OSC32L) Pulse duration, OSC32 low 12 ns tw(PXTALL) (PXTALL) Pulse duration, duration PXTAL low tw(PXTALH) (PXTALH) Pulse duration, duration PXTAL high tw(RCLKL) (RCLKL) Pulse duration, duration RCLK low tw(RCLKH) (RCLKH) Pulse duration duration, RCLK high tsu(RCVR) th(RCVR) 125 MAX tc(XT1) tw(OSC32H) 16-Mbit/s mode 12 4-Mbit/s mode 46 16-Mbit/s mode 10 4-Mbit/s mode 46 ns ns ns 16-Mbit/s mode 12 4-Mbit/s mode 46 16-Mbit/s mode 10 4-Mbit/s mode 46 Setup time, RCVR valid to RCLK rising edge 16-Mbit/s mode 18 ns Hold time, RCVR valid after RCLK rising edge 16-Mbit/s mode 1 ns ns ns tw(PXTALH) tw(PXTALL) 2V PXTAL 0.8 V tw(OSC32H) tw(OSC32L) 2V OSC32 0.8 V tw(RCLKH) tw(RCLKL) 2V RCLK 0.8 V tsu(RCVR) ÌÌÌÌÌ ÌÌÌÌÌ RCVR ÌÌÌÌÌ ÌÌÌÌÌ th(RCVR) 2V 0.8 V Figure 8. PXTAL, OSC32, RCLK, and RCVR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 timing for power-up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, and SRESET (see Figure 9) NO. 100† tr(VDD) Rise time, 1.2 V to minimum VDD-high level 1 ms 101†‡ td(VDDH-SCKV) Delay time, minimum VDD-high level to first valid SBCLK no longer high 1 ms 102†‡ td(VDDH-OSCV) tc(SCK) Delay time, minimum VDD-high level to first valid OSCIN high tw(SCKH) tw(SCKL) tt(SCK) tc(OSC) Transition time, SBCLK 103 104 105 106† 107 108 109 MIN tw(OSCH) ( ) tw(OSCL) ( ) NOM MAX UNIT 1 ms 30.3 500 ns Pulse duration, SBCLK high 13 500 ns Pulse duration, SBCLK low 13 500 ns 2 ns Cycle time, SBCLK (see Note 19) Cycle time, OSCIN (see Note 20) 1/OSCIN Pulse duration, OSCIN high (see Note 21) Pulse duration, OSCIN low (see Note 21) OSCIN = 64 MHz 5.5 OSCIN = 48 MHz 8 OSCIN = 32 MHz 8 OSCIN = 64 MHz 5.5 OSCIN = 48 MHz 8 OSCIN = 32 MHz 8 110† 111† tt(OSC) td(OSCV-CKV) Transition time, OSCIN 117† 118† th(VDDH-RSL) tw(RSH) Hold time, SRESET low after VDD reaches minimum high level 119† 288† 289† Delay time, OSCIN valid to MBCLK1 and MBCLK2 valid ns ns ns 3 ns 1 ms 5 ms Pulse duration, SRESET high 14 µs tw(RSL) tsu(RST) Pulse duration, SRESET low 14 µs Setup time, DMA size to SRESET high (Intel mode only) 10 ns th(RST) Hold time, DMA size from SRESET high (Intel mode only) 10 ns tM CLKDIV = H 2tc(OSC) CLKDIV = L tc(OSC) One-eighth of a local-memory cycle ns † This specification is provided as an aid to board design. ‡ If parameter 101 or 102 cannot be met, parameter 117 must be extended by the larger difference: real value of parameter 101 or 102 minus the max value listed. NOTES: 19. SBCLK can be any value between 2 MHz and 33 MHz. This data sheet describes the system interface (SIF) timing parameters for the cases of SBCLK at 25 MHz and 33 MHz. 20. The value of OSCIN can be 64 MHz ±1%, 32 MHz ± 1%, or 48 MHz ± 1%. If OSCIN is used to generate PXTAL, the OSCIN tolerance must be ±0.01%. 21. This maintains a ± 5% duty-cycle crystal, provided that OSCIN meets the recommended operating conditions for VIH and VIL. 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 ÏÏÏ ÏÏÏ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌ ÌÌÌÌÌ 100 VDD Minimum VDD-High Level 103 106 101 SBCLK 102 OSCIN MBCLK1 MBCLK2 SRESET 106 104 105 107 108 110 109 110 111 117 118 288 119 289 S8/SHALT ÏÏ ÏÏ ÏÏ NOTE A: To represent the information in one illustration, nonactual phase and timebase characteristics are shown. Refer to specified parameters for precise information. Figure 9. Power-Up, System Clocks, SYNCIN, and SRESET POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 memory-bus timing tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). local-memory clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and address (see Figures 10 and 11) NO. MIN 1 Period of MBCLK1 and MBCLK2 2 Pulse duration, MBCLK1/MBCLK2 high 3 Pulse duration, MBCLK1/MBCLK2 low 4 Hold time, MBCLK2 low after MBCLK1 high 5 Hold time, MBCLK1 high after MBCLK2 high 6 Hold time, MBCLK2 high after MBCLK1 low 7 Hold time, MBCLK1 low after MBCLK2 low 8 Setup time, address/enable on MAX0, MAX2, and MROMEN before MBCLK1 no longer high 9 Setup time, row address on MADL0–MADL7, MAXPH, and MAXPL before MBCLK1 no longer high 10 Setup time, address on MADH0–MADH7 before MBCLK1 no longer high 11 Setup time, MAL high before MBCLK1 no longer high 12 Setup time, address on MAX0, MAX2, and MROMEN before MBCLK1 no longer low 13 Setup time, column address on MADL0–MADL7, MAXPH, and MAXPL before MBCLK1 no longer low 14 Setup time, status on MADH0–MADH7 before MBCLK1 no longer low 120 Setup time, NMI valid before MBCLK1 low 121 Hold time, NMI valid after MBCLK1 low 126 Delay time, MBCLK1 no longer low to MRESET valid 129 Hold time, column address/status after MBCLK1 no longer low Reference 4 Periods 2tM–9 tM–9 ns tM–9 tM–9 ns tM–9 tM–9 ns tM–14 tM–14 ns 13 ns 0.5tM–9 0.5tM–9 ns 0.5tM–9 30 ns 0 ns tM–7 12 Periods UNIT ns 0 8 Periods MAX 4tM 2tM–9 16 Periods ns ns ns ns ns ns ns 20 ns ns 20 Periods OSCIN (when CLKDIV = 1) OSCIN (when CLKDIV = 0) OSCOUT MBCLK1† MBCLK2† † MBCLK1 and MBCLK2 have no timing relationship to OSCOUT. MBCLK1 and MBCLK2 can start on any OSCIN rising edge, depending on when the memory cycle starts execution. Figure 10. Clock Waveforms After Clock Stabilization 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 M8 M1 M2 M3 M4 M5 M6 M7 M8 M1 1 tM 3 MBCLK1 4 2 6 1 5 7 8 12 3 MBCLK2 MAX0 MAX2 MROMEN ADD/EN Address 9 MAXPH MAXPL MADL0–MADL7 Row 13 Col 10 MADH0–MADH7 Address 2 14 Status 11 129 MAL 120 ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ NMI ÌÌÌÌÌÌ ÌÌÌÌÌÌ 121 Valid MRESET 126 Valid Figure 11. Memory Bus – Local-Memory Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and Address POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 41 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 memory-bus timing (continued) tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). clocks, MRAS, MCAS, and MAL to address (see Figure 12) NO. 42 MIN 15 Setup time, row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer high 16 Hold time, row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high 17 Delay time, MRAS no longer high to MRAS no longer high in the next memory cycle 18 19 MAX UNIT 1.5tM–11.5 tM–6.5 ns ns Pulse duration, MRAS low 8tM 4.5tM–5 Pulse duration, MRAS high 3.5tM–5 ns 20 Setup time, column address (MADL0–MADL7, MAXPH, and MAXPL) and status (MADH0–MADH7) before MCAS no longer high 0.5tM–9 ns 21 Hold time, column address (MADL0–MADL7, MAXPH, and MAXPL) and status (MADH0–MADH7) after MCAS low tM–5 ns 22 Hold time, column address (MADL0–MADL7, MAXPH, and MAXPL) and status (MADH0–MADH7) after MRAS no longer high 2.5tM–6.5 ns 23 Pulse duration, MCAS low ns 24 Pulse duration, MCAS high, refresh cycle follows read or write cycle 3tM–9 2tM–9 25 Hold time, row address on MAXL0–MAXL7, MAXPH, and MAXPL after MAL low ns 26 Setup time, row address on MAXL0–MAXL7, MAXPH, and MAXPL before MAL no longer high 1.5tM–9 tM–9 27 Pulse duration, MAL high ns 28 Setup time, address/enable on MAX0, MAX2, and MROMEN before MAL no longer high tM–9 tM–9 29 Hold time, address/enable of MAX0, MAX2, and MROMEN after MAL low Setup time, address on MADH0–MADH7 before MAL no longer high 1.5tM–9 tM–9 ns 30 31 Hold time, address on MADH0–MADH7 after MAL low 1.5tM–9 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns ns ns ns TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 MAXPH MAXPL MADL0–MADL7 Row Column Row 16 Column 26 17 22 18 15 19 MRAS 21 23 20 24 MCAS 25 27 MAL 29 28 MAX0 MAX2 MROMEN ADD/EN Address 21 30 MADH0–MADH7 20 Address 31 Status Address Status 22 Figure 12. Memory Bus – Clocks, MRAS, MCAS, and MAL to Address POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 memory-bus timing (continued) tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). memory-bus read cycle (see Figure 13) NO. MIN MAX UNIT 32 Access time, address/enable valid on MAX0, MAX2, and MROMEN to valid data/parity 6tM–23 ns 33 Access time, address valid on MAXPH, MAXPL, MADH0–MADH7, and MADL0–MADL7 to valid data/parity 6tM–23 ns 35 Access time, MRAS low to valid data/parity 4.5tM–21.5 ns 36 Hold time, valid data/parity after MRAS no longer low 37 Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7 and MADL0–MADL7 after MRAS high (see Note 22) 38 Access time, MCAS low to valid data/parity 39 Hold time, valid data/parity after MCAS no longer low 40 Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7, and MADL0–MADL7 after MCAS high (see Note 22) 41 Delay time, MCAS no longer high to MOE low 42 Setup time, address/status in the high-impedance state on MAXPH, MAXPL, MADL0–MADL7, and MADH0–MADH7 before MOE no longer high 43 Access time, MOE low to valid data/parity 44 Pulse duration, MOE low 45 Delay time, MCAS low to MOE no longer low 46 Hold time, valid data/parity in after MOE no longer low 47 Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7, and MADL0–MADL7 after MOE high (see Note 22) 48 0 ns 2tM–10.5 ns 3tM–23 ns 0 ns 2tM–13 ns tM+13 0 ns ns 2tM–20 ns 2tM–9 3tM–9 ns 0 ns 2tM–15 ns Setup time, address/status in the high-impedance state on MAXPH, MAXPL, MADL0–MADL7, and MADH0–MADH7, before MBEN no longer high 0 ns 48a Setup time, address/status in the high-impedance state on MAXPH, MAXPL, MADL0–MADL7, and MADH0–MADH7 and before MBIAEN no longer high 0 ns 49 Access time, MBEN low to valid data/parity 49a Access time, MBIAEN low to valid data/parity 50 Pulse duration, MBEN low 50a Pulse duration, MBIAEN low 51 ns 2tM–25 2tM–25 ns ns 2tM–9 2tM–9 ns Hold time, valid data/parity after MBEN no longer low 0 ns 51a Hold time, valid data/parity after MBIAEN no longer low 0 ns 52 Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7, and MADL0–MADL7 after MBEN high (see Note 22) 2tM–15 ns 52a Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7, and MADL0–MADL7 after MBIAEN high 2tM–15 ns 53 Hold time, MDDIR high after MBEN high, read follows write cycle Setup time, MDDIR low before MBEN no longer high 1.5tM–12 3tM–5 ns 54 55 Hold time, MDDIR low after MBEN high, write follows read cycle ns ns 3tM–12 ns NOTE 22: The data/parity that exists on the address lines most likely will reach the high-impedance state some time later than the rising edge of MRAS, MCAS, MOE, or MBEN (between MIN and MAX of timing parameter 36) and will be a function of the memory being read. The MIN time given represents the time from the rising edge of MRAS, MCAS, MOE, or MBEN to the beginning of the next address, and does not represent the actual high-impedance period on the address bus. 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 MAX0 MAX2 MROMEN Address/ Enable Address Data/Parity MAXPH, MAXPL MADH0–MADH7 MADL0–MADL7 Address/ Status Address Address 33 36 37 35 MRAS 39 38 40 MCAS 43 45 46 47 41 42 44 MOE 48a 49a 51a 50a 52a MBIAEN 49 51 48 50 52 MBEN 53 55 54 MDDIR Figure 13. Memory-Bus Read Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 memory-bus timing (continued) tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). memory-bus write cycle (see Figure 14) NO. 46 MIN 58 Setup time, MW low before MRAS no longer low 60 Setup time, MW low before MCAS no longer low 63 Setup time, valid data/parity before MW no longer high 64 Pulse duration, MW low 65 Hold time, data/parity out valid after MW high 66 Setup time, address valid on MAX0, MAX2, and MROMEN before MW no longer low 67 Hold time, MRAS low to MW no longer low 69 Hold time, MCAS low to MW no longer low 70 Setup time, MBEN low before MW no longer high 71 Hold time, MBEN low after MW high 72 73 MAX UNIT tM 1.5tM–6.5 ns 5.1 ns 2.5tM–9 0.5tM–10.5 7tM–11.5 ns 5.5tM–9 4tM–11.5 1.5tM–13.5 ns 0.5tM–6.5 2tM–9 ns Setup time, MDDIR high before MBEN no longer high Hold time, MDDIR high after MBEN high 1.5tM–12 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns ns ns ns TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 MAX0 MAX2 MROMEN MAXPH, MAXPL MADH0–MADH7 MADL0–MADL7 Address/ Enable Address Address ADD/STS Data/Parity Out MRAS 58 MCAS 60 63 64 65 MW 69 67 66 70 71 MBEN 72 73 MDDIR Figure 14. Memory-Bus Write Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 memory-bus timing (continued) tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). DRAM-refresh cycle (see Figure 15) NO. MIN 15 Setup time, row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer high 16 Hold time, row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high 18 Pulse duration, MRAS low 19 Pulse duration, MRAS high 73a Setup time, MCAS low before MRAS no longer high 73b Hold time, MCAS low after MRAS low 73c Setup time, MREF high before MCAS no longer high 73d Hold time, MREF high after MCAS high Refresh Address MADL0–MADL7 MAX UNIT 1.5tM–11.5 tM–6.5 ns 4.5tM–5 3.5tM–5 ns 1.5tM–11.5 4.5tM–6.5 ns 14 ns tM–9 ns ns ns ns Address 16 15 18 19 MRAS 73a 73b MCAS 73c 73d MREF Figure 15. Memory-Bus DRAM-Refresh Cycle XMATCH and XFAIL timing (see Figure 16) tM is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or 20.83 ns minimum for a 6-MHz local bus). NO. MIN 127 Delay time, status bit 7 high to XMATCH and XFAIL recognized 128 Pulse duration, duration XMATCH or XFAIL high MADH7 6-MHz local bus 30 Status Bit 7 127 128 XMATCH XFAIL Figure 16. XMATCH and XFAIL 48 4-MHz local bus 7tM 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT ns ns TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 token-ring timing ring interface (see Figure 17) NO. MIN 153 Period of RCLK (see Note 23) 154L Pulse duration, duration RCLK low 154H Pulse duration duration, RCLK high 4 Mbit/s 46 16 Mbit/s nominal: 15.625 ns 15 4 Mbit/s nominal: 62.5 ns 35 16 Mbit/s nominal: 15.625 ns Setup time, RCVR valid before rising edge (1.8 V) of RCLK at 16 Mbit/s Hold time, RCVR valid after rising edge (1.8 V) of RCLK at 16 Mbit/s 158L Pulse duration, duration ring-baud ring baud clock low 158H Pulse duration, duration ring-baud ring baud clock high 165 ns ns 8 10 ns 1 ns 4 Mbit/s 40 16 Mbit/s 8 4 Mbit/s 40 16 Mbit/s 8 4 Mbit/s Period of OSCOUT and PXTAL (see Note 23) ns ns 125 16 Mbit/s (for PXTALIN only) ns 31.25 ±0.01 Tolerance of PXTAL input frequency (see Note 23) UNIT ns 31.25 4 Mbit/s nominal: 62.5 ns 156 MAX 125 16 Mbit/s 155 TYP % NOTE 23: This parameter is not tested but is required by the IEEE Std 802.5 specification. 153 154H RCLK 154L RCVR ÌÌÌÌÌÌ ÌÌÌÌÌÌ 156 155 Valid 158H ÌÌÌÌÌ ÌÌÌÌÌ 158L 165 OSCOUT PXTAL 1.5 V Figure 17. Ring Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 transmitter timing (see Figure 18) NO. MIN Delay time, DRVR+ rising edge (1.8 V) to DRVR– falling edge (1 V) or DRVR+ falling edge (1 V) to DRVR– rising edge (1.8 V) MAX ±2 UNIT 159 tsk(DR) 160 td(DR)H† td(DR)L† Delay time, RCLK (or PXTAL) falling edge (1 V) to DRVR+ rising edge (1.8 V) See Note 24 ns Delay time, RCLK (or PXTAL) falling edge (1 V) to DRVR+ falling edge (1 V) See Note 24 ns td(DRN)H† t(DRN)L† Delay time, RCLK (or PXTAL) falling edge (1 V) to DRVR– falling edge (1 V) See Note 24 ns Delay time, RCLK (or PXTAL) falling edge (1 V) to DRVR– rising edge (1.8 V) See Note 24 ns 161 162 163 164 DRVR+/DRVR– asymmetry t d(DR)L )t 2 d(DRN)H – t d(DR)H )t ±1.5 d(DRN)L 2 ns ns † When in active-monitor mode, the clock source is PXTAL; otherwise, the clock source is either RCLK or PXTAL. NOTE 24: This parameter is not tested to a minimum or a maximum, but is measured and used as a component required for parameter 164. RCLK or PXTAL 2.6 V 1.5 V 0.6 V DRVR+ 2.4 V 1.5 V 0.6 V 160 161 159 162 159 163 2.4 V 1.5 V 0.6 V DRVR– Figure 18. Skew and Asymmetry From RCLK or PXTAL to DRVR+ and DRVR– 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 80x8x DIO timing 80x8x DIO read cycle (see Figure 19) 25-MHZ OPERATION NO NO. MIN MAX 33-MHZ OPERATION MIN MAX UNIT 255 Delay time, SRDY low to either SCS or SRD high 15 15 ns 256 Pulse duration, SRAS high 30 30 ns 259† Hold time, SAD in the high-impedance state after SRD low (see Note 25) 0 0 ns 260 Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SRDY low 0 0 ns 261† Delay time, SRD or SCS high to SAD in the high-impedance state (see Note 25) 261a Hold time, output data valid after SRD or SCS high (see Note 25) 0 0 ns 264 Setup time, SRSX, SRS0–SRS2, SCS, and SBHE valid to SRAS no longer high (see Note 26) 30 30 ns 265 Hold time, SRSX, SRS0–SRS2, SCS, and SBHE valid after SRAS low 10 10 ns 266a Setup time, SRAS high to SRD no longer high (see Note 26) 15 15 ns 267‡ Setup time, SRSX, SRS0–SRS2 valid before SRD no longer high (see Note 25) 15 15 ns 268 Hold time, SRSX, SRS0–SRS2 valid after SRD no longer low (see Note 26) 0 0 ns 272a Setup time, SRD, SWR, and SIACK high from previous cycle to SRD no longer high tc(SCK) tc(SCK) ns 273a Hold time, SRD, SWR, and SIACK high after SRD high tc(SCK) tc(SCK) ns 275 Delay time, SRD and SWR, or SCS high to SRDY high (see Note 25) 0 25 0 25 ns 279† Delay time, SRD and SWR, high to SRDY in the high-impedance state 0 tc(SCK) 0 tc(SCK) ns 282a Delay time, SDBEN low to SRDY low in a read cycle 0 tc(SCK)/2+4 0 tc(SCK)/2+4 ns 282R Delay time, SRD low to SDBEN low (see TMS380 Second Generation Token-Ring User’s Guide, literature number SPWU005, subsection 3.4.1.1.1), provided previous cycle completed 0 tc(SCK)+3 0 tc(SCK)+3 ns 283R Delay time, SRD high to SDBEN high (see Note 25) 0 tc(SCK)/2+4 0 tc(SCK)/2+4 ns 35 35 ns 286 Pulse duration, SRD high between DIO accesses (see Note 25) tc(SCK) tc(SCK) ns † This specification is provided as an aid to board design. ‡ It is the later of SRD and SWR or SCS low that indicates the start of the cycle. NOTES: 25. The inactive chip-select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip-select in interrupt-acknowledge cycles. 26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 SCS, SRSX SRS0–SRS2 SBHE Valid† Valid 264 265 268 SRAS 256 266a 267 SIACK 272a 273a 272a 273a SWR SRD 273a 272a 286 High SDDIR 279 283R 282R SDBEN 275 282a 255 SRDY‡ Hi-Z Hi-Z 261 259 SADH0–SADH7 SADL0–SADL7 SPH, SPL§ 261a 260 Hi-Z Output Data Valid Hi-Z † In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must meet parameter 266a; SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. ‡ When the TMS380C30A begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input of the data buffers. § In 8-bit 80x8x-mode DIO reads, the SADH0–SADH7 contain don’t-care data. Figure 19. 80x8x DIO Read Cycle 52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 80x8x DIO write cycle (see Figure 20) 25-MHZ OPERATION NO NO. MIN MAX 33-MHZ OPERATION MIN MAX UNIT 255 Delay time, SRDY low to either SCS or SWR high 15 15 ns 256 Pulse duration, SRAS high 30 30 ns 262 Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SCS or SWR no longer low 15 15 ns 263 Hold time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SCS or SWR high 15 15 ns 264 Setup time, SRSX, SRS0–SRS2, SCS, and SBHE to SRAS no longer high (see Note 26) 30 30 ns 265 Hold time, SRSX, SRS0–SRS2, SCS, and SBHE after SRAS low 10 10 ns 266a Setup time, SRAS high to SWR no longer high (see Note 25) 15 15 ns 267† Setup time, SRSX, SRS0–SRS2 before SWR no longer high (see Note 25) 15 15 ns 268 Hold time, SRSX, SRS0–SRS2 valid after SWR no longer low (see Note 26) 0 0 ns 272a Setup time, SRD, SWR, and SIACK high from previous cycle to SWR no longer high tc(SCK) tc(SCK) ns 273a Hold time, SRD, SWR, and SIACK high after SWR high tc(SCK) tc(SCK) ns 276 Delay time, SRDY low in the first DIO access to the SIF register to SRDY low in the immediately following access to the SIF (see TMS380 Second-Generation Token-Ring User’s Guide, literature number SPWU005, subsection 3.4.1.1.1) 4000 4000 ns 275 279‡ Delay time, SWR or SCS high to SRDY high (see Note 25) 0 25 0 25 ns Delay time, SWR high to SRDY in the high-impedance state 0 0 ns 280 Delay time, SWR low to SDDIR low (see Note 25) 0 tc(SCK) tc(SCK)/2+4 282b Delay time, SDBEN low to SRDY low ((see TMS380 Second Generation Token-Ring User’s Guide, literature number SPWU005, subsection 3.4.1.1.1) 0 tc(SCK) tc(SCK)/2+4 If SIF register is ready (no waiting required) 0 tc(SCK)/2+4 0 tc(SCK)/2+4 If SIF register is not ready (waiting required) 0 4000 0 4000 tc(SCK)/2+4 tc(SCK)/2+4 0 tc(SCK)/2+4 tc(SCK)/2+4 ns ns 282W Delay time, SDDIR low to SDBEN low 0 283W Delay time, SCS or SWR high to SDBEN no longer low 0 0 ns ns 286 Pulse duration, SWR high between DIO accesses (see Note 25) tc(SCK) tc(SCK) ns † It is the later of SRD and SWR or SCS low that indicates the start of the cycle.123456789101112131415161718192021222324 ‡ This specification is provided as an aid to board design. NOTES: 25. The inactive chip-select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip-select in interrupt-acknowledge cycles. 26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 SCS, SRSX SRS0–SRS2 SBHE Valid 264 268 265 SRAS 256 SIACK 266a 267 272a 273a SWR 273a 286 272a SRD 272a 280 273a SDDIR 282W 283W SDBEN† 276 279 275 282b 255 SRDY Hi-Z Hi-Z 262 SADH0–SADH7 SADL0–SADL7 SPH SPL‡ Hi-Z 263 Data Hi-Z † When the TMS380C30A begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input of the data buffers. ‡ In 8-bit 80x8x-mode DIO writes, the value placed on SADH0–SADH7 is a don’t care. Figure 20. 80x8x DIO Write Cycle 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 80x8x interrupt-acknowledge-cycle timing first SIACK pulse (see Figure 21) 25-MHZ OPERATION NO. MIN 286 Pulse duration, SIACK high between DIO accesses (see Note 25) 287 Pulse duration, SIACK low on first pulse of two pulses tc(SCK) tc(SCK) 33-MHZ OPERATION MAX MIN UNIT MAX tc(SCK) tc(SCK) ns ns NOTE 25. The inactive chip-select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip-select in interrupt-acknowledge cycles. SRD SWR SCS 287 286 First SIACK Second Figure 21. 80x8x Interrupt-Acknowledge Cycle – First SIACK Pulse second SIACK pulse (see Figure 22) 25-MHZ OPERATION NO NO. MIN MAX 33-MHZ OPERATION MIN MAX UNIT 255 Delay time, SRDY low to SCS high 15 15 ns 259† Hold time, SAD in the high-impedance state after SIACK low (see Note 25) 0 0 ns 260 Setup time, output data valid before SRDY low 0 0 ns 261† Delay time, SIACK high to SAD in the high-impedance state (see Note 25) 261a Hold time, output data valid after SIACK high (see Note 25) 272a Setup time, inactive data strobe high to SIACK no longer high 273a 275 276 Delay time, SRDY low in the first DIO access to the SIF register to SRDY low in the immediately following access to the SIF 279† Delay time, SIACK high to SRDY in the high-impedance state 0 282a Delay time, SDBEN low to SRDY low in a read cycle 282R Delay time, SIACK low to SDBEN low (see TMS380 Second Generation Token-Ring User’s Guide, literature number SPWU005, subsection 3.4.1.1.1), provided previous cycle completed 35 35 ns 0 0 ns tc(SCK) tc(SCK) ns Hold time, inactive data strobe high after SIACK high tc(SCK) tc(SCK) Delay time, SIACK high to SRDY high (see Note 25) 0 25 0 4000 ns 25 ns 4000 ns ns ns 0 0 tc(SCK) tc(SCK)/2+4 0 tc(SCK) tc(SCK)/2+4 0 tc(SCK)+3 0 tc(SCK)+3 ns 283R Delay time, SIACK high to SDBEN high (see Note 25) 0 tc(SCK)/2+4 0 tc(SCK)/2+4 ns † This specification is provided as an aid to board design. NOTE 25. The inactive chip-select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip-select in interrupt-acknowledge cycles. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 SCS SRSX SRS0–SRS2, SBHE Only SCS needs to be inactive. All others are don’t care. SIACK 272a 273a SWR 273a 272a SRD 273a 272a High SDDIR 282R 279 283R SDBEN 275 276 282a SRDY† 255 Hi-Z Hi-Z 261 259 SADH0–SADH7 SADL0–SADL7 SPH SPL‡ Hi-Z 260 261a Output Data Valid † SRDY is an active-low bus-ready signal. It must be asserted before data output. ‡ In 8-bit 80x8x-mode DIO writes, the value placed on SADH0–SADH7 is a don’t care. Figure 22. 80x8x Interrupt-Acknowledge Cycle – Second SIACK Pulse 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Hi-Z TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 80x8x-mode bus-arbitration timing 80x8x-mode bus arbitration – SIF takes control (see Figure 23) NO. 25-MHZ OPERATION 33-MHZ OPERATION MIN MIN MAX UNIT MAX 208a Setup time, asynchronous signal SBBSY and SHLDA before SBCLK no longer high to assure recognition on that cycle 10 10 ns 208b Hold time, asynchronous signal SBBSY and SHLDA after SBCLK low to assure recognition on that cycle 10 10 ns 212 Delay time, SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid 224a Delay time, SBCLK low in cycle I2 to SOWN low 224c Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read 28 230 Delay time, SBCLK high to SHRQ high 241 Delay time, SBCLK high in TX cycle to SRD and SWR high, bus acquisition 241a Hold time, SRD and SWR in the high-impedance state after SOWN low, bus acquisition 20 0 User Master 20 ns 15 ns 23 ns 20 15 ns 25 25 ns 20 tc(SCK)–15 0 tc(SCK)–15 Bus Exchange ns SIF Master SBCLK SIF Inputs 208a SBBSY SHLDA 230 208b SHRQ 241 SRD SWR 212 241a SBHE SIF Outputs SADH0– SADH7 SADL0– SADL7 SPH SPL 212 Address Valid 224c Write SDDIR Read 224a SOWN† † While the system interface DMA controls are active (that is, SOWN is asserted), the SCS input is disabled. Figure 23. 80x8x-Mode Bus Arbitration – SIF Takes Control POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 80x8x-mode DMA timing 80x8x-mode DMA read cycle (see Figure 24) NO. 25-MHZ OPERATION 33-MHZ OPERATION MIN MIN MAX UNIT MAX 205 Setup time, SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid before SBCLK in T3 cycle no longer high 10 10 ns 206 Hold time, SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SBCLK low in T4 cycle if parameters 207a and 207b not met 10 10 ns 207a Hold time, SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SRD high 0 0 ns 207b Hold time, SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SDBEN no longer low 0 0 ns 208a Setup time, asynchronous signal SRDY before SBCLK no longer high to assure recognition on this cycle 10 10 ns 208b Hold time, asynchronous signal SRDY after SBCLK low to assure recognition on this cycle 10 10 ns 212 Delay time, SBCLK low to address valid 20 20 ns 214 Delay time, SBCLK low in T1 cycle to SADH0–SADH7, SADL0–SADL7, SPH, and SPL in the high-impedance state 20 15 ns 216 Delay time, SBCLK high to SALE or SXAL high 20 20 ns 216a Hold time, SALE or SXAL low after SRD high 0 217 Delay time, SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 0 218 Hold time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SALE or SXAL low 5 223R Delay time, SBCLK low in T4 cycle to SRD high (see Note 27) 0 225R Delay time, SBCLK low in T4 cycle to SDBEN high 0 25 0 ns 25 5 16 0 16 ns ns 11 ns 11 ns Delay time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL in the high-impedance state to SRD low 0 Delay time, SBCLK low in T2 cycle to SRD low 0 229 Hold time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL in the high-impedance state after SBCLK low in T1 cycle 0 0 ns 231 Pulse duration, SRD low 2tc(SCK)–25 2tc(SCK)–25 ns 233 Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SALE, SXAL no longer high 10 10 ns 226 227R 237R 247 Delay time, SBCLK high in the T2 cyle to SDBEN low 0 15 16 Setup time, data valid before SRDY low if parameter 208a not met 0 NOTE 27: While the system-interface DMA controls are active (that is, SOWN is asserted), SCS is disabled. 58 POST OFFICE BOX 655303 0 • DALLAS, TEXAS 75265 ns 15 11 0 ns ns ns TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 T4 TX T1 T2 TWAIT V T3 T4 T1 SBCLK Hi-Z SRAS ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌ ÌÌÌ 212 SBHE† SWR Valid High 227R 223R SRD‡ 216 217 217 218 226 SXAL 216 216a SALE 233 212 SADH0–SADH7 SADL0–SADL7 SPH SPL§ 212 218 214 233 205 Address Extended Address 207a 206 Data 218 208a 247¶ 229 Address 207b SRDY 237R 208b 225R SDBEN† SDDIR Low † In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA. ‡ Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS. § In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 221; that is, held after T4 high. ¶ If parameter 208A is not met, then valid data must be present before SRDY goes low. Figure 24. 80x8x-Mode DMA Read Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 80x8x-mode DMA write cycle (see Figure 25) NO. 33-MHZ OPERATION MIN MIN MAX UNIT MAX 208a Setup time, asynchronous signal SRDY before SBCLK no longer high to assure recognition on that cycle 10 10 ns 208b Hold time, asynchronous signal SRDY after SBCLK low to assure recognition on that cycle 10 10 ns 212 Delay time, SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid 20 216 Delay time, SBCLK high to SALE or SXAL high 216a Hold time, SALE or SXAL low after SWR high 0 217 Delay time, SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 0 218 Hold time, address valid after SALE, SXAL low 5 219 Delay time, SBCLK low in T2 cycle to output data and parity valid 221 Hold time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SWR high 223W Delay time, SBCLK low to SWR high 225W Delay time, SBCLK high in T4 cycle to SDBEN high 225WH 227W 233 237W 60 25-MHZ OPERATION 20 Hold time, SDBEN low after SWR, SUDS, and SLDS high Delay time, SBCLK low in T2 cycle to SWR low 0 16 20 ns 25 0 tc(SCK)/2–7 0 ns ns 29 ns ns 11 ns 11 ns ns 15 10 16 • DALLAS, TEXAS 75265 ns tc(SCK)–12 10 Delay time, SBCLK high in T1 cycle to SDBEN low 20 5 16 Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SALE, SXAL no longer high POST OFFICE BOX 655303 25 tc(SCK)–12 tc(SCK)/2–7 0 ns 0 29 0 20 ns ns 11 ns TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 TX† T4 SBCLK T1 T2 TWAIT V ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ T3 T4 T1 ÌÌÌ ÌÌÌ 212 SBHE‡ SRD Valid High 227W 223W SWR 216 217 217 SXAL 216 216a SALE 233 212 SADH0–SADH7 SADL0–SADL7 SPH SPL§ 219 218 212 218 233 221 Address Extended Address Output Data 208a SRDY 237W 208b 225WH 225W SDBEN High SDDIR † In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer and whenever the increment of the DMA address register carries beyond the least significant 16 bits. ‡ In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA. § In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 221; that is, held after T4 high. Figure 25. 80x8x-Mode DMA Write Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 61 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 80x8x-mode bus arbitration – SIF returns control (see Figure 26) 25-MHZ OPERATION NO. MIN 220 Delay time, SBCLK low in I1 cycle to SADH0–SADH7, SADL0–SADL7, SPL, SPH, SRD, and SWR in the high-impedance state 223b Delay time, SBCLK low in I1 cycle to SBHE in the high-impedance state 224b Delay time, SBCLK low in cycle I2 to SOWN high 224d Delay time, SBCLK low in cycle I2 to SDDIR high 230 Delay time, SBCLK high in cycle I1 to SHRQ low 240 Setup time, SRD, SWR, and SBHE in the high-impedance state before SOWN no longer low ns 45 ns 15 ns 27 22 ns 20 15 ns 45 20 0 I1 UNIT MAX 35 0 0 Bus Exchange T4 MIN 35 0 SIF Master T3 MAX 33-MHZ OPERATION ns User Master I2 (T1) (T2) SBCLK SHLDA 230 SHRQ† 220 SRD SWR Hi-Z 240 223b SBHE SIF Outputs SADH0– SADH7 SADL0– SADL7 SPH SPL Hi-Z SIF 220 240 Hi-Z SIF 224d Write SDDIR Read 224b SOWN‡ † In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls. ‡ While the system-interface DMA controls are active (that is, SOWN is asserted), SCS is disabled. Figure 26. 80x8x-Mode Bus Arbitration – SIF Returns Control 62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 80x8x-mode bus-release timing (see Figure 27) 25-MHZ OPERATION NO. MIN MAX 33-MHZ OPERATION MIN UNIT MAX 208a Setup time, asynchronous input SBRLS low before SBCLK no longer high to assure recognition 10 10 ns 208b Hold time, asynchronous input SBRLS low after SBCLK low to assure recognition 10 10 ns 208c Hold time, SBRLS low after SOWN high 0 0 ns T(W or 2) T3 T4 T1 T2 SBCLK† 208a 208b SBRLS‡ 208c SOWN † Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid, the signal is also specified to hold its previous value (including high impedance) until the start of that SBCLK transition. ‡ The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus, when it detects the assertion of SBRLS, it completes any internally started DMA cycle and relinquishes control of the bus. If no DMA transfer has started internally, the system interface releases the bus before starting another. Figure 27. 80x8x-Mode Bus Release POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 68xxx DIO timing 68xxx DIO read cycle (see Figure 28)123456789101112131415161718192021222324 25-MHZ OPERATION NO NO. MIN 255 Delay time, SDTACK low to either SCS, SUDS, or SLDS high 259† MAX 33-MHZ OPERATION MIN MAX UNIT 15 15 ns Hold time, SAD in the high-impedance state after SUDS or SLDS low (see Note 25) 0 0 ns 260 Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SDTACK low 0 0 ns 261† Delay time, SCS, SUDS, or SLDS high to SADH0–SADH7, SADL0–SADL7, SPH, and SPL in the high-impedance state (see Note 25) 261a Hold time, output data valid after SUDS or SLDS no longer low (see Note 25) 267 35 35 ns 0 0 ns Setup time, register address before SUDS or SLDS no longer high (see Note 25) 15 15 ns 268 Hold time, register address valid after SUDS or SLDS no longer low (see Note 26) 0 0 ns 272 Setup time, SRNW before SUDS or SLDS no longer high (see Note 25) 12 12 ns 273 Hold time, SRNW after SUDS or SLDS high 0 0 ns 273a Hold time, SIACK high after SUDS or SLDS high tc(SCK) tc(SCK) ns 275 Delay time, SCS, SUDS, or SLDS high to SDTACK high (see Note 25) 276 Delay time, SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately following access to the SIF 279† Delay time, SUDS or SLDS high to SDTACK in the high-impedance state 0 tc(SCK) 282a Delay time, SDBEN low to SDTACK low 0 282R Delay time, SUDS or SLDS low to SDBEN low (see TMS380 Second Generation Token-Ring User’s Guide, literature number SPWU005, subsection 3.4.1.1.1), provided the previous cycle completed 283R Delay time, SUDS or SLDS high to SDBEN high (see Note 25) 286 Pulse duration, SUDS or SLDS high between DIO accesses (see Note 26) 0 25 0 25 ns 4000 ns 0 tc(SCK) ns tc(SCK)/2+4 0 tc(SCK)/2+4 ns 0 tc(SCK)+3 0 tc(SCK)+3 ns 0 tc(SCK)/2+4 0 tc(SCK)/2+4 ns 4000 tc(SCK) tc(SCK) ns † This specification is provided as an aid to board design. NOTES: 25. The inactive chip-select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip-select in interrupt-acknowledge cycles. 26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 SCS SRSX SRS0 SRS1 Valid 267 268 SIACK 273a SRNW 272 273 SUDS SLDS 286 High SDDIR 279 283R 282R SDBEN 275 276 282a SDTACK† 255 Hi-Z Hi-Z 261 SADH0–SADH7 SADL0–SADL7 SPH SPL 259 260 Hi-Z 261a Output Data Valid Hi-Z † SDTACK is an active-low bus-ready signal. It must be asserted before data output. Figure 28. 68xxx DIO Read Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 68xxx DIO write cycle (see Figure 29)123456789101112131415161718192021222324 25-MHZ OPERATION NO NO. MIN MAX 33-MHZ OPERATION MIN MAX UNIT 255 Delay time, SDTACK low to either SCS, SUDS, or SLDS high 15 15 ns 262 Setup time, write data valid before SUDS or SLDS no longer low 15 15 ns 263 Hold time, write data valid after SUDS or SLDS high 15 15 ns 267† Setup time, register address before SUDS or SLDS no longer high (see Note 25) 15 15 ns 268 Hold time, register address valid after SUDS or SLDS no longer low (see Note 26) 0 0 ns 272 Setup time, SRNW before SUDS or SLDS no longer high (see Note 25) 12 12 ns 272a Setup time, inactive SUDS or SLDS high to active data strobe no longer high tc(SCK) tc(SCK) ns 273 Hold time, SRNW after SUDS or SLDS high 0 0 ns 273a Hold time, inactive SUDS or SLDS high after active data strobe high tc(SCK) tc(SCK) ns 275 Delay time, SCS, SUDS, or SLDS high to SDTACK high (see Note 25) 276 Delay time, SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately following access to the SIF 279‡ Delay time, SUDS or SLDS high to SDTACK in the high-impedance state 0 tc(SCK) 280 Delay time, SUDS or SLDS low to SDDIR low (see Note 25) 282b Delay time, SDBEN low to SDTACK low ((see TMS380 Second Generation Token-Ring User’s Guide, literaure number SPWU005, subsection 3.4.1.1.1) 0 0 25 ns 4000 ns 0 tc(SCK) ns ns 4000 0 tc(SCK)/2+4 0 tc(SCK)/2+4 If SIF register is ready (no waiting required) 0 tc(SCK)/2+4 0 tc(SCK)/2+4 If SIF register is not ready (waiting required) 0 4000 0 4000 tc(SCK)/2+4 tc(SCK)/2+4 0 tc(SCK)/2+4 tc(SCK)/2+4 ns 282W Delay time, SDDIR low to SDBEN low 0 283W Delay time, SUDS or SLDS high to SDBEN no longer low 0 286 25 Pulse duration, SUDS or SLDS high between DIO accesses (see Note 25) tc(SCK) 0 tc(SCK) ns ns ns † It is the later of SRD and SWR or SCS low that indicates the start of the cycle. ‡ This specification is provided as an aid to board design. NOTES: 25. The inactive chip-select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip-select in interrupt-acknowledge cycles. 26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are irrelevant and parameter 268 must be met. 66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 SCS SRSX SRS0 SRS1 Valid 267 268 SIACK 273a 272 273 SRNW 286 272a SUDS SLDS† 273a 280 SDDIR 282W 283W SDBEN‡ 279 276 SDTACK§ 275 255 Hi-Z Hi-Z 263 SADH0–SADH7 SADL0–SADL7 SPH SPL 282b Hi-Z 262 Data Hi-Z † For 68xxx mode, skew between SLDS and SUDS must not exceed 10 ns. Provided this limitation is observed, all events referenced to a data strobe edge use the later occurring edge. Events defined by two data strobes, edges, such as parameter 286, are measured between latest and earlier edges. ‡ When the TMS380C25 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input of the data buffers. § SDTACK is an active-low bus ready signal. It must be asserted before data output. Figure 29. 68xxx DIO Write Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 67 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 68xxx interrupt-acknowledge-cycle timing (see Figure 30) 25-MHZ OPERATION NO NO. MIN MAX 33-MHZ OPERATION MIN MAX UNIT 255 Delay time, SDTACK low to either SCS or SUDS, or SIACK high 15 15 ns 259† Hold time, SAD in the high-impedance state after SIACK no longer high (see Note 25) 0 0 ns 260 Setup time, output data valid before SDTACK no longer high 0 0 ns 261† Delay time, SIACK high to SAD in the high-impedance state (see Note 25) 261a Hold time, output data valid after SCS or SIACK no longer low (see Note 25) 267‡ Setup time, register address before SIACK no longer high (see Note 25) 272a Setup time, inactive high SIACK to active data strobe no longer high 273a Hold time, inactive SRNW high after active data strobe high 275 Delay time, SCS or SRNW high to SDTACK high (see Note 25) 0 25 0 25 ns 276 Delay time, SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately following access to the SIF 0 4000 0 4000 ns 279† Delay time, SIACK high to SDTACK in the high-impedance state 0 0 0 tc(SCK) tc(SCK)/2+4 ns Delay time, SDBEN low to SDTACK low in a read cycle tc(SCK) tc(SCK)/2+4 0 282a 282R Delay time, SIACK low to SDBEN low (see TMS380 Second Generation Token-Ring User’s Guide, literature number SPWU005, subsection 3.4.1.1.1), provided the previous cycle completed 0 tc(SCK)+3 0 tc(SCK)+3 ns 283R Delay time, SIACK high to SDBEN high (see Note 25) 0 tc(SCK)/2+4 0 tc(SCK)/2+4 ns 286 35 ns 0 0 ns 15 15 ns tc(SCK) tc(SCK) tc(SCK) tc(SCK) ns POST OFFICE BOX 655303 tc(SCK) • DALLAS, TEXAS 75265 tc(SCK) ns ns ns † This specification is provided as an aid to board design. ‡ It is the later of SRD and SRD or SCS low that indicates the start of the cycle. NOTE 25. The inactive chip-select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip-select in interrupt-acknowledge cycles. 68 Pulse duration, SIACK high between DIO accesses (see Note 25) 35 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 SCS SRSX SRS0 SRS1 SBHE Only SCS needs to be Inactive. All others are don’t care. 267 SIACK 272a 286 SRNW 273a SLDS 286 High SDDIR 279 282R 283R SDBEN 275 276 282a SDTACK† 255 Hi-Z Hi-Z 261 SADH0–SADH7 SADL0–SADL7 SPH SPL‡ 259 Hi-Z 260 261a Output Data Valid Hi-Z † SDTACK is an active-low bus ready signal. It must be asserted before data output. ‡ Internal logic drives SDTACK high and verifies that it has reached a valid-high level before making it a 3-state signal. Figure 30. 68xxx Interrupt-Acknowledge Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 69 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 68xxx-mode bus-arbitration timing 68xxx-mode bus arbitration – SIF takes control (see Figure 31) NO. 25-MHZ OPERATION 33-MHZ OPERATION MIN MIN UNIT MAX 208a Setup time, asynchronous input SBGR before SBCLK no longer high to assure recognition on this cycle 10 10 ns 208b Hold time, asynchronous input SBGR after SBCLK low to assure recognition on this cycle 10 10 ns 212 Delay time, SBCLK low to address valid 0 20 0 20 ns 224a Delay time, SBCLK low in cycle I2 to SOWN low (see Note 28) 0 20 0 15 ns 224c Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read 28 23 ns 230 Delay time, SBCLK high to either SHRQ low or SBRQ high 20 15 ns 241 Delay time, SBCLK high in TX cycle to SUDS and SLDS high 25 25 ns 241a Hold time, SUDS, SLDS, SRNW, and SAS in the high-impedance state after SOWN low, bus aquisition tc(SCK–15) NOTE 28. Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS. 70 MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tc(SCK–15) ns TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 User Master Bus Exchange SIF Master SBCLK 208b 208a SIF Inputs SBGR SBERR SDTACK SBBSY 230 230 SBRQ† 208a SAS SLDS SUDS 208b 241 Input Output 241 Read SRNW SIF Outputs SADH0– SADH7 SADL0– SADL7 SPH SPL Write 212 SIF Hi-Z 224c Write SDDIR Read 224a 241a SOWN‡ † In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system-bus transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system-bus transfer it controls. ‡ While the system-interface DMA controls are active (that is, SOWN is asserted), the SCS input is disabled. Figure 31. 68xxx-Mode Bus Arbitration – SIF Takes Control POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 71 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 68xxx-mode DMA timing 68xxx-mode DMA read cycle (see Figure 32) NO NO. 25-MHZ OPERATION 33-MHZ OPERATION MIN MIN MAX MAX UNIT 205 Setup time, input data valid before SBCLK in T3 cycle no longer high 10 10 ns 206 Hold time, input data valid after SBCLK low in T4 cycle if parameters 207a and 207b not met 10 10 ns 207a Hold time, input data valid after data strobe no longer low 0 0 ns 207b Hold time, input data valid after SDBEN no longer low 0 0 ns 208a Setup time, asynchronous input SDTACK before SBCLK no longer high to assure recognition on this cycle 10 10 ns 208b Hold time, asynchronous input SDTACK after SBCLK low to assure recognition on this cycle 10 10 ns 209 Pulse duration, SAS, SUDS, and SLDS high tc(SCK)+ tw(SCKL)–18 tc(SCK)+ tw(SCKL)–18 ns 210 Delay time, SBCLK high in T2 cycle to SUDS and SLDS active 16 11 ns 212 Delay time, SBCLK low to address valid 20 20 ns 214 Delay time, SBCLK low in T2 cycle to SAD high impedance 20 15 ns 20 ns 216 Delay time, SBCLK high to SALE or SXAL high 216a Hold time, SALE or SXAL low after SUDS and SAS high 0 20 217 Delay time, SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 0 218 Hold time, address valid after SALE, SXAL low 5 222 Delay time, SBCLK high to SAS low 25 223R 225R Delay time, SBCLK low in T4 cycle to SDBEN high 229 Hold time, SAD in the high-impedance state after SBCLK low in T4 cycle 0 16 0 233 Setup time, address valid before SALE or SXAL no longer high Setup time, address valid before SAS no longer high 237R Delay time, SBCLK high in the T2 cycle to SDBEN low 25 0 ns ns 15 ns 11 ns 11 ns 0 ns 10 10 ns tw(SCKL)–15 tw(SCKL)–15 ns 16 Setup time, data valid before SDTACK low if parameter 208a not met 0 NOTE 27: While the system-interface DMA controls are active (that is, SOWN is asserted), SCS is disabled. POST OFFICE BOX 655303 ns 5 16 233a 72 0 20 Delay time, SBCLK low in T4 cycle to SUDS, SLDS, and SAS high (see Note 27) 247 0 • DALLAS, TEXAS 75265 11 0 ns ns TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 T4 TX T1 S1 TWAIT V T2 S2 S3 S4 T3 S5 T4 S6 T1 S7 SBCLK 222 SAS† 210 209 223R SUDS SLDS 218 217 209 High SRNW 216 217 SXAL 216 218 216a SALE 212 SADL0–SADH7 SADH0–SADL7 SPH SPL 233 212 233a 233 229 214 205 Address Extended Address 206 207a Data In 247‡ Hi-Z 207b 208a SDTACK§¶ 208b SDDIR Low 237R 225R SDBEN† † On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data may be removed when either the read strobe or SDBEN becomes inactive. ‡ If parameter 208a is not met, then valid data must be present before SDTACK goes low. § Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS. ¶ All VSS pins should be routed to minimize inductance to system ground. Figure 32. 68xxx-Mode DMA Read Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 73 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 68xxx-mode DMA write cycle (see Figure 33) NO NO. 33-MHZ OPERATION MIN MIN MAX MAX UNIT 208a Setup time, asynchronous input SDTACK before SBCLK no longer high to assure recognition on this cycle 10 10 ns 208b Hold time, asynchronous input SDTACK after SBCLK low to assure recognition on this cycle 10 10 ns 209 Pulse duration, SAS, SUDS, and SLDS high tc(SCK)+ tw(SCKL)–18 tc(SCK)+ tw(SCKL)–18 ns 211 Delay time, SBCLK high in T2 cycle to SUDS and SLDS active 211a Delay time, output data valid to SUDS and SLDS no longer high 212 Delay time, SBCLK low to address valid 20 20 ns 216 Delay time, SBCLK high to SALE or SXAL high 20 20 ns 216a Hold time, SALE or SXAL low after SUDS and SAS high 0 217 Delay time, SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 0 218 Hold time, address valid after SALE, SXAL low 5 219 Delay time, SBCLK low in T2 cycle to output data and parity valid 221 Hold time, output data, parity valid after SUDS and SLDS high 222 Delay time, SBCLK high to SAS low 25 tw(SCKL)–15 25 tw(SCKL)–15 25 0 Delay time, SBCLK low to SUDS, SLDS, and SAS high 225W Delay time, SBCLK high in T4 cycle to SDBEN high tc(SCK)–12 225WH Hold time, SDBEN low after SUDS and SLDS high 0 233 Setup time, address valid before SALE or SXAL no longer high Setup time, address valid before SAS no longer high 237W Delay time, SBCLK high in T1 cycle to SDBEN low POST OFFICE BOX 655303 25 tc(SCK)–12 16 0 ns ns 29 16 233a ns 5 29 ns ns 0 20 223W 74 25-MHZ OPERATION ns ns 15 ns 11 ns 11 ns tc(SCK)/2–7 10 tc(SCK)/2–7 10 ns tw(SCKL)–15 tw(SCKL)–15 ns 16 • DALLAS, TEXAS 75265 ns 11 ns TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 T4 TX † T1 T2 TWAIT V T3 T4 T1 SBCLK 222 211 223W SAS 233a 209 SUDS SLDS 216 217 218 211 a SRNW Low 217 218 SXAL 216 216a SALE 212 233 SADL0–SADH7 SADH0–SADL7 SPL SPH 212 233 221 219 Address Extended Address Output Data 208b SDTACK‡§ 208b 225W SDDIR Low 237W 225WH SDBEN † In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer and whenever the increment of the DMA address register carries beyond the least significant 16 bits. ‡ On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data can be removed when either the read strobe or SDBEN becomes inactive. § All VSS terminals should be routed to minimize inductance to system ground. Figure 33. 68xxx-Mode DMA Write Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 75 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 68xxx-mode bus arbitration – SIF returns control (see Figure 34) 25-MHZ OPERATION NO. MIN 220 Delay time, SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS, and SLDS in the high-impedance state, bus release 223b Delay time, SBCLK low in I1 cycle to SBHE/SRNW in the high-impedance state 224b Delay time, SBCLK low in cycle I2 to SOWN high 224d Delay time, SBCLK low in cycle I2 to SDDIR high 230 Delay time, SBCLK high to either SHRQ low or SBRQ high 240 Setup from, SUDS, SLDS, SRNW, and SAS control signals in the high-impedance state before SOWN no longer low MAX MIN UNIT MAX 35 35 ns 45 ns 15 ns 27 22 ns 20 15 ns 45 0 SIF Master T2 33-MHZ OPERATION 20 0 0 0 ns Bus Exchange T3 T4 User I1 I2 T1 SBCLK SIF Inputs SBGR SDTACK 230 SBRQ† 220 240 SAS SUDS SLDS 240 223b Read SRNW Hi-Z Write SIF Outputs SADH0–SADH7 SADL0–SADL7 SPH SPL 220 Hi-Z SIF 224d Write SDDIR Read 224b SOWN † In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system-bus transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system-bus transfer it controls. Figure 34. 68xxx-Mode Bus Arbitration – SIF Returns Control 76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 68xxx-mode bus-release and error timing (see Figures 35, 36, and 37) 25-MHZ OPERATION NO. MIN MAX 33-MHZ OPERATION MIN UNIT MAX 208a Setup time, asynchronous input before SBCLK no longer high to assure recognition 10 10 ns 208b Hold time, asynchronous input SBRLS, SOWN, or SBERR after SBCLK low to assure recognition 10 10 ns 208c Hold time, SBRLS low after SOWN high 0 0 ns 236 Setup time, SBERR low before SDTACK no longer high if parameter 208a not met 30 30 ns T(W or 2) T3 T4 T1 T2 SBCLK† 208a 208b SBRLS‡ 208b SOWN 208a 208c SBERR§ 236 SDTACK † Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid, the signal is also specified to hold its previous value (including high impedance) until the start of that SBCLK transition. ‡ The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus, when it detects the assertion of SBRLS, it completes any internally started DMA cycle and relinquishes control of the bus. If no DMA transfer has started internally, the system interface releases the bus before starting another. § If SBERR is asserted when the system interface controls the system bus, the current bus transfer is completed, regardless of the value of SDTACK. If the BERETRY register is nonzero, the cycle is retried. If the BERETRY register is zero, the system interface then releases control of the system bus. The system interface ignores the assertion of SBERR if it is not performing a DMA-bus cycle on the system bus. When SBERR is properly asserted and BERETRY is zero, however, the system interface releases the bus upon completion of the current bus transfer and halts all further DMA on the system side. The error is synchronized to the local bus and DMA stops on the local sides. The value of the SDMAADR, SDMADDRX, and SDMALEN registers in the system interface are not defined after a system-bus error. Figure 35. 68xxx-Mode Bus Release and Error POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 77 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 T1 T(W or 2) SBCLK T3 T4 TH T1 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ SDTACK SBERR SHALT Figure 36. 68xxx-Mode Bus Halt and Retry, Normal Completion With Delayed Start† † Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement can vary from waveforms shown. T1 T2 T3 T4 THB THE T1 SBCLK SDTACK ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ SBERR ÌÌÌÌÌÌ ÌÌÌÌÌÌ SHALT SOWN Figure 37. 68xxx-Mode Bus Halt and Retry, Rerun Cycle With Delayed Start† † Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement can vary from waveforms shown. 78 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE SPWS034 – MARCH 1998 MECHANICAL DATA PGF (S-PQFP-G176) PLASTIC QUAD FLATPACK 132 89 88 133 0,27 0,17 0,08 M 0,50 0,13 NOM 176 45 1 44 Gage Plane 21,50 SQ 24,20 SQ 23,80 26,20 SQ 25,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040134 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 79 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TI380C30APGF OBSOLETE LQFP PGF Pins Package Eco Plan (2) Qty 176 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated