TI TLC320AD56

TLC320AD56C
Data Manual
Sigma-Delta Analog Interface Circuit
SLAS101A
September 1996
Printed on Recycled Paper
IMPORTANT NOTICE
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Copyright  1996, Texas Instruments Incorporated
Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Definitions and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Register Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–1
1–1
1–2
1–3
1–4
1–5
1–6
1–7
2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1
Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2
ADC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3
DAC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5
Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6
Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.7
Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.8
Sigma-Delta DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.9
Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.10 Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.11 FIR Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Reset and Power-Down Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Master Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Data Out (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4
Data In (DIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
Hardware Program Terminal (FC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
Frame-Sync Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7
Multiplexed Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.9
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1
2–1
2–1
2–1
2–1
2–1
2–1
2–2
2–2
2–2
2–2
2–2
2–2
2–2
2–2
2–3
2–3
2–3
2–3
2–4
2–4
2–4
2–4
3
Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Primary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Secondary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Conversion Rate vs Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Phone Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1
3–1
3–3
3–6
3–6
4
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Absolute Maximum Ratings Over Operating
Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1
Recommended Operating Conditions, DVDD = 5 V, AVDD = 5 V . . . . .
4.2.2
Recommended Operating Conditions, DVDD = 3 V, AVDD = 5 V . . . . .
4–1
4–1
4–1
4–1
4–1
iii
Contents (Continued)
Section
4.3
5
Title
Page
Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, DVDD = 5 V, AVDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1
Digital Inputs and Outputs, MCLK = 4.096 MHz,
fs = 8 kHz, Outputs Not Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2
Digital Inputs and Outputs, MCLK = 4.096 MHz,
fs = 8 kHz, Outputs Not Loaded, DVDD = 3 V . . . . . . . . . . . . . . . . . . . . .
4.3.3
ADC Path Filter, MCLK = 4.096 MHz, fs = 8 kHz . . . . . . . . . . . . . . . . . .
4.3.4
ADC Dynamic Performance, MCLK = 4.096 MHz, fs = 8 kHz . . . . . . . .
4.3.5
ADC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.6
DAC Path Filter, MCLK = 8.192 MHz, fs = 8 kHz . . . . . . . . . . . . . . . . . .
4.3.7
DAC Dynamic Performance, DVDD = 5 V or 3 V . . . . . . . . . . . . . . . . . . .
4.3.8
DAC Channel, DVDD = 5 V or 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.9
Power Supplies, No Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.10 Power-Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.11 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2
4–2
4–2
4–2
4–2
4–4
4–4
4–5
4–6
4–6
4–7
4–7
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Appendix A Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
Appendix B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
iv
List of Illustrations
Figure
1–1.
1–2.
1–3.
2–1.
2–2.
3–1.
3–2.
3–3.
3–4.
3–5.
3–6.
4–1.
4–2.
4–3.
4–4.
5–1.
5–2.
Title
Page
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Power-Down Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Analog-Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary Serial Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware and Software Ways to Make a Secondary Request . . . . . . . . . . . . . . . . . . .
Hardware FC Secondary Request
(Phone Mode Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software FC Secondary Request (Phone Mode Disabled) . . . . . . . . . . . . . . . . . . . . . .
Phone Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary DIN Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Decimation Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Decimation Filter Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Interpolation Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DAC Interpolation Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Schematic For Single-Ended Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Schematic For Differential Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2
1–3
1–4
2–4
2–5
3–2
3–3
3–4
3–5
3–6
3–6
4–8
4–8
4–9
4–9
5–1
5–2
List of Tables
Table
Title
Page
3–1. Secondary Request Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3–2. Least Significant Bit Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
3–3. Secondary Communication Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
v
vi
1 Introduction
The TLC320AD56C provides high resolution low-speed signal conversion from digital-to-analog (D/A) and
from analog-to-digital (A/D) using oversampling sigma-delta technology. This device consists of two serial
synchronous conversion paths (one for each data direction) and includes an interpolation filter before the
digital-to-analog converter (DAC) and a decimation filter after the analog-digital-converter (ADC) (see
Figure 1–1). Other overhead functions provide on-chip timing and control. The sigma-delta architecture
produces high resolution A/D and D/A conversion at low system speeds and low cost.
The options and the circuit configurations of this device can be programmed through the serial interface.
The options include reset, power-down, communications protocol, serial clock rate, and test mode as
outlined in Appendix A. The TLC320AD56C is characterized for operation from 0°C to 70°C.
1.1
Features
The TLC320AD56C includes the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single 5-V power supply voltage or 5 V analog and 3 V digital supply voltages
Power dissipation (PD) of 150 mW maximum in the operating mode
Power-down mode to 2.5 mW typical
General-purpose 16-bit signal processing
2’s-complement data format
Typical dynamic range of 85 dB for the DAC and 87 dB for the ADC
Minimum 79-dB total signal-to-(noise + distortion) for the ADC
Minimum 80-dB total signal-to-(noise + distortion) for the DAC
Differential architecture throughout the device
Internal reference voltage (Vref)
Internal 64X oversampling
Serial port interface
Phone-mode output control
System test mode, digital loopback test mode
Capable of supporting all V.34 sample rates by varying MCLK frequency
Supports business audio applications
Variable conversion rate selected as MCLK/512
1–1
1.2
Functional Block Diagram
MONOUT
INP
Decimation Filter
INM
MUX
SigmaDelta
ADC
SINC
Filter
FIR
Filter
DOUT (2’scomplement)
Buffer
AUXP
Digital
Loopback
FILT
AUXM
Vref
Vref
IGAIN
OUTP
OUTM
SigmaDelta
DAC
÷8
DIN (2’scomplement)
Interpolation Filter
Buffer
fclk
FLAG 0
FLAG 1
ALT DATA
FC
FS
I/O
Control
MCLK
÷4
Figure 1–1. Functional Block Diagram
1–2
SCLK
Terminal Assignments
NC
FILT
VCOM(ADC)
IGAIN
MONOUT
AUXP
AUXM
FN PACKAGE
(TOP VIEW)
4
3 2 1 28 27 26
OUTP
OUTM
5
6
24
VCOM(DAC)
7
23
PWRDWN
RESET
DVDD
DIN
8
22
9
21
10
20
25
11
19
12 13 14 15 16 17 18
INM
INP
AVDD
VSS (SUB)
AVSS
DVSS
ALT DATA
DOUT
FS
SCLK
MCLK
FC
FLAG 0
FLAG 1
1.3
NC – No internal connection
Figure 1–2. Terminal Assignments
1–3
IGAIN
NC
NC
NC
NC
MONOUT
AUXP
AUXM
NC
NC
FILT
VCOM(ADC)
PT PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
OUTP
OUTM
NC
1
36
2
35
3
34
VCOM(DAC)
4
33
NC
PWRDWN
RESET
NC
DVDD
DIN
NC
DOUT
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
INM
INP
NC
AVDD
NC
NC
VSS(SUB)
NC
AVSS
NC
DVSS
ALT DATA
FS
NC
NC
SCLK
MCLK
NC
NC
NC
FC
NC
FLAG0
FLAG1
13 14 15 16 17 18 19 20 21 22 23 24
NC – No internal connection
Figure 1–3. Terminal Assignments
1.4
Ordering Information
PACKAGE
1–4
TA
CHIP CARRIER
(FN)
0°C to 70°C
TLC320AD56CFN
QUAD FLAT PACK
(PT)
TLC320AD56CPT
1.5
Terminal Functions
TERMINALS
NAME
NUMBER
I/O
DESCRIPTION
PT
FN
ALT DATA
25
19
I
Signals on this terminal are routed to DOUT during secondary communication
if phone mode is enabled.
AUXM
38
26
I
Inverting input to auxiliary analog input. AUXM requires an external RC antialias
filter.
AUXP
39
27
I
Noninverting input to auxiliary analog input. Requires an external RC antialias
filter.
AVDD
33
23
I
Analog ADC path supply (5 V only)
DIN
10
11
I
Data input. DIN receives the DAC input data and command information from the
DSP and is synchronized to SCLK.
DOUT
12
12
O
Data output. DOUT transmits the ADC output bits and is synchronized to SCLK.
This terminal is at high-Z when FS is not activated.
DVDD
9
10
I
Digital power supply (5 V or 3 V)
DVSS
26
20
I
Digital ground
FC
21
16
I
Function code. FC is sampled and latched on the rising edge of FS for the primary
serial communication. Refer to the Serial Communications section for more
details.
FLAG 0
23
17
O
Output flag 0. During phone mode, FLAG 0 contains the value set in Control 2
register.
FLAG 1
24
18
O
Output flag 1. During phone mode, FLAG 1 contains the value set in Control 2
register.
FILT
47
3
O
Bandgap filter. FILT is provided for decoupling of the bandgap reference, and
provides 2.5 V to which the analog inputs or outputs can be referenced. The
optimal capacitor value is 0.1 µF (ceramic). This voltage node should be loaded
only with a high-impedance dc load.
FS
13
13
O
Frame sync. When FS goes low, the serial communication port is activated. In
all serial transmission modes, FS is held low during bit transmission. Refer to
section 3 Serial Communications for detailed description.
INM
36
25
I
Inverting input to analog modulator. INM requires an external RC antialias filter.
INP
35
24
I
Noninverting input to analog modulator. INP requires an external RC antialias
filter.
IGAIN
45
1
O
Current gain reference scaling. IGAIN is provided for decoupling of the current
gain reference and provides a 1.35-V reference. The optimal load is a
27-K resistor.
MCLK
17
15
I
Master clock. The master clock derives the internal clocks of the sigma-delta
analog interface circuit.
MONOUT
40
28
O
Monitor output. MONOUT allows for monitoring of the analog input and is a
high-impedance output. The gain or mute is selected using Control 2 register.
O
Inverting current output of the DAC. OUTM is functionally identical with and
complementary to OUTP. OUTM and OUTP current outputs can be loaded with
5 kΩ differentially or single-ended. This signal can also be used alone for
single-ended operation.
OUTM
2
6
NOTE 1: All digital inputs and outputs are TTL-compatible, unless otherwise noted for DVDD = 5 V.
1–5
1.5
Terminal Functions (Continued)
TERMINALS
NAME
NUMBER
I/O
DESCRIPTION
Noninverting current output of the DAC. OUTM and OUTP current outputs can
be loaded with 5 kΩ differentially or single ended. This signal can also be used
alone for single-ended operation.
PT
FN
OUTP
1
5
O
PWRDWN
6
8
I
Power down. When this terminal is pulled low, the device goes into a power-down
mode; the serial interface is disabled and most of the high-speed clocks are
disabled. However, all the register values are sustained and the device resumes
full power operation without reinitialization when this terminal is pulled high
again. PWRDWN resets the counters only and preserves the programmed
register contents. See subsection 2.21. Reset and Power-Down Functions.
RESET
7
9
I
Reset. The reset function is provided to initialize all the internal registers to their
default values. The serial port can be configured to the default state accordingly.
Refer to section 1.7 Register Functional Summary and subsection 2.2.1 Reset
and Power-Down Functions for more detailed descriptions.
SCLK
16
14
O
Shift clock. The shift clock signal is derived from MCLK and is used to clock serial
data into DIN and out of DOUT.
VSS(SUB)
VCOM(ADC)
30
22
I
Analog substrate. This terminal must be grounded.
46
2
O
Common mode filter. This terminal is provided for decoupling of the common
mode reference and provides a 2.5 V reference. The optimal capacitor value is
0.10 µF. This node should be loaded only with a high-impedance dc load.
VCOM(DAC)
4
7
O
Common mode filter. This terminal is provided for decoupling of the common
mode reference and provides a 2.5 V reference. The optimal capacitor value is
0.10 µF. This node should be loaded only with a high-impedance dc load.
28
21
I
Analog ground
AVSS
NOTE 1: All digital inputs and outputs are TTL-compatible, unless otherwise noted for DVDD = 5 V.
1.6
Definitions and Terminology
Data Transfer Interval
This is time during which data is transferred from DOUT and to DIN. This interval
is 16 shift clocks and this data transfer is initiated by the falling edge of the
frame-sync signal.
Signal Data
This refers to the input signal and all of the converted representations through the
ADC channel and return through the DAC channel to the analog output. This is
contrasted with the purely digital software control data.
Primary
Communications
Secondary
Communications
Frame Sync
1–6
This refers to the digital data transfer interval. Since the device is synchronous, the
signal data words from the ADC channel and to the DAC channel occur
simultaneously.
This refers to the digital control and configuration data transfer interval into DIN and
the register read data cycle from DOUT. The data transfer interval occurs when
requested by hardware or software.
Frame sync refers only to the falling edge of the signal that initiates the data transfer
interval. The primary frame sync starts the primary communications, and the
secondary frame sync starts the secondary communications.
Frame Sync and
Sampling Period
The time between the falling edges of successive primary frame-sync signals.
fs
The sampling frequency that is the reciprocal of the sampling period.
Frame-Sync Interval
The time period occupied by 16 shift clocks. It goes high on the sixteenth rising
edge of SCLK after the falling edge of the frame sync.
ADC Channel
This term refers to all signal processing circuits between the analog input and the
digital conversion results at DOUT.
DAC Channel
This term refers to all signal processing circuits between the digital data word
applied to DIN and the differential output analog signal available at OUTP and
OUTM.
Host
Any processing system that interfaces to DIN, DOUT, SCLK, or FS.
Dxx
Bit position in the primary data word (xx is the bit number).
DSxx
Bit position in the secondary data word (xx is the bit number).
d
The alpha character d represents valid programmed or default data in the control
register format (see section 3.2 Secondary Serial Communications) when
discussing other data bit portions of the register.
X
The alpha character X represents a do-not-care bit position within the control
register format.
FIR
Finite duration impulse response.
1.7
Register Functional Summary
There are three data and control registers that are used as follows:
Register 0
The No-Op register. The 0 address allows secondary requests without altering any other
register.
Register 1
The Control 1 register. The data in this register controls:
•
The software reset
•
The software power down
•
Selection of the normal or auxiliary analog inputs
•
Selection of the digital loopback
•
16-bit or 15-bit mode of operation
•
Selection of monitor amp output
Register 2
The Control 2 register. The data in this register:
•
Contains the output flag indicating a decimator FIR filter overflow
•
Contains Flag 0 and Flag 1 output values for use in the phone mode
•
Selects the phone mode
1–7
1–8
2
Functional Description
2.1
Device Functions
The functions of the TLC320AD56C are described in the following sections.
2.1.1
Operating Frequencies
The sampling (conversion) frequency is derived from the master clock (MCLK) input by equation 1.
MCLK
fs
Sampling (conversion) frequency
512
+
+
(1)
The inverse is the time between the falling edges of two successive primary frame synchronization signals
and is the conversion period.
2.1.2
ADC Signal Channel
To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data.
The input signal is filtered and applied to the ADC input. The ADC converts the signal into discrete output
digital words in 2s-complement format, corresponding to the analog signal value at the sampling time. These
16-bit digital words, representing sampled values of the analog input signal, are clocked out of the serial port
during the frame-sync interval, (DOUT), one word for each primary communication interval. During
secondary communications, the data previously programmed into the registers can be read out with the
appropriate register address, and the read bit set to 1. When no register read is requested, all 16 bits are
0 in the secondary word.
2.1.3
DAC Signal Channel
DIN receives the 16-bit serial data word (2’s complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog
current by the sigma-delta DAC comprised of a digital interpolation filter, and a digital 1-bit modulator. The
DACs differential outputs OUTP and OUTM are a current output-type, (which requires resistive loading 5kΩ
maximum). These outputs are then connected to the external low pass filter, as shown in the application
schematics in Figure 3–7 and Figure 3–8 to complete the signal reconstruction. This filter can be
incorporated in the data access arrangement (DAA) for modem applications.
2.1.4
Serial Interface
The digital serial interface consists of the shift clock, the frame synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame synchronization interval, the
SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.
During the secondary frame synchronization interval, the SCLK transfers the register read data from DOUT
when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 3–1.
2.1.5
Register Programming
All register programming occurs during secondary communications, and data is latched and valid on the
rising edge of the frame-sync signal. When the default value for a particular register is desired, that register
does not need to be addressed during the secondary communications. The no-op command addresses the
pseudo-register (register 0), and no register programming takes place during this communications.
2–1
DOUT is released from the high-impedance state on the falling edge of the primary or secondary frame-sync
interval. In addition, each register can be read back during DOUT secondary communications by setting the
read bit D13 to 1 in the appropriate register. When the register is in the read mode, no data can be written
to the register during this cycle. To return this register to the write mode requires a subsequent secondary
communication.
2.1.6
Sigma-Delta ADC
The sigma-delta ADC is a fourth-order sigma-delta modulator with 64 times oversampling. The ADC
provides high resolution and low noise performance using oversampling techniques.
2.1.7
Decimation Filter
The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating
with a ratio of 1:64. The output of this filter is a sixteen-bit 2’s-complement data word clocking at the sample
rate selected.
NOTE
The sample rate is determined through a relationship of MCLK/512.
2.1.8
Sigma-Delta DAC
The sigma-delta DAC is a fourth-order sigma-delta modulator with 64 times oversampling. The DAC
provides high-resolution, low-noise performance from a 1-bit converter using oversampling techniques. The
TLC320AD56C is a current-output DAC and requires a load resistor for current-to-voltage conversion (see
Figures 3–7 and 3–8).
2.1.9
Interpolation Filter
The interpolation filter resamples the digital data at a rate of 64 times the incoming sample rate. The
high-speed data output from this filter is then used in the sigma-delta DAC.
2.1.10
Digital Loopback
The digital loopback provides a means of testing the ADC/DAC channels and can be used for in-circuit
system-level tests. The loopback feeds the ADC output to the DAC input on the IC.
Digital loopback is enabled by setting the appropriate bit in Control 1 register (see Appendix A).
2.1.11
FIR Overflow Flag
The decimator FIR filter provides an overflow flag to the Control 2 register to indicate that the input to the
filter has exceeded the range of the internal filter calculations. When this bit is set in the register, it will remain
set until the register is read by the user. Reading this value will always reset the overflow flag.
2.2
Terminal Functions
The terminal functions are described in the following sections.
2.2.1
Reset and Power-Down Functions
2.2.1.1
Reset
The TLC320AD56C resets the internal counters and registers, including the programmed registers, in one
of two ways:
1.
By applying a low-going reset pulse to the reset terminal
2.
By writing to the programmable software reset bit (D07 in Control 1 register)
PWRDWN resets the counters only and preserves the programmed register contents. The PWRDWN
terminal must be kept low 20 ms after the power supplies have settled.
2–2
2.2.1.2
Conditions of Reset
The two internal reset signals used for the reset and synchronization functions are:
1.
Counter Reset – This signal resets all flip-flops and latches that are not externally programmed,
with the exception of those generating the reset pulse itself. Additionally, this
signal resets the software power-down bit. A counter reset is initiated with the
RESET terminal or RESET bit or PWRDWN terminal.
2.
Register Reset – This signal resets all flip-flops and latches that are not reset by the counter
reset, except those generating the reset pulse itself. A register reset is initiated
with the RESET terminal or RESET bit.
Both reset signals should be at least six master clock periods long, TRESET, and should release on the trailing
edge of the master clock.
2.2.1.3
Software and Hardware Power Down
Given the definitions above, the software programmed power-down condition is cleared by clearing the
software bit (Control 1 register, bit 6) to a 0 or by cycling the power to the device or bringing RESET low.
The output of the monitor amplifier maintains its midpoint voltage during hardware and software power
downs to minimize pops and clicks.
PWRDWN powers down the entire chip. Cycling the power-down terminal from high to low and back high
resets all flip-flops and latches that are not externally programmed, thereby preserving the register contents.
When PWRDWN is not used, it should be tied high.
2.2.2
Master Clock Circuit
The clock circuit generates and distributes necessary clocks throughout the device. MCLK is the external
master clock input. SCLK is derived from MCLK in order to provide clocking of the serial communications
between the device and a digital signal processor (DSP). The sample rates of the data paths are set to
MCLK/512.
2.2.3
Data Out (DOUT)
DOUT is taken from the high-impedance state by the falling edge of frame sync. The most significant data
bit then appears on DOUT.
DOUT is placed in a high-impedance state on the sixteenth rising edge of SCLK after the falling edge of
frame sync. In the primary communication, the data word is the ADC conversion result. In the secondary
communication, the data is the register read results when requested by the read/ write (R / W) bit with the
eight MSBs set to 0 (see Section 3 Serial Communications). If no register read is requested, the secondary
word is all zeroes.
2.2.4
Data In (DIN)
In the primary communication, the data word is the input digital signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function.
(see section 3 Serial Communications).
2.2.5
Hardware Program Terminal (FC)
FC provides for hardware programming requests for secondary communication. It works in conjunction with
the control bit D00 of the secondary data word. The signal on FC is latched 1/2 shift clock after the rising
edge of the next internally generated primary frame-sync interval. The FC terminal should be tied low when
not used (see Section 3.2 Secondary Serial Communication and Table 3–2).
2–3
2.2.6
Frame-Sync Function
The frame-sync signal indicates that the device is ready to send and receive data. The data transfer from
DOUT and into DIN begins on the falling edge of the frame-sync signal.
The frame sync is generated internally and goes low on the rising edge of SCLK and remains low during
the 16-bit data transfer.
2.2.7
Multiplexed Analog Input
The two differential analog inputs (INP and INM or AUXP and AUXM) are multiplexed into the sigma-delta
modulator. The performance of the AUX channel is similar to the normal input channel. A simple RC
antialiasing filter must be connected to AUXP and AUXM (also INP and INM when used).
Digital Circuitry
Power Down
Analog Circuitry
Power Down
PWRDWN
Clear
(For Control
Reg. 1, Bit 6)
Bit 6 is Programmed
Through a Secondary
Write Operation
Internal TLC320AD56C
Figure 2–1. Internal Power-Down Logic
2.2.8
Analog Input
The signal applied to the terminals INM and INP (shown in Figure 2–2) should be differential to preserve
the device specifications. A single-ended input signal should always be converted to a differential input
signal prior to being used by the TLC320AD56C (see section 5 Application Information). The signal source
driving the analog inputs (INM, INP, AUXM, AUXP) should have a low source impedance for lowest noise
performance and accuracy. To obtain maximum dynamic range, the input signal should be centered at
midsupply. A simple RC antialiasing filter must be connected to INP and INM (also AUXP and AUXM if used).
A suitable tradeoff for the cutoff frequency (fco) of the antialiasing filter is fco = 3 x fs. With this cutoff frequency,
the attenuation within the band of interest (0 – fs/2) is less than 0.1 dB.
2.2.9
Analog Output
The analog output swing across the OUTP and OUTM terminals depends on the value of the resistor used
from the IGAIN terminal to analog ground and the resistor load across the OUTP and OUTM terminals. Both
resistors can be used to set the output voltage swing and then gained to the desired value in the external
DAC output filter as shown in Figure 5–1 and Figure 5–2. With this external filter, the gain of the DAC channel
is –2.5 dB.
The resistor on the IGAIN terminal sets up the output current pumped and the resistor across OUTP and
OUTM is the load which converts the current output of the DAC to a voltage. Hence, the voltage swing across
OUTP and OUTM depends on the ratio of the load resistor to the value of the resistor from the IGAIN terminal
to analog ground. With 0 dB digital code applied to the DAC channel, the IGAIN resistor set at 27 kΩ, and
a load resistor of 5 kΩ, the output swing across OUTP and OUTM is –10.5 dB. The ratio of IGAIN resistance
to load resistance can be adjusted to get the desired voltage swing. For the best distortion performance,
it is recommended that the output swing be limited to –6 dB relative to 6 VPP.
2–4
TLC320AD56C
4V
2.5 V
INP
1V
4V
2.5 V
INM
1V
Figure 2–2. Differential Analog-Input Configuration
2–5
2–6
3 Serial Communications
DOUT, DIN, SCLK, FS, and FC are the serial communication signals. The digital output data from the ADC
is taken from DOUT. The digital input data for the DAC is applied to DIN. The synchronizing clock for the
serial communication data and the frame sync is taken from SCLK. The frame synchronization pulse that
encloses the ADC/DAC data transfer interval is taken from FS. For an audio signal data transmitted from
the ADC or to the DAC, primary serial communication is used. To read or write words that control both the
options and the circuit configurations of the device, secondary communication is used.
The purpose of the primary and secondary communications is to allow conversion data and control data to
be transferred across the same serial port. A primary transfer is always dedicated to conversion data. A
secondary transfer is used to set up and read the register values described in Appendix A. A primary transfer
occurs for every conversion period. A secondary transfer occurs only when requested. Two methods exist
for requesting a secondary command. The FC terminal can be used to request a secondary communication
by asserting it, or the least significant bit (LSB) of the DAC data within a primary transfer can request a
secondary communication. The selection of which method is enabled is provided in Control 1 register (bit
D0) as shown in Appendix A.
For all serial communications, the most significant bit (MSB) is transferred first. For a 16-bit ADC word and
a 16-bit DAC word, D15 is the MSB and D0 is the LSB. For a 15-bit DAC data word in the 16-bit primary
communication, D15 is the MSB, D1 is the LSB, and D0 is used for the embedded function control. All digital
data values are in 2s-complement format.
These logic signals are compatible with TTL-voltage levels and CMOS current levels (when VDD = 5 V dc).
These logic signals are also compatible with a 3-V supply.
3.1
Primary Serial Communication
A primary serial communication transmits and receives conversion signal data. The ADC word length is
always 16 bits. The DAC word length depends on the status of D0 in the Control 1 register. After power up
or reset, the device defaults to a 15-bit mode (not 16-bit mode). The DAC word length is 15 bits and the last
bit of the primary 16-bit serial communication word is a function control bit used to request secondary serial
communications. In 16-bit mode, all 16 bits of the primary communications word are used as data for the
DAC and the hardware terminal FC must be used to request secondary communications.
3–1
Figure 3–1 shows the timing relationship for SCLK, FS, DOUT and DIN in a primary communication. The
timing sequence for this operation is as follows:
1.
FS is brought low by the TLC320AD56C.
2.
One 16-bit word is transmitted from the ADC (DOUT) and one 16-bit word is received for the DAC
(DIN).
3.
FS is brought high by the TLC320AD56C signaling the end of the conversion.
ÎÎ
td3
MCLK
VIH
VIL
SCLK
VOH
VOL
0th
ÎÎ
ÎÎ
1st
2nd
td1
14th
15th
td2
FS
VOH
VOL
tdis
ten
D15
DOUT
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
D14
...D2
D1
D14
...D2
D1
D0
tsu
In 16-Bit Mode:
DIN
16th
D15
D0
MSB
LSB
th
tsu
In 16-Bit Mode:
DIN
D15
D14
FC
D1
...D2
MSB
LSB
th
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
Figure 3–1. Primary Serial Communication Timing
When a secondary request is made through the LSB of the DAC data word (16-bit mode), the format in
Table 3–1 is used.
Table 3–1. Secondary Request Format
D15
D14
D13
D12
D11
D10
D9
15-bit DAC
2’s-complement format
16-bit ADC
2’s-complement format
3–2
D8
D7
D6
D5
D4
D3
D2
D1
D0
control
3.2
Secondary Serial Communication
Secondary serial communication is used to read or write 16-bit words that program both the options and the
circuit configurations of the device. All register programming occurs during secondary communications. Two
primary and secondary communication cycles are required to program the two registers. When the default
value for a particular register is desired, then the user could omit addressing it during secondary
communication. The NOOP command addresses a pseudo-register, register 0, and no register
programming takes place during this secondary communication.
There are two methods for initiating secondary communications. They are 1) by asserting a high signal level
on FC, or 2) by asserting the LSB of the DIN 16-bit serial communication high while not in 16-bit mode (see
Control 1 register, bit 0).
FC
(Hardware)
Secondary
Request
(LSB of DIN)
16-Bit Mode
(Control 1 Register,
Bit 0)
Internal TLC320AD56C
Figure 3–2. Hardware and Software Ways to Make a Secondary Request
1.
Figures 3–3 and 3–4 show the two different ways FC requests secondary communication words
as well as the timing for FS, DOUT, DIN, and SCLK. The examples span two primary
communication frames. Figure 3–3 shows the use of hardware function control.
During a secondary communication, a register may be written to or read from. When writing a
value to a register, the DIN line contains the value to be written. The data returned on DOUT is
00H. When performing a read function, the DIN line may still provide data to be written to an
addressed register; however, the DOUT line contains the most recent value in the register
addressed by DIN.
In Figure 3–3, FC is clocked in and latched on the rising edge of frame sync (FS). This causes
the start of the secondary information 32 FCLKs after the start of the primary communication
frame. Read and write examples are shown for DIN and DOUT.
2.
Figure 3–4 shows the use of software function control.
The software request is typically used when the required resolution of the DAC channel is less
than 16 bits. Then the least significant bit (D0) can be used for the secondary requests as shown
in Table 3–2.
Table 3–2. Least Significant Bit Control Function
Control Bit D0
Control Bit Function
0
No operation (NOOP)
1
Secondary communication request
On the falling edge of the next FS, D15–D1 is input to DIN or D15–D0 is output to DOUT.
When a secondary communication request is made, FS goes low 32 FCLKs after the beginning of the
primary frame.
3–3
Communication Frame 1 (CF1)
FS
FC
Primary
(CF2)
Secondary
Primary
No Secondary
Request
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
8 SCLKs
DOUT
(Secondary
Read)
DOUT
(Secondary
Write)
DIN
(Secondary
Read or Write)
16 SCLKs
ADC Data
Out
ADC Data
Out
Register
Data
ADC Data
Out
All Bits 0
ÏÏÏÏ ÏÏÏÏÏÏ
ÏÏÏÏ ÏÏÏÏÏÏ
DAC Data In
Secondary
Update
ADC Data
Out
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
DAC Data In
16 SCLKs
32 FCLKs
16 SCLKs
64 FCLKs
64 FCLKs
Figure 3–3. Hardware FC Secondary Request
(Phone Mode Disabled)
In Figure 3–4, FC hardware terminal 15 is left in its unasserted state (0). FC is asserted through software
by embedding an asserted high level (1) in the LSB of the 16-bit primary word. This is possible when not
in 16-bit mode (Control 1 register, bit 2 = 0) because the user is using only 15 bits of DAC information.
3–4
Communication Frame 1 (CF1)
FS
Primary
FC
0
D15-D1
DIN
(Secondary
Read or Write)
DOUT
(Secondary
Read)
(CF2)
Secondary
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
Primary
ÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ
D15-D1
D0 = 1
Secondary
Update
DAC Data
No Secondary
Request
Software FC Bit
D0 = 0
DAC Data
See Note A
8 SCLKs
ADC Data
ADC Data
Register
Data
DOUT
(Secondary
Write)
All Bits 0
ADC Data
ADC Data
16 SCLKs
16 SCLKs
16 SCLKs
32 FCLKs
64 FCLKs
64 FCLKs
NOTE A: For a read cycle, the last 8 bits are do-not-care bits.
Figure 3–4. Software FC Secondary Request (Phone Mode Disabled)
Table 3–3 shows the secondary communications format. D13 is the read/not-write (R/W) bit.
D12–D8 are address bits. The register map is specified in the register set section in Appendix A. D7–D0
are data bits. The data bits are the new values for the specified register addressed by D12–D8.
Table 3–3. Secondary Communication Data Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
––
––
R/W
A
A
A
A
A
D
D
D
D
D
D
D
D
3–5
3.3
Conversion Rate vs Serial Port
The SCLK frequency is set by the frequency of MCLK. There is a 2-stage clock divider that sets the SCLK
frequency as MCLK/4.
3.4
Phone Mode Control
Phone mode control is provided for applications that need hardware control and monitoring of external
events. By allowing the device to drive two FLAG terminals (set through the Control 2 register), the host
(DSP) is capable of system control through the same serial port that connects to the device. Along with this
control is the capability of monitoring the value of the ALT DATA terminal during a secondary communication
cycle. One application for this function is in monitoring RING DETECT or OFFHOOK DETECT from a phone
answering system. The two FLAG terminals allow response to these incoming control signals. Figure 3–6
shows the timing associated with this operating mode.
Primary
Secondary
Primary
Secondary
Primary
FS
Register
Data
ALT DATA
DOUT
(Secondary
Read)
8 SCLKs
ALT DATA
DOUT
(Secondary
Write)
ALT DATA
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
1 SCLK MAX
DIN
Set FLAG0 = FLAG1 = 1
FLAG0,
FLAG1
Set FLAG0 = FLAG1 = 0
Figure 3–5. Phone Mode Timing
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
Do Not Care
DIN
(Secondary
Read)
8 Bits
R/W
Register Address
DIN
(Secondary
Write)
8 Bits
Data to the
Register
Figure 3–6. Secondary DIN Format
3–6
4 Specifications
4.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)†
Supply voltage range, DVDD, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output voltage range, DOUT, FS, SCLK, FLAG0, FLAG1 . . . . – 0.3 V to DVDD + 0.3 V
Output voltage range, OUTP, OUTM . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V
Input voltage range, DIN, PWRDWN, RESET, ALT DATA,
MCLK, FC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DVDD + 0.3 V
Input voltage range, INP, INM, AUXP, AUXM . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V
Case temperature for 10 seconds, TC: DW package . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
4.2
Recommended Operating Conditions
MIN
Supply voltage, AVDD
(see Note 2)
Analog signal input voltage,
VI(analog)
Resistance, IGAIN, R(IGAIN)
NOM
4.75
Differential, (INP – INM) peak,
for full scale operation
20
Load resistance, OUTP, OUTM, RL
27
5/27
R(IGAIN)
ADC or DAC conversion rate
(sample rate)
Operating free-air temperature, TA
4.2.1
8
0
UNIT
5.25
V
6
V
54
kΩ
kΩ
22.05
kHz
70
°C
Recommended Operating Conditions, DVDD = 5 V, AVDD = 5 V
MIN
Supply voltage, DVDD (see Note 2)
High-level input voltage, VIH
NOM
4.5
MAX
5.5
2
0.8
MCLK frequency (see Note 3)
UNIT
V
V
Low-level input voltage, VIL
4.2.2
MAX
4.096
V
11.29
MHz
UNIT
Recommended Operating Conditions, DVDD = 3 V, AVDD = 5 V
MIN
NOM
MAX
Supply voltage, DVDD (see Note 2)
2.7
3
3.3
High-level input voltage, VIH
1.8
Low-level input voltage, VIL
V
V
0.6
MCLK frequency (see Note 3)
4.096
11.29
NOTES: 2. Voltages at analog inputs and outputs and VDD are with respect to the VSS terminal.
3. The default state for an 8-kHz conversion rate requires a 4.096-MHz MCLK frequency.
V
MHz
4–1
4.3
Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range, DVDD = 5 V, AVDD = 5 V (Unless Otherwise Noted)
4.3.1
Digital Inputs and Outputs, MCLK = 4.096 MHz, fs = 8 kHz, Outputs Not Loaded
PARAMETER
TEST CONDITIONS
MIN
TYP
IO = 360 µA
IO = 2 mA
2.4
4.6
MAX
UNIT
VOH
VOL
High-level output voltage, DOUT
IIH
IIL
High-level input current, any digital input
Ci
Input capacitance
5
pF
Co
Output capacitance
5
pF
4.3.2
Low-level output voltage, DOUT
Low-level input current, any digital input
0.2
VIH = 5 V
VIL = 0.8 V
V
0.4
V
10
µA
10
µA
Digital Inputs and Outputs, MCLK = 4.096 MHz, fs = 8 kHz, Outputs Not Loaded,
DVDD = 3 V
PARAMETER
TEST CONDITIONS
IO = 360 µA
IO = 2 mA
MIN
TYP
MAX
High-level output voltage, DOUT
IIH
IIL
High-level input current, any digital input
Ci
Input capacitance
5
pF
Co
Output capacitance
5
pF
4.3.3
Low-level output voltage, DOUT
Low-level input current, any digital input
2
UNIT
VOH
VOL
V
VIH = 3.3 V
VIL = 0.6 V
0.4
V
10
µA
10
µA
ADC Path Filter, MCLK = 4.096 MHz, fs = 8 kHz (see Note 4)
PARAMETER
TEST CONDITIONS
0 to 300 Hz
300 Hz to 3 kHz
Filter gain relative to gain at 1020 Hz
3.3 kHz
MIN
TYP
MAX
– 0.5
0.2
– 0.35
0.2
– 0.4
0.3
3.6 kHz
–3
4 kHz
– 40
≥ 4.4 kHz
– 74
UNIT
dB
NOTE 4: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The analog input test
signal is a sine wave with 0 dB = 6 VI(PP) as the reference level for the analog input signal. The –1 dB pass
band is 0 to 3400 Hz for an 8-kHz sample rate. This pass band scales linearly with the sample rate.
4.3.4
4.3.4.1
ADC Dynamic Performance, MCLK = 4.096 MHz, fs = 8 kHz
ADC Signal-to-Noise (see Note 5)
PARAMETER
TEST CONDITIONS
VI = – 1 dB
VI = – 3 dB
Signal-to-noise ratio (SNR)
MIN
TYP
MAX
UNIT
86
80
84
VI = – 6 dB
VI = – 9 dB
76
81
73
78
VI = – 40 dB
VI = – 65 dB
42
47
17
22
dB
VAUX = – 9 dB
73
78
NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output voltages are
referred to AVDD /2.
4–2
4.3.4.2
ADC Signal-to-Distortion (see Note 5)
PARAMETER
TEST CONDITIONS
VI = – 1 dB
VI = – 3 dB
Signal-to-total harmonic distortion (THD)
MIN
TYP
MAX
UNIT
78
74
79
VI = – 6 dB
VI = – 9 dB
77
82
80
85
VI = – 40 dB
VI = – 65 dB
65
70
42
47
dB
VAUX = – 9 dB
80
85
NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output voltages are
referred to VDD /2.
4.3.4.3
ADC Signal-to-Distortion, DVDD = 3 V (see Note 5)
PARAMETER
TEST CONDITIONS
VI = – 1 dB
VI = – 3 dB
Signal-to-total harmonic distortion (THD)
MIN
TYP
MAX
UNIT
79
90
95
VI = – 6 dB
VI = – 9 dB
92
100
94
103
VI = – 40 dB
VI = – 65 dB
68
76
42
52
dB
VAUX = – 9 dB
94
103
NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output voltages are
referred to VDD /2.
4.3.4.4
ADC Signal-to-Distortion+Noise (see Note 5)
PARAMETER
TEST CONDITIONS
VI = – 1 dB
VI = – 3 dB
Total harmonic distortion + noise (THD+N)
MIN
TYP
MAX
UNIT
77
73
78
VI = – 6 dB
VI = – 9 dB
73
78
72
77
VI = – 40 dB
VI = – 65 dB
41
46
16
21
dB
VAUX = – 9 dB
72
77
NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output voltages are
referred to VDD /2.
4–3
4.3.4.5
ADC Signal-to-Distortion+Noise, DVDD = 3 V (see Note 5)
PARAMETER
TEST CONDITIONS
VI = – 1 dB
VI = – 3 dB
Total harmonic distortion + noise (THD+N)
MIN
TYP
MAX
UNIT
78
79
84
VI = – 6 dB
VI = – 9 dB
76
81
73
78
VI = – 40 dB
VI = – 65 dB
42
47
17
22
dB
VAUX = – 9 dB
73
78
NOTE 5: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output voltages are
referred to VDD /2.
4.3.5
ADC Channel
PARAMETER
VI(PP)
TEST CONDITIONS
MIN
Peak-to-peak input voltage
CMRR
Input resistance
VI = 0 dB at 1020 kHz
5
mV
80
dB
30
TA = 25°C
Channel delay
4.3.6
dB
± 0.3
VI = – 1 dB at 1020 Hz
Idle channel noise (on-chip reference)
Ri
V
110
ADC converter offset error
Common-mode rejection ratio at INM,
INP or AUXM, AUXP
UNIT
87
Interchannel isolation
Gain error
MAX
6
Dynamic range
EG
EO(ADC)
TYP
75
µV rms
100
kΩ
17/fs
s
DAC Path Filter, MCLK = 8.192 MHz, fs = 8 kHz (see Note 6)
PARAMETER
TEST CONDITIONS
0 to 300 Hz
Filter gain relative to gain at 1020 Hz
MIN
TYP
MAX
– 0.5
0.2
300 Hz to 3 kHz
– 0.25
0.25
3.3 kHz
– 0.35
0.3
3.6 kHz
–3
4 kHz
– 40
≥ 4.4 kHz
– 74
UNIT
dB
NOTE 6: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the
digital equivalent of a sine wave (digital full scale = 0 dB). The nominal differential DAC channel output with
this input condition is 6 VI(PP). The –1 dB pass band is 0 to 3400 Hz for an 8-kHz sample rate. This pass band
scales linearly with the sample rate.
4–4
4.3.7
4.3.7.1
DAC Dynamic Performance, DVDD = 5 V or 3 V
DAC Signal-to-Noise (see Note 7)
PARAMETER
Signal to noise ratio (SNR)
Signal-to-noise
TEST CONDITIONS
MIN
TYP
VO = 0 dB
VO = – 9 dB
80
85
72
77
VO = – 40 dB
VO = – 65 dB
41
46
16
21
MAX
UNIT
dB
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at the output of a single pole RC filter with a cutoff frequency of 32 kHz. The test is conducted in
16-bit mode.
4.3.7.2
DAC Signal-to- Distortion (see Note 7)
PARAMETER
Signal to total harmonic distortion (THD)
Signal-to-total
TEST CONDITIONS
MIN
TYP
VO = 0 dB
VO = – 9 dB
86
92
90
96
VO = – 40 dB
VO = – 65 dB
60
66
40
46
MAX
UNIT
dB
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at the output of a single pole RC filter with a cutoff frequency of 32 kHz. The test is conducted in
16-bit mode.
4.3.7.3
DAC Signal-to- Distortion+Noise (see Note 7)
PARAMETER
Total harmonic distortion + noise (THD+N)
TEST CONDITIONS
MIN
TYP
VO = 0 dB
VO = – 9 dB
80
84
72
76
VO = – 40 dB
VO = – 65 dB
41
45
16
20
MAX
UNIT
dB
NOTE 7: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test
is measured at the output of a single pole RC filter with a cutoff frequency of 32 kHz. The test is conducted in
16-bit mode.
4–5
4.3.8
DAC Channel, DVDD = 5 V or 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
Dynamic range
Interchannel isolation
EG
MAX
UNIT
85
dB
108
Gain error, 0 dB
VO = 0 dB at 1020 Hz
Idle channel
broad-band noise
See Note 8
Idle channel
narrow-band noise
0 – 4 kHz,
± 0.5
70
150
µV rms
2
20
µV rms
See Note 8
Channel delay
18/fs
VOO
Output offset voltage
at OUT (differential)
DIN = zero code
VO
Analog output
voltage,
OUTP – OUTM
With internal
reference and
full-scale digital
input,
See Note 9
2
mV
RLOAD
R(IGAIN)
VPP
9.6
Differential
s
NOTES: 8. The conversion rate is 8 kHz; the out-of-band measurement is made from 4400 Hz to 3 MHz.
9. The digital input to the DAC channel at DIN is in 2’s complement format. The TLC320AD56C is a current
DAC and requires a load resistor for current-to-voltage conversion. This output voltage is across the load
resistor (see Figures 5–1 and 5–2).
4.3.9
Power Supplies, No Load (Unless Otherwise Noted)
PARAMETER
IDD ((analog)
l )
Power supply current,
current ADC
IDD (di
it l1)
(digital1)
Power supply current
current, digital
IDD (di
it l2)
(digital2)
PD
4–6
Power supplyy current,, digital,
g ,
DVDD = 3.3 V
Power dissi
dissipation
ation
TYP
MAX
Operating
TEST CONDITIONS
MIN
18
25
Power down
0.5
UNIT
mA
mA
Operating
2
Power down
3
µA
Operating
1
mA
Power down
5
mA
µA
3
Operating
100
150
Power down
2.5
5
mW
4.3.10
Power-Supply Rejection (see Note 10)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
VDD1
Supply-voltage rejection ratio, ADC channel,
DVDD
fi = 0 to 30 kHz
55
dB
VDD2
Supply-voltage rejection ratio, DAC channel,
DVDD
fi = 0 to 30 kHz
55
dB
VDD3
Supply-voltage rejection ratio, ADC channel,
AVDD
fi = 0 to 30 kHz
50
dB
Single ended,
fi = 0 to 30 kHz
50
dB
VDD4
Supply-voltage
y
g rejection
j
ratio,, DAC channel,,
AVDD
Differential,
fi = 0 to 30 kHz
55
dB
† All typical values are at 25°C.
NOTE 10: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV
peak-to-peak signal applied to the appropriate supply.
4.3.11
Timing Requirements (see Figure 3–1)
PARAMETER
TEST CONDITIONS
MIN
td1
td2
Delay time, SCLK↑ to FS↓
tsu
th
DIN setup time before SCLK low
ten
tdis
Enable time, FS↓ to DOUT valid
td3
Delay time, MCLK↓ to SCLK↑
twH
Pulse duration, MCLK high
32
twL
Pulse duration, MCLK low
20
TYP
UNIT
0
Delay time, SCLK↑ to DOUT valid
DIN hold time after SCLK high
MAX
20
20
CL = 20 pF
20
25
Disable time, FS↑ to DOUT Hi-Z
ns
20
50
4–7
0
–20
Attenuation – dB
–40
–60
–80
–100
–120
–140
–160
0
0.8
1.6
2.4
3.2
4
4.8
5.6
6.4
7.2
8
3.2
3.6
4
fI – Input Frequency – kHz
Figure 4–1. ADC Decimation Filter Response
0.6
0.4
Attenuation – dB
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
0.4
0.8
1.2
1.6
2
2.4
2.8
fI – Input Frequency – kHz
Figure 4–2. ADC Decimation Passband Ripple
4–8
0
–20
Attenuation – dB
–40
–60
–80
–100
–120
–140
–160
0
0.8
1.6
2.4
3.2
4
4.8
5.6
6.4
7.2
8
3.2
3.6
4
fI – Input Frequency – kHz
Figure 4–3. DAC Interpolation Filter Response
0.3
0.2
Attenuation – dB
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.4
0.8
1.2
1.6
2
2.4
2.8
fI – Input Frequency – kHz
Figure 4–4. DAC Interpolation Passband Ripple
4–9
4–10
5 Application Information
TLC320AD56C
+V
VI(–)
VI(+)
_
10 kΩ
INP (+)
+
0.22 µF
–V
300 pF
20 kΩ
INM (–)
10 kΩ
AGND
2.5 V
38.4 kΩ
0.1 µF
0.39 nF
+V
_
VO(+)
VCOM(ADC)
AGND
6.8 kΩ
1 µF
10 kΩ
OUTM (–)
+
12 nF
–V
10 kΩ
15 nF
10 kΩ
OUTP (+)
VCOM(DAC)
AGND
0.1 µF
AGND
IGAIN
AGND
27 kΩ
(1%)
AGND
Figure 5–1. Application Schematic For Single-Ended Input/Output
5–1
TLC320AD56C
+V
VI1(–)
_
VI1(GND)
+
20 kΩ
INP (+)
–V
0.22 µF
20 kΩ
AGND
150 pF
2.5 V
VCOM(ADC)
0.1 µF
20 kΩ
+V
VI2(+)
_
VI2(GND)
+
150 pF
AGND
INM (–)
–V
20 kΩ
0.22 µF
AGND
38.4 kΩ
0.39 nF
+V
_
VO(+)
+
6.8 kΩ
10 kΩ
1 µF
OUTM (–)
12 nF
10 kΩ
10 kΩ
–V
38.4 kΩ
AGND
AGND
8.2 nF
0.39 nF
+V
_
VO(–)
6.8 kΩ
VCOM(DAC)
0.1 µF
AGND
10 kΩ
1 µF
10 kΩ
OUTP (+)
+
12 nF
10 kΩ
IGAIN
–V
AGND
AGND
27 kΩ
(1%)
AGND
Figure 5–2. Application Schematic For Differential Input/Output
5–2
Appendix A
Register Set
Bits D12 through D8 in a secondary serial communication comprise the address of the register that is written
with the data carried in D7 through D0. D13 determines a read or write cycle to the addressed register. When
low, a write cycle is selected.
Table A–1 shows the register map.
Table A–1. Data and Control Registers
REGISTER NO.
NO
BITS
REGISTER NAME
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
0
No operation
1
0
0
0
0
0
0
0
1
Control 1
2
0
0
0
0
0
0
1
0
Control 2
Table A–2. Control 1 Register
BITS
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
1
–
–
–
–
–
–
–
Software reset
0
–
–
–
–
–
–
–
Software reset not asserted
–
1
–
–
–
–
–
–
Software power down (analog and filters)
–
0
–
–
–
–
–
–
Software power down (not asserted)
–
–
1
–
–
–
–
–
Select AUXP and AUXM
–
–
0
–
–
–
–
–
Select INP and INM
–
–
–
0
–
–
–
–
Select INP and INM for monitor
–
–
–
1
–
–
–
–
Select AUXP and AUXM for monitor
–
–
–
–
1
1
–
–
Monitor amp gain = – 18 dB (see Note B)
–
–
–
–
1
0
–
–
Monitor amp gain = – 8 dB (see Note B)
–
–
–
–
0
1
–
–
Monitor amp gain = 0 dB (see Note B)
–
–
–
–
0
0
–
–
Monitor amp mute
–
–
–
–
–
–
1
–
Digital loopback asserted
–
–
–
–
–
–
0
–
Digital loopback not asserted
–
–
–
–
–
–
–
1
16-bit mode (hardware secondary requests)
–
–
–
–
–
–
–
0
Not 16-bit mode (software secondary requests)
NOTES:
A. Default value: 00000000
B. These gains are for a single-ended input. The gain is 6 dB lower with a differential input.
The software reset is a one-shot operation and this bit is cleared to 0 after reset. It is not necessary to write
a zero to end the master reset operation. Writing 0s to the reserved bits is suggested.
A–1
Table A–3. Control 2 Register
BITS
D7
D6
D5
–
–
–
–
–
–
DESCRIPTION
D4
D3
D2
D1
D0
X
–
–
–
–
–
Decimator FIR overflow flag (valid only during read cycle)
–
X
–
–
–
–
FLAG 1 output value (valid only during read cycle)
–
–
–
X
–
–
–
FLAG 0 output value (valid only during read cycle)
–
–
–
–
1
–
–
Phone mode enabled
–
–
–
–
–
0
–
–
Phone mode disabled
X
X
–
–
–
–
X
X
Reserved
NOTES:
A. Default value: 00000000
B. X = do not care
Writing 0s to the reserved bits is suggested.
A–2
Appendix B
Mechanical Data
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
D
0.120 (3,05)
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
18
4
E
D2/E2
E1
D2/E2
14
8
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
B–1
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
0,13 NOM
48
13
1
Gage Plane
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
1,60 MAX
0,10
4040052 / B 03/95
NOTES: A.
B.
C.
D.
B–2
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MO-136
Also may be a thermally enhanced plastic package with leads conected to the die pads