HSP43124 Data Sheet May 1999 Serial I/O Filter Features The Serial I/O Filter is a high performance filter engine that is ideal for off loading the burden of filter processing from a DSP microprocessor. It supports a variety of multistage filter configurations based on a user programmable filter and fixed coefficient halfband filters. These configurations include a programmable FIR filter of up to 256 taps, a cascade of from one to five halfband filters, or a cascade of halfband filters followed by a programmable FIR. The half band filters each decimate by a factor of two, and the FIR filter decimates from one to eight. When all six filters are selected, a maximum decimation of 256 is provided. • 45MHz Clock Rate File Number 3555.6 • 256 Tap Programmable FIR Filter • 24-Bit Data, 32-Bit Coefficients • Cascade of up to 5 Half Band Filters • Decimation from 1 to 256 • Two Pin Interface for Down Conversion by FS/4 • Multiplier for Mixing or Scaling Input with an External Source • Serial I/O Compatible with Most DSP Microprocessors For digital tuning applications, a separate multiplier is provided which allows the incoming data stream to be multiplied, or mixed, by a user supplied mix factor. A two pin interface is provided for serially loading the mix factor from an external source or selecting the mix factor from an onboard ROM. The on-board ROM contains samples of a sinusoid capable of spectrally shifting the input data by one quarter of the sample rate, FS/4. This allows the chip to function as a digital down converter when the filter stages are configured as a low-pass filter. Applications • Low Cost FIR Filter • Filter Co-Processor • Digital Tuner Ordering Information PART NUMBER The serial interface for3- input and output data is compatible with the serial ports of common DSP microprocessors. Coefficients and configuration data are loaded over a bidirectional eight bit interface. TEMP. RANGE (oC) PACKAGE PKG. NO. HSP43124PC-45 0 to 70 28 Ld PDIP E28.6 HSP43124PC-33 0 to 70 28 Ld PDIP E28.6 HSP43124SC-45 0 to 70 28 Ld SOIC M28.3 HSP43124SC-33 0 to 70 28 Ld SOIC M28.3 HSP43124SI-40 -40 to 85 28 Ld SOIC M28.3 MXIN HALF BAND FILTER #1 HALF BAND FILTER #2 HALF BAND FILTER #5 SYNCMX OUTPUT FORMATTER SYNCIN INPUT FORMATTER DIN SCLK PROGRAMMABLE FIR FILTER Block Diagram DOUT SYNCOUT CLKOUT 1 FCLK FSYNC RD WR C0-7 A0-2 CONTROL INTERFACE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HSP43124 Pinout 28 LEAD PDIP, SOIC TOP VIEW SCLK 1 SYNCIN 2 27 DOUT GND 3 26 SYNCOUT MXIN 4 25 CLKOUT SYNCMX 5 2 28 DIN 24 VCC FSYNC 6 23 C7 VCC 7 22 C6 FCLK 8 21 C5 WR 9 20 C4 RD 10 19 GND A0 11 18 C3 A1 12 17 C2 A2 13 16 C1 VCC 14 15 C0 HSP43124 Pin Description NAME TYPE DESCRIPTION VCC - +5V Power Supply GND - Ground DIN I Serial Data Input. The bit value present on this input is sampled on the rising edge of SCLK. A “HIGH” on this input represents a “1”, and a low on this input represents “0”. The word format and operation of serial interface are contained in the Data Input Section. SYNCIN I Data Sync. The HSP43124 is synchronized to the beginning of a new data word on DIN when SCLK samples SYNCIN “HIGH” one SCLK before the first bit of the new word. NOTE: SYNCIN should not maintain a “HIGH” state for longer than one SCLK cycle. SCLK I Serial Input CLK. The rising edge of SCLK clocks data on DIN and MXIN into the part. The following signals are synchronous to this clock: DIN, SYNCIN, MXIN, SYNCMX. MXIN I Mix Factor Input. MXIN is the serial input for the mix factor. It is sampled on the rising edge of SCLK. A “HIGH” on this input represents a “1”, and a low on this input represents “0”. Also used to specify the Weaver Modulator ROM output as a part of the two pin FS/4 down conversion interface. Details on word format and operation are contained in the Mix Factor Section. SYNCMX I Mix Factor Sync. The HSP43124 is synchronized to the beginning of a serially input mix factor when SCLK samples SYNCMX “HIGH” one SCLK before the first bit of the new mix factor. NOTE: SYNCMX should only pulse “HIGH” for one SCLK cycle. Also used to specify Weaver Modulator ROM output as a part of the two pin FS/4 down conversion interface. FCLK I Filter Clock. The filter clock determines the processing speed of the Filter Compute Engine. Clock rate requirements on FCLK for particular filter configurations is discussed in the Filter Compute Engine Section. This clock may be asynchronous to the serial input clock (SCLK). FSYNC is synchronous to this clock. FSYNC I Filter Sync. This input, when sampled low by the rising edge of FCLK, resets the filter compute engine so that the data sample following the next SYNCIN cycle is the first data sample into the filter structure. If a data stream is currently being input, the current sum of products and the input data are “canceled” and the DIN pin is ignored until the next SYNCIN cycle occurs. WR I Write. The falling edge of WR loads data present on C0-7 into the configuration or coefficient register specified by the address on A0-2. The WR signal is asynchronous to all other clocks. NOTE: WR should not be low when RD is low. RD I Read. The falling edge of RD accesses the control registers or coefficient RAM addressed by A0-2 and places the contents of that memory location on C0-7. When RD returns “HIGH” the C0-7 bus functions as an input bus. The RD pin is asynchronous to all other clocks. NOTE: RD should not be low when WR is low. A0-2 I Address Bus. The A0-2 inputs are decoded on the falling edge of both RD and WR. Table 1 shows the address map for the control registers. C0-7 I/O Control and Coefficient bus. This bidirectional bus is used to access the control registers and coefficient RAM. CLKOUT O Output Clock. Programmable bit clock for serial output. NOTE: Assertion of FSYNC initializes CLKOUT to a high state. SYNCOUT O Output Data Sync. SYNYOUT is asserted HIGH for one CLKOUT cycle before the first bit of a new output sample is available on DOUT. DOUT O Serial Data Output. The bit stream is synchronous to the rising edge of CLKOUT. (See the Serial Output Formatter section for additional details.) 3 HSP43124 INPUT FORMATTER DIN VARIABLE LENGTH SHIFT REGISTER (8-24-BITS) SYNCIN SYNCMX MUX # BITS † MSB F/2 † FORMAT † MULTIPLY/ ACCUMULATOR 57 MSB F/L † FCLK † CLKOUT # BITS † SYNCOUT SERIAL MULTIPLIER SYNCMX MIX MXIN SEL † WEAVER MODULATOR ROM MXIN OUTPUT FORMATTER SYNCIN INPUT HOLDING REG MIX FACTOR HOLDING REG FILTER COMPUTE ENGINE VARIABLE LENGTH SHIFT REGISTER (8 TO 24 BITS) M U 48 X ROUND/ SATURATE 24 REGISTER FILE 25 + + 32 CONTROL † PARAMETERS † FILT EN † MUX # HBs † R E G ROUND/ SATURATE CLKOUT DOUT ROUND † DECIMATION FORMAT † RATE † GAIN COR † FIR SYM † CONTROL HALFBAND COEFFICIENT ROM # BITS † FORMAT † COEFFICIENT RAM RD EN † FILTER LENGTH † RAM ACCESS † A0-2 C0-7 WR RD FSYNC FCLK †Indicates configuration control word data parameter. SCLK FIGURE 1. SERIAL FILTER BLOCK DIAGRAM Functional Descriptions The HSP43124 is a high performance digital filter designed to process a serial input data stream. A second serial interface is provided for mix factor inputs, which are multiplied by the input samples as shown in Figure 1. The multiplier result is passed to the Filter Compute Engine for processing. The Filter Compute Engine centers around a single multiply/accumulator (MAC). The MAC performs the sum-ofproducts required by a particular filter configuration. The processing rate of the MAC is determined by the filter clock, FCLK. Increasing FCLK relative to the input sample rate increases the length of filter that can be realized. The filtered results are passed to the Output Formatter where they are rounded or truncated to a user defined bit width. The Output Formatter then generates the timing and synchronization signals required to serially transmit the data to an external device. Filter Configuration Data is written to the configuration control registers on the falling edge of the WR input. This requires that the address, A0-2, and data, C0-7, be stable and valid on the falling edge of the WR, as shown in Figure 2. NOTE: WR should not be active low when RD is active low. Data is read from the configuration control registers on the falling edge of the RD input. The contents of a particular register are accessed by setting up an address, A0-2, to the falling edge of RD as shown in Figure 2. The data is output on C0-7. The data on C0-7 remains valid until RD returns HIGH, at which point the C0-7 bus is Three-Stated and functions as an input. For proper operation, the address on A0-2 must be held until RD returns “high” as shown in Figure 2. NOTE: RD should not be active low when WR is active low. WRITE TIMING WR A0-2 C0-7 The HSP43124 is configured for operation by loading a set of eight control registers. These registers are written through a bidirectional interface which is also used for reading the control registers. The interface consists of an 8-bit data bus, C0-7, a 3-bit address bus, A0-2, and read/write lines, RD and WR. The address map for the control registers is shown in Table 1. READ TIMING RD A0-2 C0-7 FIGURE 2. READ/WRITE TIMING 4 HSP43124 TABLE 1. CONFIGURATION CONTROL REGISTER FUNCTIONAL DESCRIPTION ADDRESS 000 REGISTER DESCRIPTION Filter Configuration BIT POSITIONS BIT FUNCTION 2-0 Specifies the number of halfbands to use. Number ranges from 0 to 5. Other values are invalid. 3 Filter Enable bit. 1 = Enable. 0 = Minimum filter bypass (either the FIR or HBF must be enabled to get an output). 4 Coefficient read enable. When set to 1, enables reading and disables writing of coefficient RAM. NOTE: This bit must be set to 0 prior to writing the Coefficient RAM. 7-5 FIR Decimation Rate. Range is 1-8 (8 = 000). 001 Programmable FIR Filter Length 7-0 Number of Taps in the Programmable FIR Filter. For even or odd symmetric filters, values range from 4- 256, 1 to 3 are invalid, and 0000000 = 256. For asymmetric filters, the value loaded in this register must be two times the actual number of coefficients. 010 Coefficient RAM Access 7-0 Coefficient RAM is loaded by multiple writes to this address. (See Writing Coefficients section for additional details.) 011 Input Format 4-0 Number of bits in input data word, from 8 (01000) to 24 (11000). Values outside the range of 8 - 24 are invalid. 100 Output Timing 5 Number System. 0 = Two’s Complement, 1 = Offset Binary. 6 Serial Format. 1 = MSB First, 0 = LSB First. 7 Unused 4-0 5 101 110 111 Output Format Filter Symmetry Mix Factor Format 1 = MSB First, 0 = LSB First. 6-7 Unused 4-0 Number of bits in output data word, from 8 to 32. A value of 32 is represented by 00000, and values from 1 to 7 are invalid. 5 Round Select. 1 = Round to Selected Number of Bits, 0 = Truncate. 6 Number System. 0 = Two’s Complement, 1 = Offset Binary. 7 Gain Correction. 1 = Apply scale factor of 2 to data. 0 = No Scaling. 1-0 00 = Even Symmetric FIR Coefficients 01 = Non-Symmetric Coefficients 10 = Odd Symmetric FIR 7-2 Reserved: Must be 0. 4-0 Number of bits in mix factor, from 8 (01000) to 24 (11000). Values outside the range of 8 - 24 are invalid. 5 Serial Format. 1 = MSB First, 0 = LSB First. 6 Mix Factor Select. 1 = Serial Input, 0 = Weaver modulator look-up-table. 7 Unused Writing Coefficients The HSP43124 provides a register bank to store filter coefficients for configurations which use the programmable filter. The register bank consists of 128 thirty-two-bit registers. Each register is loaded by 4 one byte writes to the bidirectional interface used for loading the configuration registers. The coefficients are loaded in order from least significant byte (LSB) to most significant byte (MSB). 5 Number of FCLKS per CLKOUT. Range 1 to 32. (00000 = 32 FCLKS) The coefficient registers are loaded by first setting the coefficient read enable bit to “0” (bit 4 of the Filter Configuration Register). Next, coefficients are loaded by setting the A2-0 address to 010 (binary) and writing one byte at a time as shown in Figure 3. The down loaded bytes are stored in a holding register until the 4th write cycle. On completion of the fourth write cycle, the contents of the holding register are loaded into the Coefficient RAM, and the write pointer is incremented to the next register. If the user attempts to write more than 128 coefficients, the pointer HSP43124 halts at the 128th register location, and writing is disabled. The coefficient address pointer is reset when any other configuration register is written or read. NOTE: A new coefficient set may be loaded during a filter calculation at the risk of corrupting output data until the load is complete. WR and ending with the center tap. The coefficient associated with the first tap is the first to be multiplied by an incoming data sample as shown in Figure 5. For even/odd symmetric filters of length N, N/2 coefficients must be loaded if the filter length is even, and (N+1)/2 coefficients must be loaded if the filter length is odd. For example, a 17 tap symmetric filter would require the loading of 9 coefficients. Enough storage is provided for a 256 tap symmetric filter. A0-2 = 010 (BINARY) A0-2 X2 Z -1 X(n) INPUT C0-7 LSB MSB LSB SECOND COEFFICIENT FIGURE 3. COEFFICIENT LOADING The number of coefficients that must be loaded is dependent on whether the coefficient set exhibits even symmetry, odd symmetry, or asymmetry (see Figure 4). EVEN SYMMETRIC POINT OF SYMMETRY ODD LENGTH EVEN LENGTH NOTE: Filters with even symmetric coefficients exhibit symmetry about the center of the coefficient set. Most FIR filters have coefficients which are symmetric in nature. ODD SYMMETRIC CENTER OF COEFFICIENT SET 0.5 0.25 0.1 -0.1 -0.25 Z -1 X0 MSB C0 FIRST COEFFICIENT X1 -0.5 NOTE: Odd symmetric coefficients have a coefficient envelope which has the characteristics of an odd function (i.e. coefficients which are equidistant from the center of the coefficient set are equal in magnitude but opposite in sign). Coefficients designed to function as a differentiator or Hilbert Transform exhibit these characteristics. ASYMMETRIC C1 C2 LAST FILTER TAP FIRST FILTER TAP + Y(n) OUTPUT Y(n) = C0X2 + C1X1 + C2X0 FIGURE 5. THREE TAP TRANSVERSAL FILTER ARCHITECTURE For asymmetric filters the entire coefficient set must be loaded. The coefficients are loaded in order starting with the first tap and ending with the final filter tap (see Figure 5 for tap/coefficient association). Enough storage is provided for a 128 tap asymmetric filter. For asymmetric filters the value loaded into the Programmable Filter Length Register addressed must be twice the actual number of coefficients. Reading Coefficients The coefficients are read from the storage registers one byte at a time via C0-7 as shown in Figure 6. To read the coefficients, the user first sets the Coefficient Read Enable bit to 1 (bit 4 of Filter Configuration Control Register). Setting this bit resets the RAM read pointer and disables the RAM from being written. Next, with A2-0 = 010, multiple “high” to “low” transitions of RD, output the coefficients on C0-7, one byte at a time, in the order they were written. NOTE: RD should not be “low” when WR is “low”. RD A0-2 A0-2 = 010 (BINARY) C0-7 LSB MSB FIRST COEFFICIENT LSB MSB SECOND COEFFICIENT FIGURE 6. COEFFICIENT READING NOTE: Asymmetric Coefficient sets exhibit no symmetry. FIGURE 4. COEFFICIENT CHARACTERISTICS For filters that exhibit either even or odd symmetry, only the unique half of the coefficient set must be loaded. The coefficients are loaded in order starting with the first filter tap 6 Data Input Data is serially input to the HSP43124 through the DIN input. On the rising edge of SCLK, the bit value present at DIN is clocked into the Variable Length Shift Register. The beginning of a serial data word is designated by asserting SYNCIN “high” one SCLK prior to the first data bit as shown HSP43124 in Figure 7. On the following SCLK, the first data bit is clocked into the Variable Length Shift Register. Data bits are clocked into the shift register until the data word, of user programmable length (8 to 24 bits), is complete. At this point, the shifting of data into the register is disabled and its contents are held until SYNCIN is asserted on the rising edge of SCLK. When this occurs, the contents of the Variable Length Shift Register are transferred to the Input Holding Register, and the shift register is enabled to accept serial data on the following SCLK. The serial data word may be two’s complement or offset binary and may be input most significant bit (MSB) first or least significant bit (LSB) first as defined in the Input Format Register (see Table 1). If a data word is specified to be less than 24 bits, the least significant bits of the Input Holding Register are zeroed. NOTE: SYNCIN should not be “high” for longer than one SCLK cycle. SCLK The MXIN and SYNCMX inputs can function as two pin interfaces to Weaver Modulator ROM addresses. Used in proper sequence, down conversion by FS/4 can be achieved. These inputs are latched on the rising edge of SCLK when SYNCIN is high as shown in Figure 9. The mapping of SYNCIN and MXIN to ROM outputs is given in Table 2. When SYNCIN is high on the rising edge of SCLK, the output of the ROM is transferred to the Mix Factor holding register, and the SYNCMX and MXIN inputs are decoded to produce a new ROM output. As a result, there is a latency of one SYNCIN cycle between when the SYNCMX and MXIN inputs are decoded and when the ROM output is loaded into the Mix Factor Holding register. TABLE 2. WEAVER MODULATOR ROM DECODING SYNCIN/ SYCNMX DIN/ MXIN multiplier. The mix factor data word is programmable in length from 8 to 24 bits and may be input MSB or LSB first as specified in the Mix Factor Format Register. If a data word is specified to be less than 24 bits, the least significant bits of the Mix Factor Holding Register are zeroed. LSB LSB SYNC LEADS DATA NOTE: Assumes data is being loaded LSB first. FIGURE 7. SERIAL INPUT TIMING FOR EITHER DIN OR MXIN INPUTS Mix Factor The HSP43124 provides a second serial interface for loading values which are multiplied by the input samples in the serial multiplier. These values, or mix factors, are input using the MXIN and SYNCMX pins. Aside from being used as a serial input, this interface can also be used to select mix factors from the Weaver Modulator ROM. The mix factor source is specified in the Mix Factor Format Register (see Table 1). NOTE: Data is passed unmodified through the serial multiplier by selecting the Weaver Modulation ROM as the mix factor source and tying both SYNCMX and MXIN “high”. The procedure for loading serial mix factors is similar to that for the loading of data via the DIN input. The bit value present on MXIN is clocked into the Variable Length Shift register by the rising edge of SCLK. The beginning of the serial word is designated by the assertion of SYNCMX one SCLK prior to the first bit of the serial word as shown in Figure 7. After the serial word has been clocked into the shift register, the shifting of bits into the register is disabled and its contents are held until the next assertion of SYNCMX. When SYNCMX is asserted on the rising edge of SCLK, the contents of the Variable Length Shift register are transferred into the Mix Factor Holding Register. The parallel output of the Mix Factor Holding Register feeds directly into the serial 7 SYNCMX MXIN MIX FACTOR 0 0 0 0 1 -1 1 0 0 1 1 1 Serial Multiplier The Serial Multiplier multiplies the Mix Factor Holding register by the contents of the Input Holding register. The multiplication cycle is initiated when SYNCIN is sampled high by the rising edge of SCLK. This transfers the contents of the Variable Length Shift register to the Input Holding Register, and loads the output of the Mix Factor Holding Register into the Serial Multiplier. On subsequent SCLKs, the contents of the Input Holding Register are shifted into the Serial Multiplier for processing. When the last data bit is shifted into the multiplier, the multiplication cycle is complete and the result is written to the Register File on the next rising edge of FCLK. The synchronization between a data sample and the mix factor it is to be multiplied by is dependent on which mix factor source is specified. For mix factors which are input serially, the mix factor is loaded concurrently with the data sample to be multiplied (see Figure 8). HSP43124 The cascade of up to five halfband filters is an efficient decimating filter structure. Each fixed coefficient filter in the chain introduces a decimation of two, and the aggregate decimation rate of the entire halfband filtering stage is given by: SCLK SYNCIN MSB LSB DIN LSB DECHB = 2(NUMBER OF HALFBAND FILTERS SELECTED) X0 Thus, a cascade of 3 halfband filters would decimate the input sample stream by a factor of 8. SYNCMX MSB LSB LSB MXIN M0 SYNC LEADS DATA FIGURE 8. DATA/MIX FACTOR SYNCHRONIZATION FOR SERIALLY INPUT MIX FACTORS NOTE: Figure 8 shows the loading of a data sample, X0, such that it will be multiplied by a mix factor designated by M0. For mix factor bit widths which are less than the input bit width, SYNCMX may be asserted before SYNCIN if desired. If the mix factor is generated by the Weaver Modulator ROM, the mix factor must be specified on MXIN and SYNCMX one SYNCIN before that which precedes the target data word (see Figure 9). SCLK SYNCIN MSB LSB DIN LSB X0 SYCNMX/ MXIN M0 SYNC LEADS DATA FIGURE 9. DATA/MIX FACTOR SYNCHRONIZATION WEAVER MODULATOR MIX FACTORS Filter Compute Engine The Filter Compute Engine centers around a multiply accumulator which is used to perform the sum-of-products required for a variety of filtering configurations. These configurations include a cascade of up to 5 halfband filters, a single symmetric filter of up to 256 taps, a single asymmetric filter of up to 128 taps, or a cascade of halfband filters followed by a programmable filter. The filter configuration is specified by programming the Filter Configuration Register (see Table 1). 8 (EQ. 1) Figure 10A is a block diagram of the halfband filter section. The normalized frequencies for each halfband stage is labeled. Figure 10B is an illustration of a cascaded filter composed of five halfband filters. The final stage filter output is clocked at FCLK/32. Since the output of each filter is at half the rate of the input, the five halfband filter passband characteristics can be viewed on a single plot whose X axis is normalized to the filter output clock rate. Notice that all halfband filters, by design, have 120dB passbands that are less than the output rate divided by 2. Since the alias profile is well below -120dB in the filter passband, alias concerns are eliminated. The frequency responses of the five filters are presented graphically in Figure 10C and in tabular form in Table 3. Notice that the 6dB passband bandwidth (F = 0.25) is identical for all five halfband filters. The width of the transition band, however, is different for each filter. The transition band for the fifth halfband filter, HB5, is the narrowest while that for the first halfband filter, HB1, is the widest. The cascade of the halfband filters always terminates with HB5 and is preceded by filters in order of increasing transition bandwidth. For example, if the HSP43124 is configured to operate with three halfbands, the chain of filters would consist of HB3 followed by HB4 and terminated with HB5. If only one halfband is selected, HB5 is used. HSP43124 STAGE 1 INPUT TO HALFBAND SECTION Fs FCLK 4 FCLK 2 FCLK 8 FCLK 4 FCLK 2 FCLK FCLK 16 8 FCLK 4 FCLK 2 FCLK FCLK FCLK FCLK 8 4 32 FCLK 16 FS 2 FCLK FCLK FCLK FCLK 32 8 4 FS 2 FCLK FNORMALIZED = Fs HB5 35 TAP 0 1 FNORMALIZED = FHB1 FHB1= Fs or Fs/2 FHB1/2 1 FHB2 = FHB1 or FHB1/2 0 FNORMALIZED = FHB2 STAGE 4 19 TAP HB3 FHB2/2 MUX3 0 1 FNORMALIZED = FHB3 FCLK STAGE 3 HB4 23 TAP MUX4 FCLK STAGE 2 Fs/2 MUX5 3FCLK 4 FHB3 = FHB2 or FHB2/2 STAGE 5 HB2 11 TAP FCLK 64 FHB3/2 MUX2 FNORMALIZED = FHB4 0 1 FHB4 = FHB3 or FHB3/2 COMPOSITE FILTER 7 TAP HB1 FCLK 64 FHB4/2 0 MUX1 1 FCLK FIGURE 10B. SPECTRAL COMPOSITION OF FIVE CASCADED HALFBANDS OUTPUT OF HALFBAND SECTION 0 -20 MULTIPLEXERS’ DECODER TABLE AND EQUATIONS MUX1 MUX2 MUX3 MUX4 MUX5 000 0 0 0 0 0 001 0 0 0 0 1 MAGNITUDE (dB) BITS2-0 -60 -80 0 0 0 1 1 011 0 0 1 1 1 100 0 1 1 1 1 -160 101 1 1 1 1 1 -180 MUX2 = BIT2 MUX3 = (BIT1 AND BIT0) OR BIT2 HB1 TRANSITION BW HB2 HB3 HB4 HB5 -100 -120 010 MUX1 = (BIT2 AND BIT0) AND BIT1 6dB BANDWIDTH -40 -140 -200 0.125 0.25 0.375 0.5 NORMALIZED FREQUENCY (NORMALIZED TO OUTPUT FREQUENCY) MUX4 = BIT1 OR BIT2 MUX5 = BIT0 OR BIT1 OR BIT2 INVALID = BIT2 AND BIT1 FIGURE 10A. BLOCK DIAGRAM OF FIXED COEFFICIENT HALFBAND FILTERS 9 FIGURE 10C. COMPOSITE RESPONSE OF FIXED COEFFICIENT HALFBAND FILTERS WITH RESPECT TO THE NORMALIZED FREQUENCY SHOWN IN FIGURE 10A HSP43124 The coefficient set for each of the halfband filters is given in Table 4. These values are the 32-bit, two’s complement, integer representation of the filter coefficients. Scaling these values by 2-31 yields the fractional two’s complement coefficients used to achieve unity gain in the Filter Processor. and DECHB is the aggregate decimation rate for the cascade of halfband filters (see Table 5). For example, if the input sample rate is 800kHz, a 128 tap FIR filter with no decimation is selected, and a cascade of 2 halfband filters is used, calculate the minimum FCLK rate as follows: If a specific frequency response is desired, a programmable FIR filter may be activated. The filter compute engine takes advantage of symmetry in FIR coefficients is by summing data samples sharing a common coefficient prior to multiplication. In this manner, two filter taps are calculated per multiply accumulate cycle. If an asymmetric filter is specified, only one tap per multiply accumulate cycle is calculated. 800kHz 128 - + 33 + 1 --------------------- -------- 1 4 2 Min FCLK = ( 200kHz ) [ 64 + 33 + 1 ] = 19.6MHz or at least 14 (800kHz) = 11.2MHz The processing rate of the Filter Compute Engine is proportional to FCLK. As a result, the frequency of FCLK must exceed a minimum value to insure that a filter calculation is complete before the result is required for output. In configurations which do not use decimation, one input sample period is available for filter calculation before an output is required. For configurations which employ decimation, up to 256 input sample periods may be available for filter calculation. The following equation specifies the minimum FCLK rate required for configurations which use the programmable filter as an FIR filter. FS -------------------- ( TAPS/(2*DEC FIR ) + HB CLKS + 1 ) Min FCLK = DEC HB or at least14F S when Halfbands are used (EQ. 3) Thus, the Min FCLK is 19.6MHz. NOTE: For configurations in which the halfband filters are used, the FCLK rate must exceed 14FS. The longest length FIR filter realizable for a particular configuration is determined by solving the above equation for TAPS. The resulting expression is given below. Max TAPS = 2DECFIR ((FCLK/FS)DECHB - HBCLKS - 1) (EQ. 4) The maximum throughput sample rate may be specified by solving the above equation for FS. The resulting equation is Max FS = FCLK*DECHB /(TAPS/(2*DECFIR) + HBCLKS + 1). (EQ. 5) NOTE: For configurations using filters with asymmetric coefficients, the term TAPS in the above equations should be multiplied by two in order to determine the correct FCLK. (EQ. 2) In this equation FS is the input sample rate (SCLK/# Bits in SER word), TAPS is the number of taps in the FIR filter (0 to 256), DECFIR is the decimation rate of the programmable FIR (1 to 8), HBCLKS is a compute clock factor based on the number of halfband filters in the configuration (see Table 5), The Filter Compute Engine is synchronized with an incoming data stream by asserting the FSYNC input. When this input is sampled low by the rising edge of FCLK, the Compute Engine is reset, and the data word following the next assertion of SYNCIN is recognized as the first data sample input to the filter structure. TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS NORMALIZED FREQUENCY HALFBAND #1 0.000000 -0.000000 0.007812 0.000000 0.015625 -0.000113 0.023438 HALFBAND #3 HALFBAND #4 HALFBAND #5 0.000000 0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000000 -0.000677 -0.000006 -0.000000 -0.000000 -0.000000 0.031250 -0.002243 -0.000052 -0.000000 -0.000000 -0.000000 0.039062 -0.005569 -0.000227 -0.000000 -0.000000 0.000000 0.046875 -0.011596 -0.000719 -0.000001 0.000000 -0.000000 0.054688 -0.021433 -0.001859 -0.000009 -0.000000 -0.000000 0.062500 -0.036333 -0.004165 -0.000041 -0.000000 -0.000000 0.070312 -0.057670 -0.008391 -0.000149 -0.000001 -0.000000 0.078125 -0.086916 -0.015557 -0.000448 -0.000012 -0.000000 0.085938 -0.125619 -0.026983 -0.001175 -0.000066 -0.000000 0.093750 -0.175382 -0.044301 -0.002767 -0.000258 -0.000000 10 HALFBAND #2 HSP43124 TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS (Continued) NORMALIZED FREQUENCY HALFBAND #1 HALFBAND #2 HALFBAND #3 HALFBAND #4 HALFBAND #5 0.101562 -0.237843 -0.069457 -0.005963 -0.000815 -0.000000 0.109375 -0.314663 -0.104701 -0.011924 -0.002208 -0.000000 0.117188 -0.407509 -0.152566 -0.022368 -0.005313 -0.000000 0.125000 -0.518045 -0.215834 -0.039695 -0.011613 -0.000000 0.132812 -0.647925 -0.297499 -0.067100 -0.023435 -0.000031 0.140625 -0.798791 -0.400727 -0.108640 -0.044186 -0.000287 0.148438 -0.972266 -0.528809 -0.169262 -0.078552 -0.001468 0.156250 -1.169959 -0.685131 -0.254777 -0.132639 -0.005427 0.164062 -1.393465 -0.873129 -0.371785 -0.214009 -0.016180 0.171875 -1.644372 -1.096269 -0.527552 -0.331613 -0.041152 0.179688 -1.924262 -1.358019 -0.729872 -0.495620 -0.092409 0.187500 -2.234728 -1.661842 -0.986908 -0.717181 -0.187497 0.195312 -2.577375 -2.011181 -1.307047 -1.008144 -0.349593 0.203125 -2.953834 -2.409468 -1.698769 -1.380771 -0.606862 0.210938 -3.365774 -2.860128 -2.170548 -1.847495 -0.991193 0.218750 -3.814917 -3.366593 -2.730783 -2.420719 -1.536664 0.226562 -4.303048 -3.932319 -3.387764 -3.112694 -2.278126 0.234375 -4.832037 -4.560817 -4.149669 -3.935463 -3.250174 0.242188 -5.403856 -5.255675 -5.024594 -4.900864 -4.486639 0.250000 -6.020599 -6.020600 -6.020600 -6.020600 -6.020600 0.257812 -6.684504 -6.859450 -7.145791 -7.306352 -7.884833 0.265625 -7.397981 -7.776287 -8.408404 -8.769932 -10.112627 0.273438 -8.163642 -8.775419 -9.816921 -10.423476 -12.738912 0.281250 -8.984339 -9.861469 -11.380193 -12.279667 -15.801714 0.289062 -9.863195 -11.039433 -13.107586 -14.352002 -19.344007 0.296875 -10.803663 -12.314765 -15.009147 -16.655094 -23.416153 0.304688 -11.809574 -13.693460 -17.095793 -19.205034 -28.079247 0.312500 -12.885208 -15.182171 -19.379534 -22.019831 -33.409992 0.320312 -14.035372 -16.788332 -21.873730 -25.119940 -39.508194 0.328125 -15.265501 -18.520315 -24.593418 -28.528942 -46.509052 0.335938 -16.581776 -20.387625 -27.555685 -32.274414 -54.604954 0.343750 -17.991278 -22.401131 -30.780161 -36.389088 -64.087959 0.351562 -19.502172 -24.573368 -34.289623 -40.912403 -75.444221 0.359375 -21.123947 -26.918915 -38.110786 -45.892738 -89.610390 0.367188 -22.867725 -29.454887 -42.275345 -51.390583 -108.973686 0.375000 -24.746664 -32.201569 -46.821358 -57.483341 -152.503693 0.382812 -26.776485 -35.183285 -51.795181 -64.272881 -153.443375 0.390625 -28.976198 -38.429543 -57.254162 -71.898048 -158.914017 0.398438 -31.369083 -41.976673 -63.270584 -80.556969 -156.960175 0.406250 -33.984089 -45.870125 -69.937607 -90.550629 -153.317627 0.414062 -36.857830 -50.167850 -77.378593 -102.379677 -161.115540 0.421875 -40.037594 -54.945438 -85.762718 -117.007339 -153.504684 11 HSP43124 TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS (Continued) NORMALIZED FREQUENCY HALFBAND #1 HALFBAND #2 HALFBAND #3 HALFBAND #4 HALFBAND #5 0.429688 -43.585945 -60.304272 -95.332924 -136.890198 -158.650345 0.437500 -47.588165 -66.385063 -106.462181 -185.130432 -154.637756 0.445312 -52.164894 -73.392075 -119.793030 -187.297241 -153.870453 0.453125 -57.495132 -81.640152 -136.802948 -182.300125 -161.882385 0.460938 -63.861992 -91.658478 -175.030167 -203.460876 -152.278915 0.468750 -71.755898 -104.468010 -158.939362 -174.691895 -164.329758 0.476562 -82.156616 -122.641861 -157.095886 -174.737076 -153.535690 0.484375 -97.627930 -166.537369 -155.613434 -175.108841 -153.507477 0.492188 -139.751450 -165.699081 -154.708450 -169.966568 -167.665482 TABLE 4. HALFBAND FILTER COEFFICIENTS (32 BITS, UN-NORMALIZED) COEFFICIENT HALFBAND #1 HALFBAND #2 HALFBAND #3 HALFBAND #4 HALFBAND #5 C0 -67230275 12724188 624169 -197705 23964 C1 0 0 0 0 0 C2 604101076 -105279784 -6983862 2303514 -242570 C3 1073741823 0 0 0 0 C4 604101076 629426509 38140187 -13225905 1306852 C5 0 1073741827 0 0 0 C6 -67230275 629426509 -145867861 51077176 -4942818 C7 0 0 0 0 C8 -105279784 650958284 -161054660 14717750 C9 0 1073741793 0 0 C10 12724188 650958284 657968488 -37027884 C11 0 1073741825 0 C12 -145867861 657968488 84032070 C13 0 0 0 C14 38140187 -161054660 -191585682 C15 0 0 0 C16 -6983862 51077176 670589251 C17 0 0 1073741824 C18 624169 -13225905 670589251 C19 0 0 C20 2303514 -191585682 C21 0 0 C22 -197705 84032070 C23 0 C24 -37027884 C25 0 C26 14717750 C27 0 C28 -4942818 C29 0 12 HSP43124 TABLE 4. HALFBAND FILTER COEFFICIENTS (32 BITS, UN-NORMALIZED) (Continued) COEFFICIENT HALFBAND #1 HALFBAND #2 HALFBAND #3 HALFBAND #4 HALFBAND #5 C30 1306852 C31 0 C32 -242570 C33 0 C34 23964 TABLE 5. PERFORMANCE ENVELOPE PARAMETERS NUMBER OF HALFBANDS HBCLKS DECHB 0 0 1 1 13 2 2 33 4 3 69 8 4 125 16 5 221 32 The duty cycle of CLKOUT is 50% for rates that have an even number of FCLKs per CLKOUT. For rates that have and odd number of FCLKs per CLKOUT the high portion of the CLKOUT waveform spans (n+1)/2 FCLKs and the low portion spans (n-1)/2 FCLKs where n is the number of FCLKs. External devices synchronize to the beginning of an output data word by monitoring SYNCOUT. This output is asserted “high” one CLKOUT prior to the first bit of the next data word as shown in Figure 11. CLKOUT Serial Output Formatter The Output Formatter serializes the parallel output of the filter compute engine and generates the timing and synchronization signals required to support a serial interface. The Formatter produces serial data words with programmable lengths from 8 to 32 bits. The data words may be organized with either most or least significant bit first. Also, the data word may be rounded or truncated to the desired length and the format of the output data may be specified as either two's complement or offset binary. To simplify applications where the Serial I/O Filter is used as a down converter, the output formatter can be configured to scale the output by a factor of 2. The above options are programmed via the Output Format and Output Timing Registers detailed in Table 1. The HSP43124 outputs a bit stream through DOUT which is synchronous to a programmable clock signal output on CLKOUT. The output clock, CLKOUT, is derived from FCLK and has a programmable rate from 1 to 1/32 times FCLK. SYNCOUT MSB DOUT LSB MSB LSB SYNC LEADS DATA NOTE: Assumes data is being output LSB first. FIGURE 11. SERIAL OUTPUT TIMING Input and Output Data Formats The data formats for the input, output and coefficients are fractional two’s complement. The bit weightings in the data words are given in Figure 12. Input or output data words programmed to have less than 24 bits, map to the most significant bit positions of the 24-bit word. For example, an input word defined to be 8 bits wide would map to the bit positions with weightings from -20 to 2-7. FRACTIONAL TWO’S COMPLEMENT FORMAT FOR 24-BIT INPUT AND OUTPUT 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 . -20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 FRACTIONAL TWO’S COMPLEMENT FORMAT FOR 32-BIT COEFFICIENTS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 . 7 6 5 4 3 2 1 -20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 NOTE: The negative sign on the MSB implies 2’s complement formt. FIGURE 12. DATA FORMATS 13 HSP43124 FCLK/SCLK Uncertainty Region Figure 13 shows a clocking relationship for the HSP43124 Serial I/O filter that could result in an uncertainty at the output. For simplicity, the frequency of FCLK and SCLK are assumed to be equal to each other, and CLKOUT is assumed to be equal to FLCK. When the rising edge of FCLK lags behind the rising edge of SCLK by a small amount of time (TSCFC), then the FCLK edge on which samples are read into the filter compute engine is determined by a race condition. In order to insure proper function for the HSP43124, TSCFC must be greater than 3.8ns. If exact timing (a particular clock edge for a specific data bit) then make SCLK and FCLK synchronous. If FCLK and SCLK are asynchronous, there will be jitter (a specific data bit will be output as 1 of 2 possible clock edges depending on the FCLK to SCLK phasing). For multiple part applications, use synchronous clocks or use separate syncs on what receives each data, as the outputs may vary by a clock cycle. The SYNCOUT jitter demonstrated by the 3/2 frequency example can be generalized to other asynchronous FFCLK/FSCLK ratios. Setting the frequencies for FCLK and SCLK at integer multiples of one another eliminates timing jitter in the output sample rate. 1 2 SCLK SYNCIN DIN MSB LSB MSB 1 2 CLKOUT SYNCOUT DOUT MSB LSB NULL FIGURE 14A. NUMBER OF CLKOUT = NUMBER OF BITS + 1 FOR THE TIME PERIOD BETWEEN SYNCOUTS WHERE FFCLK/FSCLK = 3/2 1 SYNCIN SYNCIN DIN MSB LSB LSB MSB MSB MSB 1 2 LSB MSB CLKOUT FCLK SYNCOUT SYNCOUT DOUT 2 SCLK SCLK DIN MSB LSB MSB MSB TSCFC FIGURE 13. FCLK/SCLK UNCERTAINTY REGION Asynchronous FCLK and SCLK If FCLK and SCLK are asynchronous clocks, then the output sample rate (tracked by SYNCOUT) of the HSP43124 might jitter in a real time system. This jitter will be demonstrated using an SCLK with a period that is 3/2 times the period of FCLK (i.e., FFCLK/FSCLK = 3/2), as shown in Figure 14A and Figure 14B. If the LSB occurs when there are two FCLK edges in one SCLK period (see Figure 14A), then a null data bit will occur in the DOUT data stream. If the LSB occurs when there is one FCLK edge in one SCLK period for the LSB (see Figure 14B), then no null data bit will occur. Given the 3/2 period relationship between FCLK and SCLK, the user can see that the SYNCOUT jitters by one clock. For example, if the output data is represent by 16 bits, then the number of CLKOUT rising edges between SYNCOUT pulses should jitter between 15 and 16. 14 DOUT MSB FIGURE 14B. NUMBER OF CLKOUT = NUMBER OF BITS FOR THE TIME PERIOD BETWEEN SYNCOUTS WHERE FFCLK/FSCLK = 3/2 HSP43124 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output Voltage . . . . . . . . . . . . . . . . .GND -0.5V to VCC +0.5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature . . . . . . . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Voltage Range (Commercial). . . . . . . . . . . . . . . . . . . 4.75V to 5.25V Voltage Range (Industrial) . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0oC to 70oC Temperature Range (Industrial) . . . . . . . . . . . . . . . . . -40oC to 85oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40,304 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications VCC = 5.0V +5%, TA = 0o to 70oC Commercial, TA = -40o to 85oC Industrial PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current ICCOP VCC = Max, FCLK = SCLK = 45MHz Notes 2, 3 - 203 mA Standby Power Supply Current ICCSB VCC = Max, Outputs Not Loaded - 500 µA Input Leakage Current II VCC = Max, Input = 0V or VCC -10 10 µA Output Leakage Current IO VCC = Max, Input = 0V or VCC -10 10 µA Clock Input High VIHC VCC = Max, FCLK and SCLK 3.0 - V Clock Input Low VILC VCC = Min, FCLK and SCLK - 0.8 V Logical One Input Voltage VIH VCC = Max 2.0 - V Logical Zero Input Voltage VIL VCC = Min - 0.8 V Logical One Output Voltage VOH IOH = -5mA, VCC = Min 2.6 - V Logical Zero Output Voltage VOL IOL = 5mA, VCC = Min - 0.4 V Input Capacitance CIN FCLK = SCLK = 1MHz All Measurements Referenced to GND. TA = 25oC, Note 4 - 10 pF - 10 pF Output Capacitance COUT NOTES: 2. Power supply current is proportional to frequency. Typical rating is 4.5mA/MHz. 3. Output load per test circuit and CL = 40pF. 4. Not tested, but characterized at initial design and at major process/design changes. 15 HSP43124 AC Electrical Specifications (Note 5) VCC = +4.75V to +5.25V, TA = 0oC to 70oC (Commercial) VCC = +4.75V to +5.25V, TA = -40oC to 85oC (Industrial) 45MHz PARAMETER SYMBOL NOTES 40MHz 33MHz MIN MAX MIN MAX MIN MAX UNITS FCLK, SCLK Period tCP 22 - 25 - 30 - ns FCLK, SCLK High tCH 8 - 10 - 12 - ns FCLK, SCLK Low tCL 8 - 10 - 12 - ns Setup Time DIN, MXIN, SYNCIN, SYNCMX to SCLK tDS 8 - 8 - 9 - ns Hold Time DIN, MXIN, SYNCIN, SYNCMX from SCLK tDH 0 - 0 - 0 - ns Setup Time FSYNC to FCLK tSS 8 - 8 - 8 - ns Hold Time FSYNC from FCLK tSH 0 - 0 - 0 - ns Setup Time C0-7, A0-2 to Falling Edge of WR tWS 10 - 10 - 10 - ns Hold Time C0-7, A0-2 from Falling Edge of WR tWH 3 - 3 - 3 - ns Setup Time A0-2 to Falling Edge of RD tRS 10 - 10 - 10 - ns Hold Time A0-2 from Rising Edge of RD tRH 0 - 0 - 0 - ns WR High tWRH 10 - 10 - 12 - ns WR Low tWRL 10 - 10 - 12 - ns RD High tRDH 10 - 10 - 10 - ns RD Low to Data Valid tRDO - 25 - 25 - 25 ns RD High to Output Disable tOD - 6 - 6 - 6 ns FCLK to CLKOUT tFOC - 12 - 13 - 14 ns CLKOUT to SYNCOUT, DOUT tDO - 8 - 9 - 10 ns Output Rise, Fall Time tRF - 3 - 3 - 3 ns Note 6 NOTES: 5. AC tests performed with CL = 40pF, IOL = 5mA, and IOH = -5mA. Input reference level for FCLK and SCLK is 2.0V, all other inputs 1.5V. Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V. 6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. AC Test Load Circuit DUT S1 CL (NOTE) SWITCH S1 OPEN FOR ICCSB AND ICCOP IOH ± 1.5V EQUIVALENT CIRCUIT NOTE: Test head capacitance. 16 IOL HSP43124 Waveforms tWRH tWRL WR tWS tWH tRF C0-7, A0-2 tRF 2.0V 0.8V FIGURE 16. OUTPUT RISE AND FALL TIMES FIGURE 15. TIMING RELATIVE TO WR tRDH RD tCP tCL tRS tCH tRH A0-2 SCLK tDS tDH DIN, MXIN, SYNCIN, SYNCMX C0-7 tRDO tOD FIGURE 17. INPUT DATA TIMING FIGURE 18. TIMING RELATIVE TO READ tCP tFOC FCLK tCH tCL CLKOUT SYNCOUT DOUT tDO tSS tSH FSYNC FIGURE 19. TIMING RELATIVE TO FLCK AND CLKOUT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 17