TI TLC320AD535

TLC320AD535C/I
Dual Channel Voice/Data Codec
Data Manual
2000
Mixed Signal Products
SLAS202B
IMPORTANT NOTICE
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Copyright  2000, Texas Instruments Incorporated
Contents
Section
1
2
3
4
5
Title
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Voice Channel Codec Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Data Channel Codec Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Device Requirements and System Overview . . . . . . . . . . . . . . . . . . . .
2.2
Codec Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Hybrid Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Voice Channel Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Miscellaneous Logic and Other Circuitry . . . . . . . . . . . . . . . . . . . . . . . .
Codec Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
ADC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
DAC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Sigma-Delta DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
Analog and Digital Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
Software Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Test Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Primary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1
FS High Mode Primary Communication Timing . . . . . . . . .
4.1.2
FS Low Mode Primary Communication Timing . . . . . . . . . .
4.2
Secondary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1
FS High Mode Secondary Communication Timing . . . . . . .
4.2.2
FS Low Mode Secondary Communication Timing . . . . . . .
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Absolute Maximum Ratings Over Operating Free-Air
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
1–1
1–1
1–2
1–3
1–4
1–4
1–5
1–5
2–1
2–1
2–1
2–1
2–1
2–1
3–1
3–1
3–1
3–1
3–1
3–1
3–2
3–2
3–2
3–2
3–2
3–3
4–1
4–1
4–2
4–2
4–3
4–4
4–4
5–1
5–1
5–1
iii
5.3
Electrical Characteristics Over Operating Free-Air Temperature
Range, DVDD = 5 V/3.3 V, xAVDD = 5 V/3.3 V,
MVDD = 5 V/3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5.3.1
Digital Inputs and Outputs, fs = 8 kHz,
Outputs Not Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5.3.2
ADC Channel, fs = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
5.3.3
ADC Dynamic Performance, fs = 8 kHz . . . . . . . . . . . . . . . . 5–2
5.3.3.1
ADC Signal-to-Noise . . . . . . . . . . . . . . . . . . . . . 5–2
5.3.3.2
ADC Signal-to-Distortion . . . . . . . . . . . . . . . . . . 5–2
5.3.3.3
ADC Signal-to-Distortion + Noise . . . . . . . . . . 5–2
5.3.4
ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
5.3.5
DAC Channel, fs = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
5.3.6
DAC Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
5.3.6.1
DAC Signal-to-Noise . . . . . . . . . . . . . . . . . . . . . 5–3
5.3.6.2
DAC Signal-to-Distortion . . . . . . . . . . . . . . . . . . 5–3
5.3.6.3
DAC Signal-to-Distortion + Noise . . . . . . . . . . 5–3
5.3.7
DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
5.3.8
Logic DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 5–4
5.3.9
Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
5.3.10
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
5.3.11
Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5.3.12
Flash Write Enable Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5.3.13
8-Ω Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5.4
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5.4.1
Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5.4.2
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5.5
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
A Programmable Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
iv
List of Illustrations
Figure
Title
Page
4–1 Primary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . . . 4–1
4–2 FS High Mode Primary Serial Communication Timing . . . . . . . . . . . . . . . . . . 4–2
4–3 FS Low Mode Primary Serial Communication Timing . . . . . . . . . . . . . . . . . . 4–2
4–4 Secondary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . 4–3
4–5 FS Output During Software Secondary Serial Communication Request
(FS High Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
4–6 FS Output During Software Secondary Serial Communication Request
(FS Low Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
5–1 Serial Communication Timing for FS High Mode . . . . . . . . . . . . . . . . . . . . . . 5–6
5–2 ADC Decimation Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
5–3 ADC Decimation Filter Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
5–4 DAC Interpolation Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
5–5 DAC Interpolation Filter Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
6–1 Functional Block of a Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6–2 Voice Channel Codec Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6–3 Data Channel Codec Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
List of Tables
Table
Title
Page
4–1 Least-Significant-Bit Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
v
vi
1 Introduction
The TLC320AD535 dual channel voice/data codec is a mixed-signal broadband connectivity device. The
TLC320AD535 is comprised of a two-channel codec and analog hybrid circuitry with two independent serial ports for
communication with the host processor and external resistors and capacitors for setting gain and filter poles. The
device also contains microphone bias and amplification, audio mixing capabilities in the voice channel,
programmable gain control, and three (SPKR_LEFT, SPKR_RIGHT, and MONOUT) speaker drivers.The device
operates with either a 5-V analog, a 5-V digital, and a 5-V monitor power supply or a 3.3-V analog, a 3.3-V digital,
and a 5-V monitor power supply or 5-V analog, 3.3-V digital, and 5-V monitor power supply. It is available in a single
64-pin PM (QFP) package.
1.1 Features
•
Analog, Digital, and Monitor Amp Power Supplies: 5 V or 3.3 V
•
Separate Software Power-Down Modes for Data and Voice Channels
•
Independent Voice and Data Channel Sample Rates up to 11.025 kHz
•
16-Bit Signal Processing
•
Dynamic Range of 80 dB in the Data and Voice Channels
•
Total Signal-to-Noise + Distortion of 77 dB for the ADCs
•
Total Signal-to-Noise + Distortion of 74 dB for the DACs
•
Programmable Gain Amplifiers
•
600-Ω TAPI Audio and Data Channel Drivers
•
60-Ω Headphone Driver With Programmable Gain Amplifier
•
8-Ω AT41 Differential Speaker Driver With Programmable Gain Amplifier
•
Maximum Microphone Bias of 5 mA at 2.5 V/1.5 V
•
Maximum Handset Reference of 2.5 mA at 2.5 V/1.5 V
•
Maximum Data Channel Reference of 10 mA at 2.5 V/1.5 V
•
5-V MVDD Power Reset Circuit
•
Flash Write Enable Circuit, for Writing the Flash Memory Device
•
Available in a 64-Pin PM (QFP) Package Operating From –40°C to 85°C
1–1
1.2 Functional Block Diagram
Data
Channel
Serial
Port
Data Channel
Codec
H
Y
B
R
I
D
A
M
P
Power
Reset
Circuit
DRVR
Control
Logic
Flash
Write
Enable
DRVR
Voice Channel
Codec
Voice
Channel
Serial
Port
1–2
BIAS/
AMPL
1.3 Voice Channel Codec Logic Diagram
–
+
TAPI_IN
TAPI Preamp
20/0 dB Gain
2.5 V/1.5 V
–
+
MIC_AUDIO
Mic Preamp
20/0 dB Gain
MIC_BIAS
M
I
X
E
R
2.5 V/1.5 V
HSRX_FB
HSRXM
HSRXP
16-Bit
ADC
+
2.5 V/1.5 V
Line_In PGA
12 to –36 dB
1.5 dB Noiseless Steps
31 Steps and Mute
Phantom Power
2.5 V/1.5 V @ 5 mA
–
+
–
–1
+
SPKR_LEFT
–
60-Ω Pwr Spkr Buffer
0 dB or Mute
( Same Polarity)
Handset RX (Hybrid)
+
SPKR_RIGHT
–
HS_REF
2.5 V/1.5 V
16-Bit
DAC
–
HSTX_OUT
HSTX_IN
2.5 V/1.5 V
Internal
HS_BUF
+
–
+
2.5 V/1.5 V
Handset TX (Hybrid)
+
–
Line_Out PGA
12 to –36 dB
1.5 dB Noiseless Steps
31 Steps and Mute
+
TAPI_OUT
–
600-Ω
Out Buffer
0 dB or Mute
600-Ω Handset Out Buffer
0 dB or Mute
1–3
1.4 Data Channel Codec Logic Diagram
DTRX_FB
DTRXM
DTRXP
–
+
–
+
16-Bit
ADC
Data (Hybrid)
DT_REF
DTTX_OUT
DTTX_IN
2.5 V/1.5 V
–
+
Data_In PGA
0/6/12/18 dB Gain
with Mute
2.5 V/1.5 V
2.5 V/1.5 V
@ 10 mA
Mon_Out PGA
0-3-6-9-12 dB Gain
with Mute
–1
16-Bit
DAC
–
M
U
X
+
Data (Hybrid)
MONOUTP
–
–
DT_BUF
+
+
2.5 V/1.5 V
0/–6/–12/–18 dB or Mute
600-Ω Data_Out PGA
8 Ω Speaker Buffer
0 dB or Mute
NC
NC
MONOUTP
MVDD
MONOUTM
MVSS
NC
FILT
MIC_BIAS
MIC_AUDIO
TEST1
TEST2
SPKR_RIGHT
SPKR_LEFT
TAPI_IN
TAPI_OUT
1.5 Terminal Assignments
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VSS
DAVDD
DREFP_DAC
DREFM_DAC
DAVSS
DREFP_ADC
DREFM_ADC
NC
DTRX_FB
DTRXM
DTRXP
DT_REF
DTTX_OUT
DTTX_IN
DT_BUF
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TLC320AD535C/I
FLSH_OUT
FLSH_IN
RESET
POR
DT_FS
DT_DOUT
DV SS
DVDD
DT_SCLK
DT_DIN
DT_MCLK
VC_DIN
VC_DOUT
VC_MCLK
VC_SCLK
VC_FS
1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC–Make no external connection
1–4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VAVDD
VREFP_ADC
VREFM_ADC
VAVSS
VREFP_DAC
VREFM_DAC
NC
HSRX_FB
HSRXM
HSRXP
HS_REF
HSTX_OUT
HSTX_IN
HS_BUF
NC
SI_SEL
MONOUTM
1.6 Ordering Information
TA
PACKAGE
PLASTIC QUAD FLATPACK (PM)
0°C to 70°C
TLC320AD535
–40°C to 85°C
TLC320AD535I
1.7 Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
I/O
DAVDD
DAVSS
2
I
Data channel analog power supply (5 V/3.3 V)
5
I
Data channel analog ground
DREFM_ADC
7
O
Data channel ADC voltage reference filter output. DREFM_ADC provides low-pass filtering for the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_ADC
and DREFP_ADC. The nominal DC voltage at this terminal is 0 V.
DREFM_DAC
4
O
Data channel DAC voltage reference filter output. DREFM_DAC provides low-pass filtering for the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_DAC
and DREFP_DAC. The nominal dc voltage at this terminal is 0 V.
DREFP_ADC
6
O
Data channel ADC voltage reference filter output. DREFP_ADC provides low-pass filtering for the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_ADC
and DREFP_ADC. The dc voltage at this terminal is 3.375 V at 5-V DAVDD supply and 2.25 V at 3.3-V DAVDD
supply.
DREFP_DAC
3
O
Data channel DAC voltage reference filter output. DREFP_DAC provides low-pass filtering for the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between DREFM_DAC
and DREFP_DAC. The dc voltage at this terminal is 3.375 V at 5-DAVDD supply and 2.25 V at 3.3-DAVDD supply.
DT_BUF
15
O
Data channel buffer amp analog output. DT_BUF is programmed for 0-dB gain or is muted using the control
registers. This output is normally fed to the DTTX_IN terminal through an input resistor.
DT_DIN
26
I
Data channel digital data input. DT_DIN handles DAC input data as well as control register programming
information during the data channel frame sync interval and is synchronized to DT_SCLK.
DT_DOUT
22
O
Data channel digital data output. Data channel ADC output bits are transmitted during the data channel frame
sync period that is synchronized to DT_SCLK. DT_DOUT is at high impedance when DT_FS is not activated.
DT_FS
21
O
Data channel serial port frame sync signal. DT_FS signals the beginning of transmit for ADC data and receiving
of DAC data in the data channel. This signal can be active high (FS high mode) or active low (FS low mode)
depending on the voltage applied to SI_SEL (See Section 4, Serial Communications for more details).
DT_MCLK
27
I
Data channel master clock input. All of the internal clocks for the data channel are derived from this clock.
DT_REF
12
O
Handset amplifier reference voltage. The voltage at this pin is set at 2.5 V for a 5-V DAVDD supply and 1.5 V for
a 3.3-V DAVDD supply. The maximum source current at this terminal is 2.5 mA.
9
O
Data channel receive path amplifier feedback node. DTRX_FB connects to the output of the data channel receive
path amplifier and allows a parallel resistor/capacitor to be placed in the amplifier feedback path for setting gain
and filter poles.
DTRXM
10
I
Data channel receive path amplifier analog inverting input
DTRXP
11
I
Data channel receive path amplifier analog noninverting input.
DT_SCLK
25
O
Data channel shift clock signal. This signal clocks serial data into DT_DIN and out of DT_DOUT during the data
channel frame-sync interval. DT_SCLK = DT_MCLK/2
DTTX_IN
14
I
Data channel transmit amplifier analog inverting input. This node is normally fed by the DT_BUF output through
an input resistor. The noninverting input of the amplifier is connected internally to 2.5 V for 5 V supply and 1.5
V for 3.3 V supply.
DTTX_OUT
13
O
Data channel transmit amplifier analog output
DVDD
24
I
Digital power supply (5 V/3.3 V).
DVSS
23
I
Digital ground
FILT
57
O
Bandgap filter node. FILT provides decoupling of the 3.375-V bandgap reference. The optimal capacitor value
is 0.1 µF (ceramic). This node should not be used as a voltage source.
DTRX_FB
1–5
1.7 Terminal Functions (Continued)
TERMINAL
NAME
NO.
DESCRIPTION
I/O
FLSH_IN
18
I
External logic input. When brought low FLSH_IN enables the FLSH_OUT output.
FLSH_OUT
17
O
Power output to write/erase flash EEPROM device (such as Intel 28F400B or AMD Am29F400). Outputs 5 V
(± 10%) at 45 mA maximum when FLSH_IN is brought low. FLSH_OUT does not go to a logic high state when
off. There is an internal NMOS pull down to maintain the specified voltage. An external pull down is not required.
HS_BUF
35
O
Handset buffer amplifier analog output. HS_BUF can be programmed for 0-dB gain or muted using the control
registers. This output is normally fed to the HSTX_IN terminal through an input resistor.
HS_REF
38
O
Handset amplifier reference voltage HS_REF is set at 2.5 V for 5-V supply and 1.5 V for 3.3-V supply. The
maximum source current at this terminal is 2.5 mA.
HSRX_FB
41
O
Feedback node for handset receive path amplifier. HSRX_FB is connected to the output of the handset receive
path amplifier and allows a parallel resistor/capacitor to be placed in the amplifier feedback path for setting gain
and filter poles.
HSRXM
40
I
Handset receive path amplifier analog inverting input
HSRXP
39
I
Handset receive path amplifier analog noninverting input
HSTX_IN
36
I
Handset transmit amplifier analog inverting input. This node is normally fed by the HSBUF output through an
input resistor. The noninverting input of the amplifier is connected internally to 2.5 V for 5 V supply and 1.5 V
for 3.3 V supply.
HSTX_OUT
37
O
Handset transmit amplifier analog output
MIC_AUDIO
55
I
Microphone preamplifier analog input. MIC_AUDIO can be programmed to add either 0-dB or 20-dB gain using
the control registers.
MIC_BIAS
56
O
Output that provides 2.5 V/1.5 V bias for electret microphone. The maximum source current at this terminal
is 5 mA.
MONOUTM
60
O
8 Ω monitor speaker amplifier analog output. MONOUTM is set for 0-dB gain or is muted using the control
registers.
MONOUTP
62
O
8 Ω monitor speaker amplifier analog output. MONOUTP is set for 0-dB gain or is muted using the control
registers.
MVDD
MVSS
61
I
Monitor amplifier supply (5 V/3.3 V)
59
I
Monitor amplifier ground
NC
All terminals marked NC should be left unconnected.
POR
20
O
Power on reset signal. POR remains low while the 5-V supply at MVDD is below its threshold voltage and for
40 ms after it rises above the reset threshold.
RESET
19
I
Codec device reset. RESET initializes all device internal registers to their default values. This signal is active
low.
SI_SEL
33
I
Serial interface mode select. When SI_SEL is tied to DVDD, the serial port is in FS high mode. When SI_SEL
is tied to DVSS, the serial port is in FS low mode (See Section 4, Serial Communications for more details).
SPKR_LEFT
51
O
Analog output from 60-Ω speaker line amplifier. SPKR_LEFT is set for 0-dB gain or is muted using the control
registers.
SPKR_RIGHT
52
O
Analog output from 60-Ω speaker line amplifier. SPKR_RIGHT is set for 0-dB gain or is muted using the control
registers.
TAPI_IN
50
I
Analog input to the TAPI (or sound card) preamplifier which can be programmed to add either 0 dB or 20 dB
gain via the control registers.
TAPI_OUT
49
O
TAPI buffer amplifier analog output. This 600-Ω amplifier is set for 0-dB gain or is muted using the control
registers.
TEST1
54
I/O
Test input/output port. TEST1 is for factory testing only and should be left unconnected.
TEST2
53
I/O
Test input/output port. TEST2 is for factory testing only and should be left unconnected.
VAVDD
VAVSS
48
I
Voice channel analog power supply (5 V/3.3 V)
45
I
Voice channel analog ground
VC_DIN
28
I
Voice channel digital data input. VC_DIN handles DAC input data as well as control register programming
information during the voice channel frame sync interval. VC_DIN is synchronized to VC_SCLK.
1–6
1.7 Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
VC_DOUT
29
O
Voice channel digital data output. Voice channel ADC output bits are transmitted during the voice channel frame
sync period synchronized to VC_SCLK. VC_DOUT is at high impedance when VC_FS is not activated.
VC_FS
32
O
Voice channel serial port frame sync signal. VC_FS signals the beginning of transmit for ADC data and receive
of DAC data in the voice channel. This signal can be active high (FS high mode) or active low (FS low mode)
depending on the voltage applied to SI_SEL (see Section 4, Serial Communication for more details).
VC_MCLK
30
I
Voice channel master clock input. All internal clocks for the voice channel are derived from this clock.
VC_SCLK
31
O
Voice channel shift clock signal. VC_SCLK clocks serial data into VC_DIN and out of VC_DOUT during the
voice channel frame-sync interval. VC_SCLK = VC_MCLK/2
VREFM_ADC
46
O
Voice channel ADC voltage reference filter output. VREFM_ADC provides low-pass filtering of the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between VREFM_ADC
and VREFP_ADC. The nominal dc voltage at this terminal is 0 V.
VREFM_DAC
43
O
Voice channel DAC voltage reference filter output. VREFM_DAC provides low-pass filtering of the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between VREFM_DAC
and VREFP_DAC. The nominal dc voltage at this terminal is 0 V.
VREFP_ADC
47
O
VREFP_DAC
44
O
VSS
1
I
Voice channel ADC voltage reference filter output. VREFP_ADC provides low-pass filtering the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between VREFM_ADC
and VREFP_ADC. The dc voltage at this terminal is 3.375 V with a 5-V VAVDD supply and 2.25 V with a 3.3-V
VAVDD supply.
Voice channel DAC voltage reference filter output. VREFP_DAC provides low-pass filtering the internal
bandgap reference. The optimal ceramic capacitor value is 0.1 µF, which is connected between VREFM_DAC
and VREFP_DAC. The dc voltage at this terminal is 3.375 V with a 5-V VAVDD supply and 2.25 V with a 3.3-V
VAVDD supply.
Internal substrate connection. VSS should be tied to either DAVSS or VAVSS for normal operation.
1–7
1–8
2 Functional Description
2.1 Device Requirements and System Overview
The TLC320AD535 device consists of two codec channels, a hybrid circuit with external resistors and capacitors for
setting gain and filter poles, two independent serial ports, and other miscellaneous logic functions.
2.2 Codec Functions
The codec portion of the TLC320AD535 device performs the functions required for two channels of analog-to-digital
conversion, digital-to-analog conversion, lowpass filtering, control of analog input and output gains, internal
oversampling coupled with internal decimation and interpolation, and two 16-bit serial port interfaces to the host
processor. The two serial ports operate independently and are capable of operating at different sample rates. The
maximum sample rate of either codec channel is 11.025 kHz.
2.3 Hybrid Functions
The hybrid circuitry in the data channel includes integrated amplifiers whose gains and filter pole frequencies are set
by external resistors and capacitors. This allows maximum flexibility to make adjustments for board variations and
international standards while providing integration of the function. The filter amplifier stages in the data channel are
followed by a programmable gain amplifier, which feeds 8-Ω differential speaker drivers for the AT41 call progress
monitor speakers. The monitor speaker driver can be programmed for 0-dB gain or muted through the control 2
register. The source for the monitor speaker input can be either the output of the amplified DAC output (Data_Out
PGA) or the ADC input signal through control register 1 (See Appendix A).
A 2.5 V/1.5 V reference voltage (DT_REF) is provided as a reference for the transformer. It is necessary to reference
to 2.5 V/1.5 V (rather than ground), since the amplifiers are powered off by single-rail supplies. DT_REF is 2.5 V when
DAVDD is 5 V and 1.5 V when DAVDD is 3.3 V.
2.4 Voice Channel Analog
The analog circuitry in the voice channel includes a microphone bias, which sources a maximum of 5 mA at 2.5 V/
1.5 V, and preamplifiers for the microphone, which can be selected for 0-dB or 20-dB gain. The device also has a
handset interface with receive and transmit amplifiers. These three inputs can be summed in any combination and
the result sent to a Line_In programmable gain amplifier (PGA) stage with gain range from 12 dB to –36 dB in 1.5
dB noiseless steps. This feeds the voice channel ADC. In the DAC path, the output of the DAC is sent to a Line-Out
PGA with gain range from 12 dB to –36 dB in 1.5 dB noiseless steps. This feeds both a 600-Ω TAPI output driver and
a 60-Ω mono speaker driver that can be muted or programmed for 0-dB gain. The time-out for noiseless gain change
or the maximum time the system can wait for a zero crossing of a signal before it will effect the gain change request
is approximately 9 ms.
2.5 Miscellaneous Logic and Other Circuitry
The logic functions include the circuitry required to implement two independent serial ports and control register
programming through secondary communication on those serial ports. There are five control registers that are
programmed during secondary communications from either the data channel serial port or the voice channel serial
port. These control registers set amplifier gains, choose multiplexer inputs, select loopback functions, and read the
ADC overflow flags. The device also includes a power-on reset (POR) circuit to monitor the 5-V MVDD power supply
in the system and provides a reset signal when the supply MVDD voltage drops below its threshold voltage. In addition,
there is a flash write enable (FWE) circuit that takes an external logic input and provides 40 mA of current to power
the write enable circuit of an external memory device. The flash write enable circuit is powered from the digital power
supply.
2–1
2–2
3 Codec Functional Description
3.1 Operating Frequencies
The TLC320AD535 is capable of supporting any sample rate up to the maximum sample rate of 11.025 kHz in either
the data channel or voice channel. The sample rate is set by the frequency of the codec master clock that is input
to the serial port for that channel.
The sampling (conversion) frequency is derived from the internally-generated codec master clock divider circuit by
the following equation:
fs
+ Sampling (conversion) frequency + ǒXX_MCLKń512Ǔ
XX_SCLK + XX_MCLKń2
(1)
Where XX_MCLK refers to either the voice channel or data channel codec clock (VC_MCLK or DT_MCLK) fed to
the codec externally by the clock rate divider circuit. The clock rate divider circuit divides the system master clock
to obtain the necessary clock frequency to feed the codecs.
The inverse of the sampling frequency is the conversion period. The sample rates of the voice and data channels
can be set independently by their respective codec master clocks. The two codec channels can be sampled at
different rates simultaneously.
3.2 ADC Signal Channel
The input signals are amplified and filtered by on-chip buffers before being applied to their respective ADC input. In
the case of the voice channel, inputs from a microphone input and the handset input may be summed together before
being amplified/attenuated by the ADC line PGA. The ADC converts the signal into discrete output digital words in
2s-complement format, corresponding to the analog signal value at the sampling time. These 16-bit digital words,
representing sampled values of the analog input signal, are sent to the host through the serial port interface for their
respective channels. If the ADC reaches its maximum value, a control register flag is set. This overflow bit resides
at D0 in the data channel control register 2 or the voice channel control register 5. These bits can only be read from
their respective serial ports, and the overflow flag is cleared only if it is read through the voice channel serial port,
and similarly for the data channel. The ADC and DAC conversions are synchronous and phase-locked.
3.3 DAC Signal Channel
The DAC receives the 16-bit data words (2s complement) from the host through the serial port interface for each
channel. The data is converted to analog voltages by their respective sigma-delta DACs comprised of a digital
interpolation filter and a digital modulator. The outputs of the DACs are each then passed to internal low pass filters
to complete the signal reconstruction resulting in an analog signal. Those analog signals are then buffered and
amplified by an output driver capable of driving the required load. The gain of these output amplifiers is programmed
by the
+codec control registers, as shown in Appendix A.
3.4 Sigma-Delta ADC
Each ADC is an oversampling sigma-delta modulator. The ADC provides high resolution and low noise performance
using oversampling techniques and the noise shaping advantages of sigma-delta modulators.
3.5 Decimation Filter
Each decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating with a
ratio equal to the oversampling ratio. The output of this filter is a 16-bit 2s-complement data word clocking at the
selected sample rate.
3–1
3.6 Sigma-Delta DAC
Each DAC is an oversampling sigma-delta modulator. The DAC performs high-resolution, low-noise digital-to-analog
conversion using oversampling sigma-delta techniques.
3.7 Interpolation Filter
Each interpolation filter resamples the digital data at a rate of N times the incoming sample rate, where N is the
oversampling ratio. The high-speed data output from this filter is then applied to the sigma-delta DAC.
3.8 Analog and Digital Loopbacks
The test capabilities include an analog loopback and digital loopback. The loopbacks provide a means of testing the
ADC/DAC channels and are used for in-circuit system-level tests. The loopback feeds the ADC output to the DAC
input on the IC for each individual channel. The analog loopback functions test only the codec portions of the device
and do not include the hybrid amplifiers.
Analog loopback loops the DAC output back into the ADC input of the same channel. Digital loopback loops the ADC
output back into the DAC input of the respective channel. Analog loopback is enabled by setting the D4 bit in the
control register 1 for the data channel or control register 3 for the voice channel. Digital loopback is enabled by setting
the D5 bit high in control register 1 for the data channel or control register 3 for the voice channel.
3.9 Software Power Down
The software power down resets all internal counters, but leaves the contents of the programmable control registers
unchanged for the selected channel. The device has separate and independent software power down bits for the
voice and data channels. The software power down feature is invoked by setting the D6 bit high in control register
1 for the data channel or setting the D6 bit in control register 3 for the voice channel. There is no hardware power
down function in the TLC320AD535.
3.10 Reset Circuit
This circuit monitors the 5-V MVDD power supply coming into the device from the bus and asserts an active low
power-on-reset ( POR) signal whenever this supply voltage drops below its threshold voltage. The reset signal
remains low while the supply voltage is below the threshold voltage. It remains low for 40 ms (nominal) after the supply
voltage has risen above the reset threshold voltage. Once the voltage rises above the threshold, an internal counter
is activated and holds the POR signal low for an additional 40 ms (nominal). The signal then goes high and remains
high as long as the MVDD supply remains in the acceptable voltage range. This circuit is, in effect, on initial power
up of the device and POR is held low until the supply voltage rises above the threshold. In addition, a reset is triggered
if a transient spike of sufficient magnitude and duration occurs. The supply must drop below the threshold voltage
for a period of time greater than the delay time shown in the following table (delay time, MVDD to reset). If a spike
occurs that drops below the threshold, but the supply voltage returns above the threshold within the delay time, POR
remains in the high state.
3–2
V(TO)
MVDD
0V
POR
40 ms
20 µs
Detection of Threshold
Crossing as MVDD
Goes High
20 µs
Detection of Threshold
Crossing as MVDD
Goes Low
PARAMETER
40 ms
Detection of Threshold
Crossing as MVDD Goes High
MIN
NOM
MAX
UNIT
Delay time, MVDD to reset
10
20
40
µs
Delay time reset pulse (POR)
20
40
80
ms
4.5
4.63
4.75
Threshold voltage V(TO)
5-V MVDD
V
3.11 Test Module
The test module serves the purpose of facilitating design verification testing and simplifying factory production testing.
There are two input/output terminals (TEST1 and TEST2) dedicated to implementing the test functions. The function
of these terminals is for factory self-test only, and no connection (NC) should be made to either of these terminals.
3–3
3–4
4 Serial Communications
DT_DOUT, DT_DIN, DT_SCLK, and DT_FS are the serial communication signals for the data channel serial port,
while VC_DOUT, VC_DIN, VC_SCLK, and VC_FS are the serial communication signals for the voice channel serial
port. The digital output data from the ADC is taken from DT_DOUT (or VC_DOUT). The digital input data for the DAC
is applied to DT_DIN (or VC_DIN). The synchronization clock for the serial communication data and the frame-sync
is taken from DT_SCLK and VC_SCLK for the data and voice channels, respectively. The frame-sync pulse which
signals the beginning of the ADC and DAC data transfer interval is taken from DT_FS and VC_FS for the data and
voice channels, respectively.
For signal data transmitted from the ADC or to the DAC, a primary serial communication is used. A secondary
communication reads or writes words to the control registers, which control both the options and the circuit
configurations of the device.
The purpose of primary and secondary communications is to allow conversion data and control data to be transferred
across the same serial port. A primary transfer is always dedicated to conversion data. A secondary transfer is used
to set up or read the control register values described in Appendix A, Programmable Register Set. A primary transfer
occurs for every conversion period. A secondary transfer occurs only when requested. Secondary serial
communication is requested by software - D0 of the primary data input to DT_DIN for the data channel serial port or
to VC_DIN for the voice channel serial port. A secondary request can be made for the voice channel without making
a secondary request for the data channel, or vice versa. Control registers 1 and 2 can only be written to or read from
the data channel serial port. Control registers 3 through 6 can only be written to or read from the voice channel serial
port.
4.1 Primary Serial Communication
Primary serial communication transmits and receives conversion signal data. The DAC word length is 15 bits and
the last bit of the primary 16-bit serial communication word is a control bit used to request secondary serial
communication. For all serial communications, the most significant bit is transferred first. For the 16-bit ADC word,
D15 is the most significant bit, and D0 is the least significant bit. For the 15-bit DAC data word in a primary
communication, D15 is the most significant bit, D1 is the least significant bit, and D0 is used for the secondary
communication request control. All digital data values are in 2s-complement data format. Refer to Figure 4–1.
XX_DIN
D15–D1
D0
D/A Data
Secondary
Communication Request
A/D Data
XX_DOUT
D15–D0
Figure 4–1. Primary Communication DIN and DOUT Data Format
4–1
4.1.1
FS High Mode Primary Communication Timing
There are two possible modes for serial data transfer. One mode is the FS high mode which is selected by tying the
SI_SEL pin to DVDD. Figure 4–2 shows the timing relationship for XX_SCLK, XX_FS, XX_DOUT and XX_DIN in a
primary communication for either the voice or data channel when in FS high mode. The timing sequence for this
operation is as follows:
1. XX_FS is brought high and remains high for one XX_SCLK period, then goes low.
2. A 16-bit word is transmitted from the ADC (DT_DOUT and VC_DOUT) and a 16-bit word is received for DAC
conversion (DT_DIN and VC_DIN).
XX_SCLK
XX_FS
XX_DIN
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XX_DOUT
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4–2. FS High Mode Primary Serial Communication Timing
4.1.2
FS Low Mode Primary Communication Timing
The second possible serial interface mode is the FS low mode, which is selected by tying the SI_SEL pin to DVSS.
This mode differs from the FS high mode in that the frame sync signal (FS) is active low, data transfer starts on the
falling edge of XX_FS, and XX_FS remains low throughout the data transfer. Figure 4–3 shows the timing relationship
for XX_SCLK, XX_FS, XX_DOUT and XX_DIN in a primary communication for either the voice or data channel when
in FS low mode. The timing sequence for this operation is as follows:
1. XX_FS is brought low by the TLC320AD535.
2. A 16-bit word is transmitted from the ADC (DT_DOUT and VC_DOUT) and a 16-bit word is received for DAC
conversion (DT_DIN and VC_DIN).
3. XX_FS is brought high signaling the end of the data transfer.
XX_SCLK
XX_FS
XX_DIN
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XX_DOUT
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4–3. FS Low Mode Primary Serial Communication Timing
4–2
4.2 Secondary Serial Communication
Secondary serial communication reads or writes 16-bit words that program both the options and the circuit
configurations of the device for either the voice channel or the data channel. Register programming always occurs
during secondary communication for that channel. Control registers 1 and 2 can only be written to or read from the
data channel serial port. Control registers 3 through 6 can only be written to or read from the voice channel serial port.
Four primary and secondary communication cycles are required to program the four voice channel registers. In the
same manner, two primary and secondary communication cycles are necessary to program the data channel control
registers. If the default value for a particular register is desired, then the register addressing can be omitted during
secondary communications. The NOOP (no operation) command addresses a pseudo-register, register 0, and no
register programming takes place during this secondary communication. This can be used for either the data channel
or the voice channel serial port.
During a secondary communication, a register is written to or read from. When writing a value to a register, the
DT_DIN (or VC_DIN) line contains the value to be written. The data returned on DT_DOUT (or VC_DOUT) is 00h.
The method for requesting a secondary communication is by asserting the least significant bit (D0) of DT_DIN (or
VC_DIN) high as shown in Table 4–1.
Table 4–1. Least-Significant-Bit Control Function
CONTROL BIT D0
CONTROL BIT FUNCTION
0
No secondary communication request
1
Secondary communication request
Figure 4–4 shows the data format XX_DIN and XX_DOUT during secondary communication.
Don’t Care
D15
XX_DIN
(Read)
––
––
1
R/W
D12 D11 D10
D9
D8
Register Address
D7–D0
Register Data
D15
XX_DIN
(Write)
XX_DOUT
(Read)
––
––
0
D12 D11 D10
D9
D8
D7–D0
AII 0
Register Data
D15–D8
D7–D0
AII 0
XX_DOUT
(Write)
D15–D0
Figure 4–4. Secondary Communication DIN and DOUT Data Format
4–3
4.2.1
FS High Mode Secondary Communication Timing
On the rising edge of SCLK, coinciding with the falling edge of FS for that channel, D15–D0 is input serially to DT_DIN
(or VC_DIN), and D15–D0 is output serially on DT_DOUT (or VC_DOUT). If a secondary communication request is
made, FS goes high again 128 SCLKs after the beginning of the primary frame to signal the beginning of the
secondary frame one SCLK period later. See Figure 4–5.
128 XX_SCLKs
P
S
P
P
XX_FS
XX_DIN
Data (D0=1)
Register R/W
Secondary Communication
Request
Data (D0=0)
No Secondary
Communication Request
ÎÎ
ÎÎ
Figure 4–5. FS Output During Software Secondary Serial Communication Request (FS High Mode)
4.2.2
FS Low Mode Secondary Communication Timing
On the falling edge of XX_FS for that channel, D15–D0 is input serially to XX_DIN and D15–D0 is output serially on
XX_DOUT. XX_FS remains low during the data transfer and then returns high. If a secondary communication request
is made, XX_FS goes low 128 SCLKs after the beginning of the primary frame to signal the beginning of the secondary
frame. See Figure 4–6.
128 XX_SCLKs
XX_FS
XX_DIN
P
S
P
Data (D0=1)
Register R/W
Data (D0=0)
Secondary Communication
Request
No Secondary
Communication Request
Figure 4–6. FS Output During Software Secondary Serial Communication Request (FS Low Mode)
4–4
5 Specifications
5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)†
Supply voltage range, DVDD, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output voltage range, all digital output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Input voltage range, all digital input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Case temperature for 10 seconds: PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
5.2 Recommended Operating Conditions
3.3-V supply
Supply voltage
voltage, DAVDD, VAVDD, MVDD, DVDD (see Note 2)
5-V supply
Analog
g signal
g
peak-to-peak input voltage
g {, DT_RXM,
_
, DT_RXP,
_
, MIC_AUDIO,
_
, TAPI_IN,
_ ,
HS_RXM, HS_RXP, VI(analog)
MIN
NOM
MAX
3
3.3
3.6
4.5
5
5.5
3.3-V supply
2
5-V supply
3
Differential output load resistance, TAPI_OUT, DT_BUF, HS_BUF, RL
Differential output load resistance, MONOUTP, MONOUTM, RL
Differential output load resistance, SPKR_RIGHT, SPKR_LEFT, RL
V
V
V
600
Ω
8
Ω
Ω
60
Input impedance, MIC_AUDIO
50
Master clock
kΩ
5.645
Load capacitance, CL
ADC or DAC conversion rate
Operating free-air temperature, TA
† Preamplifier gain set to 0 dB
NOTE 2: Voltages at analog inputs and outputs and xVDD are with respect to the xVSS terminal.
UNIT
MHz
20
pF
8 11.025
kHz
85
°C
–40
5.3 Electrical Characteristics Over Operating Free-Air Temperature Range,
DVDD = 5 V/3.3 V, xAVDD = 5 V/3.3 V, MVDD=5 V/3.3 V
5.3.1
Digital Inputs and Outputs, fs = 8 kHz, Outputs Not Loaded
PARAMETER
TEST CONDITIONS
IO = –360 µA
IO = 2 mA
MIN
TYP
MAX
UNIT
2.4
DVDD+0.5
V
DVSS–0.5
0.4
V
10
µA
10
µA
VOH
VOL
High-level output voltage, any digital output
IIH
IIL
High-level input current, any digital input
Ci
Input capacitance, any digital input
10
Co
Output capacitance, any digital output
10
II(lkg)
IOZ
Input leakage current, any digital input
30
µA
Output leakage current, any digital output
30
µA
Low-level output voltage, any digital output
Low-level input current, any digital input
VIH = 5 V
VIL = 0.6 V
pF
pF
5–1
5.3.2
ADC Channel, fs = 8 kHz (see Note 3)
PARAMETER
Filter gain relative to gain at 1020 Hz
TEST CONDITIONS
MIN
0 to 300 Hz
–0.5
TYP
0.2
300 Hz to 3 kHz
–0.5
0.25
3.3 kHz
–0.5
0.3
3.6 kHz
MAX
–3
4 kHz
–35
≥ 4.4 kHz
–74
UNIT
dB
NOTE 3: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The analog input test signal is a sine wave with
0 dB = 3 VI(PP) at 5-V supply and 0 dB = 2 VI(PP) at 3.3-V supply voltage as the reference level for the ADC analog input signal. The
–3-dB passband is 0 to 3600 Hz for an 8-kHz sample rate. This pass-band scales linearly with the sample rate.
5.3.3
ADC Dynamic Performance, fs = 8 kHz
5.3.3.1 ADC Signal-to-Noise (see Note 4)
PARAMETER
TEST CONDITIONS
VI = –1 dB
VI = –9 dB
Signal-to-noise ratio (SNR)
MIN
TYP
75
80
67
72
MAX
UNIT
dB
VI = –40 dB
36
36
NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referred to 2.5 V for 5-V supply and
1.5 V for 3.3-V supply. The output configuration is in a 3.3 V single ended mode.
5.3.3.2 ADC Signal-to-Distortion (see Note 4)
PARAMETER
Signal-to-total harmonic distortion (THD)
TEST CONDITIONS
VI = –3 dB
VI = –9 dB
MIN
TYP
73
78
77
82
MAX
UNIT
dB
VI = –40 dB
56
61
NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referred to 2.5 V for 5-V supply and
1.5 V for 3.3-V supply. The output configuration is in a 3.3 V single ended mode.
5.3.3.3 ADC Signal-to-Distortion + Noise (see Note 4)
PARAMETER
Signal-to-total harmonic distortion + noise (THD + N)
TEST CONDITIONS
VI = –3dB
VI = –9 dB
MIN
TYP
72
77
68
73
MAX
UNIT
dB
VI = –40 dB
37
42
NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output are referred to 2.5 V for 5-V supply and
1.5 V for 3.3-V supply. The output configuration is in a 3.3 V single ended mode.
5–2
5.3.4
ADC Characteristics
PARAMETER
VI(PP)
Peak-input voltage, TAPI_IN, MIC_AUDIO
TEST CONDITIONS
MIN
Intrachannel isolation
EG
Gain error
VI = –1 dB at 1020 kHz
EO(ADC)
ADC channel offset error including hybrid amplifiers
With a 0.1-µF capacitor between
CAP_D and DTRX_FB
EO(ADC)
ADC channel offset error including hybrid amplifiers
With no capacitor between CAP_D
and DTRX_FB
MAX
3
Dynamic range
Idle channel noise (on-chip reference)
UNIT
V
80
dB
85
dB
±0.6
dB
5
mV
20
mV
26
Channel delay
5.3.5
TYP
Preamp gain = 0 dB
75
17/fs
µV rms
s
DAC Channel, fs = 8 kHz (see Note 5)
PARAMETER
Filter gain relative to gain at 1020 Hz
TEST CONDITIONS
MIN
0 to 300 Hz
–0.5
TYP
0.3
300 Hz to 3 kHz
–0.25
0.25
3.3 kHz
–0.35
0.3
3.6 kHz
MAX
–3
4 kHz
–35
≥ 4.4 kHz
–70
UNIT
dB
NOTE 5: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the digital equivalent of a
sine wave (digital full scale = 0 dB). The –3 dB passband is 0 to 3600 Hz for an 8-kHz sample rate. This pass band scales linearly with
the sample rate.
5.3.6
DAC Dynamic Performance
5.3.6.1 DAC Signal-to-Noise (see Note 6)
PARAMETER
TEST CONDITIONS
VI = 0 dB
VI = –9 dB
Signal-to-noise ratio (SNR)
MIN
TYP
71
76
62
67
MAX
UNIT
dB
VI = –40 dB
31
36
NOTE 6: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. The output configuration is in a 3.3 V single ended mode.
5.3.6.2 DAC Signal-to-Distortion (see Note 6)
PARAMETER
Signal-to-total harmonic distortion (THD)
TEST CONDITIONS
VI = –3 dB
VI = –9 dB
MIN
TYP
78
83
70
75
MAX
UNIT
dB
VI = –40 dB
56
61
NOTE 6: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. The output configuration is in a 3.3 V single ended mode.
5.3.6.3 DAC Signal-to-Distortion + Noise (see Note 6)
PARAMETER
Signal-to-total harmonic distortion + noise (THD + N)
TEST CONDITIONS
VI = –3 dB
VI = –9 dB
MIN
TYP
69
74
63
68
MAX
UNIT
dB
VI = –40 dB
30
35
NOTE 6: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. The output configuration is in a 3.3 V single ended mode.
5–3
5.3.7
DAC Characteristics
PARAMETER
EG
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic range
79
dB
Intrachannel isolation
85
dB
Gain error
±0.7
VI = –1 dB at 1020 kHz
0 kHz to 4 kHz (see Note 7)
Idle channel narrow-band noise
dB
125
Channel delay
18/fs
25
VOO
Output offset voltage, HS_BUF, DT_BUF
DIN = All zeros
Analog output voltage
voltage, MONOUTP-MONOUTM
MONOUTP MONOUTM
Differential with respect to MVDD/2
and full
full-scale
scale digital input
(see Note 8)
5V
VO
Analog
g output voltage,
g TAPI_OUT, SPKR_LEFT,
SPKR_RIGHT
Single-ended
g
with respect to
HS_REF and full-scale digital input
5V
VO
µV rms
s
mV
–1.78
1.78
–1.2
1.2
–2
2
V
–1.5
1.5
V
V
3.3 V
3.3 V
NOTES: 7. The conversion rate is 8 kHz.
8. This amplifier should only be used in differential mode. Common mode: 2.5 V in 5 V supply and 1.5 V in 3.3 V supply.
5.3.8
Logic DC Electrical Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
V
VIL
VIH
Low-level input voltage
–0.3
1.5
High-level input voltage
2.4
DVDD+0.3
V
II(lkg)
IO(lkg)
Input leakage current
10
µA
10
µA
VOH
VOL
High-level output voltage at rated load current
2.4
DVDD–0.5
V
Low-level output voltage at rated load current
DVSS–0.5
0.4
V
5.3.9
Output leakage current
Power Supply Rejection (see Note 9)
PARAMETER
VDD1
VDD2
Supply-voltage rejection ratio, ADC channel DAVDD and VAVDD
VDD3
VDD4
Supply-voltage rejection ratio, DAC channel, DAVDD and VAVDD
Supply-voltage rejection ratio, ADC channel, DVDD
TEST CONDITIONS
MIN
TYP
fi = 0 to fs/2
fi = 0 to fs/2
50
fi = 0 to fs/2
fi = 0 to 30 kHz
50
MAX
40
UNIT
dB
Supply-voltage rejection ratio, DAC channel, DVDD
50
NOTE 9: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200 mV peak-to-peak signal
applied to the appropriate supply.
5.3.10 Power Supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
60
mA
IDD(analog)
IDD(digital)
Codec power supply current, analog (including hybrid and drivers) Operating
40
Codec power supply current, digital
Operating
10
IDD(monitor)
Power supply current, 8 Ω monitor speaker driver
Operating
135
5–4
mA
315
mA
5.3.11 Reset Circuit
PARAMETER
TEST CONDITIONS
MIN
TA= –40°C to 85°C for 5 V
I(SINK) = 1.2 mA
TYP
UNIT
4.75
V
0.3
V
0.4
V
Reset threshold voltage
VOL
VOH
POR output low-level voltage
td(RPD)
td(RDD)
POR low delay time after threshold exceeded
20
40
80
ms
Delay time after threshold crossed before POR activates
10
20
40
µs
POR output low-level voltage
I(SINK) = 3.2 mA
I = –500 µA
POR output high-level voltage
4.50
MAX
V(TO)
VOL
0.8 DVDD
V
5.3.12 Flash Write Enable Circuit
PARAMETER
VOH(FLSH
OH(FLSH_OUT)
OUT)
Output high-level
high level voltage,
voltage FLSH
FLSH_OUT
OUT
VOL(FLSH_OUT)
Output low-level voltage, FLSH_OUT
IO(FLSH_OUT)
O(FLSH OUT)
Output
Out
ut current,
current FLSH_OUT
FLSH OUT
MIN
TYP
MAX
FLSH_IN low (5 V supply)
TEST CONDITIONS
4.5
5
5.5
FLSH_IN low (3.3 V supply)
2.5
3
3.5
FLSH_IN high
0
FLSH_IN low (5 V supply)
40
FLSH_IN low (3.3 V supply)
25
UNIT
V
1.5
V
45
mA
mA
5.3.13 8-Ω Drive
PARAMETER
TEST CONDITIONS
MIN
Output gain when PGA gain is mute
TYP
MAX
UNIT
–96
–12 dB (input)
Output gain when PGA gain is 0 dB
Output gain when PGA gain is 12 dB
–1.5
0.7
1.5
10.5
12.5
13.5
TYP
MAX
dB
5.4 Timing Characteristics (see Parameter Measurement Information)
5.4.1
Timing Requirements
PARAMETER
MIN
td1
tsu1
Delay time, XX_SCLK↑ to XX_FS↓
th1
td3
Hold time, XX_DIN, after XX_SCLK high
20
ns
Delay time, XX_MCLK↓ to XX_SCLK↑
50
ns
twH
twL
Pulse duration, XX_MCLK high
32
ns
Pulse duration, XX_MCLK low
20
ns
tpW
RESET input pulse width
10MCLKS
ns
5.4.2
0
UNIT
Setup time, XX_DIN, before XX_SCLK low
25
ns
ns
Switching Characteristics
PARAMETER
td2
ten1
Delay time, XX_SLCK↑ to XX_DOUT
tdis1
Disable time, XX_FS↑ to XX_DOUT Hi-Z
Enable time, XX_FS↓ to XX_DOUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20
CL = 20 pF
25
ns
20
5–5
5.5 Parameter Measurement Information
twH
XX_MCLK
td3
twL
XX_SCLK
td1
XX_FS
tdis1
td2
D15
XX_DOUT
ten1
D14
tsu1
XX_DIN
D15
D14
th1
Figure 5–1. Serial Communication Timing for FS High Mode
0
–20
Attenuation – dB
–40
–60
–80
–100
– 120
0.8
1.6
2.4
3.2
4
4.8
fI – Input Frequency – kHz
5.6
Figure 5–2. ADC Decimation Filter Response
5–6
6.4
7.2
0.8
0.6
Attenuation – dB
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0.4
0.8
1.2
1.6
2
2.4
fI – Input Frequency – kHz
2.8
3.2
Figure 5–3. ADC Decimation Filter Passband Ripple
0
–20
Attenuation – dB
–40
–60
–80
–100
– 120
0.8
1.6
2.4
3.2
4
4.8
fI – Input Frequency – kHz
5.6
6.4
7.2
Figure 5–4. DAC Interpolation Filter Response
5–7
0.8
0.6
Attenuation – dB
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0.4
0.8
1.2
1.6
2
2.4
fI – Input Frequency – kHz
2.8
Figure 5–5. DAC Interpolation Filter Passband Ripple
5–8
3.2
6 Application Information
Data
Channel
Serial
Port
Data Channel
Codec
H
Y
B
R
I
D
Matching
Network
POTS
A
M
P
Power
Reset
Circuit
AT41
SPKR
DRVR
Control
Logic
Headset I/F
Flash
Write
Enable
SPKR
DRVR
Voice Channel
Codec
Voice
Channel
Serial
Port
TAPI I/F
BIAS/
AMPL
MIC
Figure 6–1. Functional Block of a Typical Application
6–1
–
TAPI_IN
+
TAPI Preamp
2.5 V/1.5 V 20/0 dB Gain
Voice Channel Codec
–
MIC_AUDIO
0.33 µF
M
I
X
E
R
+
Mic Preamp
2.5 V/1.5 V 20/0 dB Gain
2.2 kΩ
†
Phantom Power
2.5 V/1.5 V @ 5 mA
16-Bit
ADC
+
2.5 V/1.5 V
Line_In PGA 12 to –36 dB
1.5 dB Noiseless Steps
31 Steps and Mute
MIC_BIAS
HSRX_FB
–
–1
+
†
SPKR_LEFT
–
HSRXM
From
Hand Set
60 Ω Pwr Spkr Buffer
0 dB or Mute
( Same Polarity)
–
†
†
HSRXP
+
Handset RX (Hybrid)
†
†
+
†
16-Bit
DAC
–
2.5 V/1.5 V
HSTX_OUT
HSTX_IN
SPKR_RIGHT
–
2.5 V/1.5 V
Line_Out PGA 12 to –36 dB
1.5 dB Noiseless Steps
31 Steps and Mute
†
†
+
TAPI_OUT
–
600 Ω TPI Out Buffer
0 dB or Mute
–
+
HS_BUF
Handset TX (Hybrid)
2.5 V/1.5 V
Internal
+
–
600 Ω Handset Out Buffer
0 dB or Mute
† Required to meet communication standards
Figure 6–2. Voice Channel Codec Typical Application
6–2
2.2 µF
+
HS_REF
†
2.2 µF
2.2 µF
†
T1
Primary
(Line)
†
DTRXM
–
†
†
DTRXP
†
–
+
†
16-Bit
ADC
+
Data (Hybrid)
†
2.5 V/1.5 V
Data_In PGA
0/6/12/18 dB Gain
With Mute
Mon_Out PGA
0-3-6-9-12 dB Gain
with Mute
–1
DTREF (2.5 V @ 10 mA)
16-Bit
DAC
DTTX_OUT
†
DTTX_IN
†
–
M
U
X
+
2.5 V/1.5 V
†
MONOUTP
AT41
–
+
–
Data (Hybrid)
+
2.5 V/1.5 V
8 Ω Speaker Buffer
0 dB or Mute
DT_BUF
MONOUTM
+
–
2.5 V/1.5 V
0/-6/-12/-18 dB or Mute
600 Ω Data_Out PGA
† Required to meet communication standards
Figure 6–3. Data Channel Codec Typical Application
6–3
6–4
Appendix A
Programmable Register Set
Bits D12–D8 in a secondary serial communication comprise the address of the register that is written with data carried
in bits D7–D0. D13 determines a read or write cycle to the addressed register. When low (0), a write cycle is selected.
Table A–1 shows the register map.
Table A–1. Register Map
REGISTER NO.
D15
D14
D13
D12
D11
D10
D9
D8
REGISTER NAME
0
0
0
R/W
0
0
0
0
0
No operation
1
0
0
R/W
0
0
0
0
1
Control 1
2
0
0
R/W
0
0
0
1
0
Control 2
3
0
0
R/W
0
0
0
1
1
Control 3
4
0
0
R/W
0
0
1
0
0
Control 4
5
0
0
R/W
0
0
1
0
1
Control 5
6
0
0
R/W
0
0
1
1
0
Control 6
Table A–2. Control Register 1, Data Channel Control
D7
D6
D5
D4†
D3
D2
D1
D0
1
—
—
0
—
—
—
—
Software reset for data channel asserted
0
—
—
0
—
—
—
—
Software reset for data channel not asserted
—
1
—
0
—
—
—
—
S/W power down for data channel enabled
—
0
—
0
—
—
—
—
S/W power down for data channel disabled
—
—
1
0
—
—
—
—
Data channel digital loopback asserted
—
—
0
0
—
—
—
—
Data channel digital loopback not asserted
—
—
—
0
1
—
—
—
Select data_in PGA for monitor amp input
—
—
—
0
0
—
—
—
Select DAC output for monitor amp input
—
—
—
0
—
1
—
1
Monitor amp PGA gain = 12 dB
—
—
—
0
—
1
0
Monitor amp PGA gain = 9 dB
—
—
—
0
—
0
1
1
Monitor amp PGA gain = 6 dB
—
—
—
0
—
0
1
0
Monitor amp PGA gain = 3 dB
—
—
—
0
—
0
0
1
Monitor amp PGA gain = 0 dB
—
—
—
0
† D4 = reserved
Default value: 00000000
—
0
0
0
Monitor amp PGA gain = mute
DESCRIPTION
A–1
Table A–3. Control Register 2, Data Channel Control
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
1
0
0
—
—
—
—
—
Data in (DTRX) PGA gain = mute
0
1
1
—
—
—
—
—
Data in (DTRX) PGA gain = 18 dB
0
1
0
—
—
—
—
—
Data in (DTRX) PGA gain = 12 dB
0
0
1
—
—
—
—
—
Data in (DTRX) PGA gain = 6 dB
0
0
0
—
—
—
—
—
Data in (DTRX) PGA gain = 0 dB
—
—
—
1
0
0
—
—
DAC data out PGA gain = mute
—
—
—
0
1
1
—
—
DAC data out PGA gain = –18 dB
—
—
—
0
1
0
—
—
DAC data out PGA gain = –12 dB
—
—
—
0
0
1
—
—
DAC data out PGA gain = –6 dB
—
—
—
0
0
0
—
—
DAC data out PGA gain = 0 dB
—
—
—
—
—
—
1
—
8 ohm monitor speaker driver gain = 0 dB
—
—
—
—
—
—
0
—
8 ohm monitor speaker driver gain = mute
—
—
—
—
—
—
—
X
Data channel ADC overflow indicator: ← 1 = overflow
Default value: 00000000
Table A–4. Control Register 3, Voice Channel Control
D7
D6
D5
D4
D3
D2
D1
D0
1
—
—
—
—
—
—
—
Voice channel software reset
0
—
—
—
—
—
—
—
Voice channel software reset not asserted
—
1
—
—
—
—
—
—
Software power down for voice channel enabled
—
0
—
—
—
—
—
—
Software power down for voice channel disabled
—
—
1
—
—
—
—
—
Voice channel digital loopback
—
—
0
—
—
—
—
—
Voice channel digital loopback not asserted
—
—
—
1
—
—
—
—
Voice channel digital loopback
—
—
—
0
—
—
—
—
Voice channel digital loopback not asserted
—
—
—
—
1
—
—
—
TAPI preamp seleted for ADC input
—
—
—
—
0
—
—
—
TAPI preamp not selected for ADC input
—
—
—
—
—
1
—
—
Microphone preamp selected for ADC input
—
—
—
—
—
0
—
—
Microphone preamp not selected for ADC input
—
—
—
—
—
—
1
—
Handset preamp not selected for ADC input
—
—
—
—
—
—
0
—
Handset preamp selected for ADC input
—
—
—
—
—
—
—
1
TAPI output buffer gain = mute
—
—
—
—
—
—
—
0
TAPI output buffer gain = 0 dB
Default value: 00000000
A–2
DESCRIPTION
Table A–5. Control Register 4, Voice Channel Control
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
1
—
—
—
—
—
—
—
TAPI_IN preamp gain = 20 dB
0
—
—
—
—
—
—
—
TAPI preamp gain = 0 dB
—
1
—
—
—
—
—
—
Microphone preamp gain = 20 dB
—
0
—
—
—
—
—
—
Microphone preamp gain = 0 dB
—
—
1
1
0
0
0
0
Voice ADC input PGA gain = mute
—
—
1
0
0
0
0
1
Voice ADC input PGA gain = 12 dB
—
—
1
0
0
0
0
0
Voice ADC input PGA gain = 10.5 dB
—
—
0
1
1
1
1
1
Voice ADC input PGA gain = 9 dB
—
—
0
1
1
1
1
0
Voice ADC input PGA gain = 7.5 dB
—
—
0
1
1
1
0
1
Voice ADC input PGA gain = 6 dB
—
—
0
1
1
1
0
0
Voice ADC input PGA gain = 4.5 dB
—
—
0
1
1
0
1
1
Voice ADC input PGA gain = 3 dB
—
—
0
1
1
0
1
0
Voice ADC input PGA gain = 1.5 dB
—
—
0
1
1
0
0
1
Voice ADC input PGA gain = 0 dB
—
—
0
1
1
0
0
0
Voice ADC input PGA gain = –1.5 dB
—
—
0
1
0
1
1
1
Voice ADC input PGA gain = –3 dB
—
—
0
1
0
1
1
0
Voice ADC input PGA gain = –4.5 dB
—
—
0
1
0
1
0
1
Voice ADC input PGA gain = –6 dB
—
—
0
1
0
1
0
0
Voice ADC input PGA gain = –7.5 dB
—
—
0
1
0
0
1
1
Voice ADC input PGA gain = –9 dB
—
—
0
1
0
0
1
0
Voice ADC input PGA gain = –10.5 dB
—
—
0
1
0
0
0
1
Voice ADC input PGA gain = –12 dB
—
—
0
1
0
0
0
0
Voice ADC input PGA gain = –13.5 dB
—
—
0
0
1
1
1
1
Voice ADC input PGA gain = –15 dB
—
—
0
0
1
1
1
0
Voice ADC input PGA gain = –16.5 dB
—
—
0
0
1
1
0
1
Voice ADC input PGA gain = –18 dB
—
—
0
0
1
1
0
0
Voice ADC input PGA gain = –19.5 dB
—
—
0
0
1
0
1
1
Voice ADC input PGA gain = –21 dB
—
—
0
0
1
0
1
0
Voice ADC input PGA gain = –22.5 dB
—
—
0
0
1
0
0
1
Voice ADC input PGA gain = –24 dB
—
—
0
0
1
0
0
0
Voice ADC input PGA gain = –25.5 dB
—
—
0
0
0
1
1
1
Voice ADC input PGA gain = –27 dB
—
—
0
0
0
1
1
0
Voice ADC input PGA gain = –28.5 dB
—
—
0
0
0
1
0
1
Voice ADC input PGA gain = –30 dB
—
—
0
0
0
1
0
0
Voice ADC input PGA gain = –31.5 dB
—
—
0
0
0
0
1
1
Voice ADC input PGA gain = –33 dB
—
—
0
0
0
0
1
0
Voice ADC input PGA gain = –34.5 dB
—
—
0
0
0
0
0
1
Voice ADC input PGA gain = –36 dB
—
—
0
0
0
0
0
0
Voice ADC input PGA gain = 0 dB
Default value: 00000000
A–3
Table A–6. Control Register 5, Voice Channel Control
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
1
1
0
0
0
0
—
—
Voice DAC output PGA gain = mute
1
0
0
0
0
1
—
—
Voice DAC output PGA gain = 12 dB
1
0
0
0
0
0
—
—
Voice DAC output PGA gain = 10.5 dB
0
1
1
1
1
1
—
—
Voice DAC output PGA gain = 9 dB
0
1
1
1
1
0
—
—
Voice DAC output PGA gain = 7.5 dB
0
1
1
1
0
1
—
—
Voice DAC output PGA gain = 6 dB
0
1
1
1
0
0
—
—
Voice DAC output PGA gain = 4.5 dB
0
1
1
0
1
1
—
—
Voice DAC output PGA gain = 3 dB
0
1
1
0
1
0
—
—
Voice DAC output PGA gain = 1.5 dB
0
1
1
0
0
1
—
—
Voice DAC output PGA gain = 0 dB
0
1
1
0
0
0
—
—
Voice DAC output PGA gain = –1.5 dB
0
1
0
1
1
1
—
—
Voice DAC output PGA gain = –3 dB
0
1
0
1
1
0
—
—
Voice DAC output PGA gain = –4.5 dB
0
1
0
1
0
1
—
—
Voice DAC output PGA gain = –6 dB
0
1
0
1
0
0
—
—
Voice DAC output PGA gain = –7.5 dB
0
1
0
0
1
1
—
—
Voice DAC output PGA gain = –9 dB
0
1
0
0
1
0
—
—
Voice DAC output PGA gain = –10.5 dB
0
1
0
0
0
1
—
—
Voice DAC output PGA gain = –12 dB
0
1
0
0
0
0
—
—
Voice DAC output PGA gain = –13.5 dB
0
0
1
1
1
1
—
—
Voice DAC output PGA gain = –15 dB
0
0
1
1
1
0
—
—
Voice DAC output PGA gain = –16.5 dB
0
0
1
1
0
1
—
—
Voice DAC output PGA gain = –18 dB
0
0
1
1
0
0
—
—
Voice DAC output PGA gain = –19.5 dB
0
0
1
0
1
1
—
—
Voice DAC output PGA gain = –21 dB
0
0
1
0
0
1
—
—
Voice DAC output PGA gain = –24 dB
0
0
1
0
0
0
—
—
Voice DAC output PGA gain = –25.5 dB
0
0
0
1
1
1
—
—
Voice DAC output PGA gain = –27 dB
0
0
0
1
1
0
—
—
Voice DAC output PGA gain = –28.5 dB
0
0
0
1
0
1
—
—
Voice DAC output PGA gain = –30 dB
0
0
0
1
0
0
—
—
Voice DAC output PGA gain = –31.5 dB
0
0
0
0
1
1
—
—
Voice DAC output PGA gain = –33 dB
0
0
0
0
1
0
—
—
Voice DAC output PGA gain = –34.5 dB
0
0
0
0
0
1
—
—
Voice DAC output PGA gain = –36 dB
0
0
0
0
0
0
—
—
Voice DAC output PGA gain = 0 dB
—
—
—
—
—
—
1
—
60 Ω Spkr_L/R buffer gain = 0 dB
—
—
—
—
—
—
0
—
60 Ω Spkr_L/R buffer gain = mute
—
—
—
—
—
—
—
X
Voice channel ADC overflow: 1 = overflow
Default value: 00000000
Table A–7. Control Register 6, Voice Channel Control
D7
D6
D5
D4
D3
D2
D1
D0
1
—
—
—
—
—
—
—
Handset out buffer gain = mute
0
—
—
—
—
—
—
—
Handset out buffer gain = 0 dB
—
X
X
X
X
X
X
X
Reserved
Default value: 00000000
A–4
DESCRIPTION
Appendix B
Mechanical Data
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
10,20
SQ
9,80
12,20
SQ
11,80
Gage Plane
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
1,60 MAX
0,08
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
B–1
B–2
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