MC74VHC1G14 Single Schmitt−Trigger Inverter The MC74VHC1G14 is a single gate CMOS Schmitt−trigger inverter fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The MC74VHC1G14 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1G14 to be used to interface 5 V circuits to 3 V circuits. The MC74VHC1G14 can be used to enhance noise immunity or to square up slowly changing waveforms. • • • • • • • High Speed: tPD = 4 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25°C MARKING DIAGRAMS SC70−5/SC−88A/SOT−353 DF SUFFIX CASE 419A Power Down Protection Provided on Inputs Chip Complexity: FETs = 101 Pb−Free Packages are Available 1 SOT23−5/TSOP−5/SC59−5 DT SUFFIX CASE 483 VA M G IN A 2 GND 3 VA M G G 5 Pin and Function Compatible with Other Standard Logic Families 1 Pin 1 5 Balanced Propagation Delays NC VA M G G M Features http://onsemi.com 5 VCC 4 OUT Y 1 Pin 1 = Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. PIN ASSIGNMENT 1 Figure 1. Pinout (Top View) IN A 1 NC 2 IN A 3 GND 4 OUT Y 5 VCC FUNCTION TABLE OUT Y Figure 2. Logic Symbol A Input Y Output L H H L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 17 1 Publication Order Number: MC74VHC1G14/D MC74VHC1G14 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage −0.5 to )7.0 V VIN DC Input Voltage −0.5 to +7.0 V −0.5 to VCC )0.5 V VOUT DC Output Voltage IIK DC Input Diode Current −20 mA IOK DC Output Diode Current $20 mA IOUT DC Output Sink Current $12.5 mA ICC DC Supply Current per Supply Pin $25 mA *65 to )150 °C 260 °C TSTG Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature Under Bias qJA Thermal Resistance PD Power Dissipation in Still Air at 85°C MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup )150 °C SC70−5/SC−88A (Note 1) TSOP−5 350 230 °C/W SC70−5/SC−88A TSOP−5 150 200 mW Level 1 Oxygen Index: 28 to 34 Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) u2000 u200 N/A V Above VCC and Below GND at 125°C (Note 5) $500 mA ESD Withstand Voltage Latchup Performance UL 94 V−0 @ 0.125 in Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage 2.0 5.5 V VIN DC Input Voltage 0.0 5.5 V DC Output Voltage 0.0 VCC V *55 )125 °C − − No Limit No Limit ns/V Operating Temperature Range VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Time, Years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 TJ = 80° C Time, Hours FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 90 ° C Junction Temperature °C NORMALIZED FAILURE RATE Device Junction Temperature versus Time to 0.1% Bond Failures TJ = 110° C Input Rise and Fall Time TJ = 120° C tr , tf TJ = 130° C TA TJ = 100° C VOUT 1 1 10 100 1000 TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 MC74VHC1G14 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions TA ≤ 85°C TA = 25°C VCC (V) Min Typ Max Min VT+ Positive Threshold Voltage 3.0 4.5 5.5 1.85 2.86 3.50 2.0 3.0 3.6 2.20 3.15 3.85 VT− Negative Threshold Voltage 3.0 4.5 5.5 0.9 1.35 1.65 1.5 2.3 2.9 1.65 2.46 3.05 0.9 1.35 1.65 VH Hysteresis Voltage 3.0 4.5 5.5 0.30 0.40 0.50 0.57 0.67 0.74 1.20 1.40 1.60 0.30 0.40 0.50 VIN ≤ VT − Min IOH = −50 mA 2.0 3.0 4.5 1.9 2.9 4.4 2.0 3.0 4.5 IOH = −4 mA IOH = −8 mA 3.0 4.5 2.58 3.94 VIN ≥ VT + Max IOL = 50 mA 2.0 3.0 4.5 IOL = 4 mA IOL = 8 mA VOH VOL Minimum High−Level Output Voltage Maximum Low−Level Output Voltage 0.0 0.0 0.0 Max −55 ≤ TA ≤ 125°C Min 2.20 3.15 3.85 Max Unit 2.20 3.15 3.85 V 0.9 1.35 1.65 1.20 1.40 1.60 0.30 0.40 0.50 V 1.20 1.40 1.60 V 1.9 2.9 4.4 1.9 2.9 4.4 V 2.48 3.80 2.34 3.66 V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 1.0 20 40 mA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns TA ≤ 85°C TA = 25°C Symbol Parameter tPLH, tPHL Maximum Propagation Delay, A to Y CIN Min Test Conditions −55 ≤ TA ≤ 125°C Typ Max Min Max Min Max Unit ns VCC = 3.3 ± 0.3 V CL = 15 pF CL = 50 pF 7.0 8.5 12.8 16.3 1.0 1.0 15.0 18.5 1.0 1.0 17.0 20.5 VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF 4.0 5.5 8.6 10.6 1.0 1.0 10.0 12.0 1.0 1.0 11.5 13.5 5 10 Maximum Input Capacitance 10 10 pF Typical @ 25°C, VCC = 5.0 V CPD 7.0 Power Dissipation Capacitance (Note 6) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 3 MC74VHC1G14 VCC A or B 50% GND tPLH Y tPHL 50% VCC Figure 4. Switching Waveforms OUTPUT INPUT CL* *Includes all probe and jig capacitance. A 1−MHz square input wave is recommended for propagation delay tests. Figure 5. Test Circuit ORDERING INFORMATION Device Package MC74VHC1G14DFT1 SC−88A/SOT−353 MC74VHC1G14DFT1G SC−88A/SOT−353 (Pb−Free) MC74VHC1G14DFT2 SC−88A/SOT−353 MC74VHC1G14DFT2G SC−88A/SOT−353 (Pb−Free) MC74VHC1G14DTT1 SOT−23/TSOP−5 MC74VHC1G14DTT1G SOT−23/TSOP−5 (Pb−Free) Shipping † 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC74VHC1G14 PACKAGE DIMENSIONS SC−88A, SOT−353, SC−70 CASE 419A−02 ISSUE J A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. G 5 4 −B− S 1 2 DIM A B C D G H J K N S 3 D 5 PL 0.2 (0.008) B M M N INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC −−− 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 J C K H SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC −−− 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 MC74VHC1G14 PACKAGE DIMENSIONS TSOP−5 CASE 483−02 ISSUE F NOTE 5 2X 0.10 T 2X 0.20 T NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X 0.20 C A B 5 1 4 2 3 M B S K L DETAIL Z G A DIM A B C D G H J K L M S DETAIL Z J C 0.05 SEATING PLANE H T MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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