IS31IO7328 MULTI-FUNCTION I/O DRIVER January 2012 GENERAL DESCRIPTION FEATURES The IS31IO7328 2-wire serial-interfaced peripheral features 8 I/O ports. Ports are divided into four push pull I/Os and four open-drain I/Os and transition detection. Any of the 8 I/O ports can be configured as an input or an output. All I/O ports configured as inputs are continuously monitored for state changes (transition _______ detection). State changes are indicated by the INT output. The interrupt is latched, allowing detection of transient changes. When the IS31IO7328 is subsequently read through the serial interface, any pending interrupt is cleared. The open-drain outputs are rated to sink 20mA at 0.22V headroom, and are capable of driving LEDs. ________ The RST input clears the serial interface, terminating any I2C communication to or from the IS31IO7328. The IS31IO7328 uses two address inputs to allow 2 I2C slave addresses. The slave address also determines the power-up logic state for the I/O ports. 400kHz I2C serial interface 2.4V to 5.5V operation 4 push-pull I/O ports 4 open-drain I/O ports, rated to 20mA sink current at 0.22V headroom Selectable I/O port power-up default logic states _______ INT output alerts change on inputs Low 0.3μA (Typ.) standby current -40°C to +125°C temperature range APPLICATIONS Cell phones Notebooks SAN/NAS Satellite radio Servers Automotive TYPICAL APPLICATION CIRCUIT Figure 1 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 Typical Application Circuit 1 IS31IO7328 OD3 AD SCL OD2 I2C Input Filter Control SDA I/O Ports OD1 OD0 PP3 PP2 PP1 PP0 INT Power-on RST Reset Figure 2 Functional Block Diagram Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 2 IS31IO7328 PIN CONFIGURATION Package Pin Configuration (Top View) QFN-16 AD 1 12 PP2 RST 2 11 PP1 INT 3 10 PP0 VCC 4 9 OD3 PIN DESCRIPTION No. 1 Pin AD Description Address Inputs. Select device slave address with AD. _________ 2 3 ________ RST _______ Reset Input, Active Low. Drive RST low to clear the 2-wire interface. _______ INT Interrupt Output, Active Low. INT is an open-drain output. 4 VCC Positive Supply Voltage. Bypass VDD to GND with a ceramic capacitor of at least 1μF. 5,14 GND Ground. 6~9 OD0~OD3 Open-Drain I/O Ports. 10~13 PP0~PP3 CMOS Push-Pull I/O Ports. 15 SCL I2C-Compatible Serial-Clock Input. 16 SDA I2C-Compatible Serial-Data I/O. Thermal Pad Connect to GND. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 3 IS31IO7328 ORDERING INFORMATION Industrial Range: -40°C to +125°C Order Part No. Package QTY/Reel IS31IO7328-QFLS4-TR QFN-16, Lead-free 2500 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 4 IS31IO7328 ABSOLUTE MAXIMUM RATINGS Supply voltage, VCC Voltage at any input pin ________ -0.3V ~ +6.0V -0.3V ~ VCC+0.3V -0.3V ~ +6.0V -0.3V ~ VCC+0.3V ±100mA 120mA 10mA 10mA _______ SCL, SDA, AD, RST, INT, OD0-OD3 PP0–PP3 PP source output current PP/OD sink current SDA sink current _______ INT sink current Continuous power dissipation (TA = 70°C) 16-Pin WQFN (Derate 29.0mW/°C over 70°C) Maximum junction temperature, TJMAX Storage temperature range, TSTG Operating temperature range, TA Solder information, vapor phase (60s) infrared (15s) 2.32W 150°C -65°C ~ +150°C −40°C ~ +125°C 215°C 220°C Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = 2.4V ~ 5.5V, unless otherwise noted. Typical values are at VCC = 3.3V, TA = 25°C. (Note 1) Symbol Parameter Condition Min. Typ. Unit 5.5 V VCC Supply voltage VPOR Power-on-reset voltage ISTB Standby current (Interface idle) SCL and SDA and other digital inputs at VCC 0.3 1.9 μA Supply current (Interface running) Input high-voltage, SDA, SCL, fSCL = 400kHz; other digital inputs at VCC 8 20 μA I+ VIH VIL IIH, IIL CIN VOL VOH VOLSDA _______ VOLINT 2.4 Max. VCC falling, TA = -40°C 2.35 VCC falling, TA = -20°C 2.3 1.4 ________ AD RST, OD0~OD3, Input low-voltage, SDA, SCL, V ________ AD RST, OD0~OD3, Input leakage current, SDA, ________ SCL, AD RST, OD0~OD3, PP0~PP3 Input capacitance, SDA, SCL, ________ AD, RST, OD0~OD3, PP0~PP3 Output low voltage, PP0~PP3, OD0~OD3 Output high voltage PP0~PP3 V 0.4 V +0.2 μA ________ SDA, SCL, AD, RST , OD0~OD3, PP0~PP3 at VDD or GND. -0.2 (Note3) 10 pF VCC = 2.5V, ISINK = 10mA 200 VCC = 3.3V, ISINK = 15mA 240 VCC = 5.0V, ISINK = 20mA 250 VCC = 2.5V, ISOURCE = 5mA VCC-316 VCC = 3.3V, ISOURCE = 5mA VCC-213 VCC = 5.0V, ISOURCE = 10mA VCC-289 mV mV Output Low-Voltage SDA ISINK = 6mA 180 mV _______ ISINK = 5mA 180 mV Output Low-Voltage INT Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 5 IS31IO7328 TIMING CHARACTERISTICS VCC = 2.4V ~ 5.5V, unless otherwise noted. Typical values are at VCC = 3.3V, TA = 25°C. (Note 3) Symbol Parameter Condition Min. Typ. Max. Unit 400 kHz fSCL Serial-Clock Frequency tBUF Bus Free Time Between a STOP and a START Condition 1.3 μs tHD, STA Hold Time (Repeated) START Condition 0.6 μs tSU, STA Repeated START Condition Setup Time 0.6 μs tSU, STO STOP Condition Setup Time 0.6 μs tHD, DAT Data Hold Time tSU, DAT Data Setup Time 100 ns tLOW SCL Clock Low Period 1.3 μs tHIGH SCL Clock High Period 0.7 μs 0.9 μs tR Rise Time of Both SDA and SCL Signals, Receiving (Note 4) 20 + 0.1Cb 300 ns tF Fall Time of Both SDA and SCL Signals, Receiving (Note 4) 20 + 0.1Cb 300 ns Fall Time of SDA Transmitting (Note 4) 20 + 0.1Cb 250 ns Pulse Width of Spike Suppressed (Note 5) 50 tF, TX tSP Cb Capacitive Load for Each Bus Line tW ________ ns 400 RST Pulse Width pF 500 ns 1 μs ________ tRST _______ RST Rising to START Condition Setup Time _______ PORT AND INTERRUPT I N T TIMING CHARACTERISTIC VDD = 2.4V ~ 5.5V, unless otherwise noted. Typical values are at VDD = 3.3V, TA = 25°C. (Note 3) Parameter Symbol Condition Min. Typ. Max. Unit 4 μs Port Output Data Valid Port Input Setup Time tPV CL≤ 100pF tPSU CL≤ 100pF 0 μs Port Input Hold Time tPH CL≤ 100pF 4 μs ———— I N T Input Data Valid Time tIV CL≤ 100pF 4 μs ———— tIR CL≤ 100pF 4 μs I N T Reset Delay Time from Acknowledge Note 1: All parameters are tested at TA = 25°C. Specifications over temperature are guaranteed by design. Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. Note 3: Guaranteed by design. Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7× VCC. Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 6 IS31IO7328 Table 1 Power Up Default State For I/O Ports Pin Connection Table 2 Port Power Up Default AD PP3 PP2 PP1 PP0 OD3 OD2 OD1 OD0 AD = GND 0 0 0 0 0 0 0 0 AD = VDD 1 1 1 1 Hi-Z Hi-Z Hi-Z Hi-Z Command Byte Register Command Byte Address Function Power-up Default Protocol 00h (Note 6) Input port A (OD0~OD3) XXXX R 01h (Note 6) Input port B (PP0~PP3) XXXX R 02h (Note 6) Output port A Refer to Table 1 R/W 03h (Note 6) Output port B Refer to Table 1 R/W 04h (Note 6,7) Port A configuration 0000 R/W 05h (Note 6,7) Port B configuration 0000 R/W 06h (Note 6) Port A interrupt control 0000 R/W 07h (Note 6) Port B interrupt control 0000 R/W Note 6: When reading or writing data from/to the port A/B, the 4 MSBs of the data are effective Note 7: When configuring the command byte registers with address 04 or 05, the LSBs of data have to be set to 0. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 7 IS31IO7328 Figure 3 2-Wire Serial Interface Timing Details Figure 4 START and STOP Conditions Figure 5 Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 Bit Transfer 8 IS31IO7328 DETAILED DESCRIPTION FUNCTIONAL OVERVIEW STANDBY MODE The IS31IO7328 is a Multi-function I/O driver operating from a 2.4V to 5.5V supply with four push-pull and four open-drain I/O ports. Each open-drain and push-pull port is rated to sink 20mA at 0.22V headroom, and the entire device is rated to sink 160mA at 0.22V headroom into all ports combined. The outputs drive loads connected to supplies up to +5.5V. When the serial interface is idle, the IS31IO7328 automatically enters standby mode, drawing minimal supply current. The IS31IO7328 is set to two I2C slave addresses using the address select inputs AD, and is accessed ________ over an I2C serial interface up to 400 kHz. The RST input clears the serial interface in case of a bus lockup, terminating any serial transaction to or from the IS31IO7328. The IS31IO7328 consists of input, output port registers, configuration registers and interrupt control register. All I/O ports offer latching transition detection when configured as inputs. All input ports are continuously monitored for changes. _______ A latching interrupt output, INT, is programmed to flag logic changes on ports used as inputs. Data changes _______ on any input port forces INT to a logic-low. Changing the I/O port level through the serial interface does not _______ cause an interrupt. The interrupt output INT is cleared successfully by reading the corresponding input/output ports. Ports default to logic-high or logic-low on power-up in groups of two (see Table 1). INITIAL POWER-UP On power-up, the transition detection logic is reset, _______ and INT is reset. The power-up default states of the 8 I/O ports are set according to the I2C slave address selection inputs, AD (see Table 1). For I/O ports used as inputs, ensure that the default states are logic-high so that the I/O ports power up in the high impedance state. POWER-ON RESET The IS31IO7328 contains an integral power-on-reset (POR) circuit that ensures all registers are reset to a known state on power-up. When VDD rises above VPOR (2.3V max), the POR circuit releases the registers and 2-wire interface for normal operation. When VDD drops to less than VPOR, the IS31IO7328 resets all register contents to the POR defaults. I/O PORT INPUT TRANSITION DETECTION All I/O ports configured as inputs are monitored for changes since the expander was last accessed through the serial interface. The open-drain interrupt _______ output, INT, activates when one of the port pins changes states and only when the pin is configured as an input. The interrupt deactivates when the input/output register is read. A pin configured as an output does not cause an interrupt. Each 8-bit port register is read independently; therefore, an interrupt caused by port A (OD0~OD3) is not cleared by a read of port B (PP0~PP3)’s register. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of that I/O does not match the content of output port register. The IS31IO7328 has interrupt control register to avoid false interrupt by setting the interrupt control register bit high firstly, when the I/O state is stable, clear the interrupt control register to enable the input transition detection function. ACCESSING THE IS31IO7328 SERIAL ADDRESSING The IS31IO7328 operates as a slave that sends and receives data through a 2-wire interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master, typically a microcontroller, initiates all data transfers to and from the IS31IO7328, and generates the SCL clock that synchronizes the data transfer (see Figure 3). SDA operates as both an input and an open-drain output. A pull up resistor, typically 4.7kΩ, is required on SDA. SCL operates only as an input. A pull up resistor, typically 4.7kΩ, is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a START condition sent by a master, followed by the IS31IO7328’s 7-bit slave addresses plus R/W bits, 1 or more data bytes, and finally a STOP condition (see Figure 4). ________ RST INPUT ________ The active-low RST input voids any I2C transaction involving the IS31IO7328, forcing the IS31IO7328 into the I2C STOP condition. A reset does not affect the interrupt output. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 9 IS31IO7328 START AND STOP CONDITIONS BIT TRANSFER Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, the master issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (see Figure 4). One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (Figure 5). Figure 6 1 SCL 2 SDA S 3 4 5 6 7 8 Slave Address 1 3 A 0 START CONDITION 2 Acknowledge 4 5 6 7 8 1 A Command Byte R/W ACKNOWLEDGE FROM SLAVE 2 3 4 Data Nibble ACKNOWLEDGE FROM SLAVE 5 6 7 8 0 0 0 0 A ACKNOWLEDGE FROM SLAVE Write 0 When Writing The Port INTERNAL WRITE TO PORT DATA OUT FROM PORT DATA VALID tPV Figure 7 Writing to the IS31IO7328 SCL 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 PORT I/O ACKNOWLEDGE FROM SN7328 SDA S 1 0 1 1 0 AD 0 0 Command Byte 1 A 0 1 1 0 AD S W Effective Data ACKNOWLEDGE FROM SN7328 ACKNOWLEDGE FROM SN7328 A 1 0 D7 A D6 D5 NO ACKNOWLEDGE FROM MASTER Ineffective Data D4 D3 D2 D1 D0 NA P R tPH PORT tIV tPSU tIR INT OUTPUT S=START CONDITION P=STOP CONDITION Figure 8 SHADED=SLAVE TRANSMISSION NA=NO ACKNOLEDGE Reading I/O Ports of IS31IO7328 Note: Data from/to IS31IO7328, only the 4 MSBs of the data are effective Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 10 IS31IO7328 SLAVE ADDRESS The IS31IO7328 has a 7-bit slave address. The 8th bit ____ following the 7-bit slave address is the R/W bit. Set this bit low for a write command and high for a read command. The complete slave address is: transmit one or more bytes of data. The IS31IO7328 acknowledges these subsequent bytes of data and updates the corresponding group’s ports with each new byte until the master issues a STOP condition (Figure 7). READING PORT REGISTERS To read the device data, the bus master must first send A6 A5 A4 A3 A2 A1 A0 1 0 1 1 0 AD 0 ____ the IS31IO7328 address with the R/W bit set to zero, followed by the command byte, which determines which register is accessed. After a restart, the bus master must then send the IS31IO7328 address with ____ DATA BUS TRANSACTION The command byte is the first byte to follow the 8-bit device slave address during a write transmission (see Table 2). The command byte is used to determine which of the following registers are written or read. ACKNOWLEDGE The acknowledge bit is a clocked 9th bit the recipient uses to acknowledge receipt of each byte of data (see Figure 6). Each byte transferred effectively requires 9bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the IS31IO7328, the device generates the acknowledge bit because the IS31IO7328 is the recipient. When the IS31IO7328 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. CONFIGURATION REGISTERS The configuration registers configure the directions of the I/O pins. Set the bit in the respective configuration register to enable the corresponding port as an input. Clear the bit in the configuration register to enable the corresponding port as an output. The 4 LSBs of the commend data should be set to 0. INTERRUPT CONTROL REGISTERS The interrupt control registers control the interrupt function of I/O ports when the I/O port used as input. Set the bit in the respective interrupt control register to disable the corresponding port’s interrupt function. Clear the bit in the interrupt control register to enable the corresponding port’s interrupt function. the R/W bit set to 1. Data from the register defined by the command byte is then sent from the IS31IO7328 to the master. The IS31IO7328 acknowledges the slave address, and _______ samples the ports during the acknowledge bit. INT desserts during the slave address acknowledge. When the master reads one byte from the I/O ports of the IS31IO7328 and subsequently issues a STOP condition (Figure 8), the IS31IO7328 transmits the current port data, clears the change flags, and resets _______ the transition detection. INT desserts during the slave acknowledge. The new snapshot data is the current port data transmitted to the master, and therefore, port changes occurring during the transmission are detected. PORT OUTPUT SIGNAL-LEVEL TRANSLATION The open-drain output architecture allows for level translation to higher or lower voltages than the IS31IO7328’s supply. Each of the push-pull output ports has protection diodes to V+ and GND. When a port output is driven to a voltage higher than V+ or lower than GND, the appropriate protection diode clamps the output to a diode drop above V+ or below GND. When the IS31IO7328 is powered down (V+ = 0V), every output port’s protection diodes to V+ and GND continue to appear as a diode clamp from each output to GND (Figure 9). Each of the I/O ports OD0~OD3 has a protection diode to GND (Figure 10). When a port is driven to a voltage lower than GND, the protection diode clamps the port to a diode drop below GND. To obtain a high voltage, Open-Drain I/O Ports should connect an resistance to VDD (Figure 10). WRITING TO PORT REGISTERS Transmit data to the IS31IO7328 by sending the device slave address and setting the LSB to a logic zero. The command byte is sent after the address and determines which registers receive the data following the command byte. A write to either output port groups of the IS31IO7328 starts with the master transmitting the group’s slave ____ address with the R/W bit set low. The master can now Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 Figure 9 IS31IO7328 Push-Pull I/O Ports Structure 11 IS31IO7328 VDD 100k VCC OD0 OD1 IS31IO7328 OD2 OD3 Figure 11 Figure 10 Driving LEDs with OD Ports IS31IO7328 Open-Drain I/O Ports Structure DRIVING LEDS In the case that an OD output is used to drive an LED, a 100kΩ pull-up resistor should be used to prevent the output from floating while the LED is off. An OD port which is left floating may experience a slight increase in input leakage current due to the input structure of the IO port. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 12 IS31IO7328 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 12 Classification Profile Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 13 IS31IO7328 TAPE AND REEL INFORMATION Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 14 IS31IO7328 PACKAGE INFORMATION QFN-16 Note: All dimensions in millimeters unless otherwise stated. Integrated Silicon Solution, Inc. – www.issi.com Rev.A, 12/27/2011 15