FDMF3030 — Extra-Small, High-Performance, High-Frequency, DrMOS Module Benefits Description Ultra-Compact 6x6mm PQFN, 72% Space-Saving Compared to Conventional Discrete Solutions Fully Optimized for System Efficiency The DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET-plusdriver, power-stage solution for high-current, highfrequency, synchronous buck, DC-DC applications. The FDMF3030 integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact, 6x6mm package. Clean-Switching Waveforms with Minimal Ringing High-Current Handling Features Over 93% Peak-Efficiency Thermal Warning Flag for Over-Temperature Condition Driver Output Disable Function (DISB# Pin) Fairchild PowerTrench® Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing Fairchild SyncFET™ Technology (Integrated Schottky Diode) in Low-Side MOSFET High-Current Handling: 50A High-Performance PQFN Copper-Clip Package 3-State 5V PWM Input Driver Automatic Diode Emulation (Skip Mode) Enabled through ZCD_EN# Input Internal Pull-Up and Pull-Down for ZCD_EN# and DISB# Inputs, Respectively With an integrated approach, the complete switching power stage is optimized with regard to driver and MOSFET dynamic performance, system inductance, and power MOSFET RDS(ON). The FDMF3030 uses ® Fairchild's high-performance PowerTrench MOSFET technology, which dramatically reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications. A driver IC with reduced dead times and propagation delays further enhances performance. A thermal warning function indicates a potential over-temperature situation. The FDMF3030 also incorporates a ZeroCross Detect (ZCD_EN# pin) for improved light-load efficiency and provides a 3-state 5V PWM input for compatibility with a wide range of PWM controllers. Applications Notebook Computers Integrated Bootstrap Schottky Diode Adaptive Gate-Drive Timing for Shoot-Through Protection Desktop Computers, V-Core and Non-V-Core DC-DC Converters Under-Voltage Lockout (UVLO) High-Current DC-DC Point-of-Load Converters Small Form-Factor Voltage Regulator Modules Optimized for Switching Frequencies up to 1MHz Low-Profile SMD Package Fairchild Green Packaging and RoHS Compliance High-Performance Gaming Motherboards Compact Blade Servers & Workstations, V-Core and Non-V-Core DC-DC Converters Networking and Telecom Microprocessor Voltage Regulators ® Based on the Intel 4.0 DrMOS Standard Ordering Information Part Number Current Rating Package Top Mark FDMF3030 50A 40-Lead, Clipbond PQFN DrMOS, 6.0mm x 6.0mm Package FDMF3030 © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module September 2012 VIN 3V ~ 24V V5V CVIN CVDRV VCIN VDRV DISB# VIN RBOOT DISB# BOOT PWM Input PWM OFF CBOOT FDMF3030 PHASE ZCD_EN# ON VOUT VSWH LOUT Open-Drain Output THWN# COUT CGND PGND Figure 1. Typical Application Circuit DrMOS Block Diagram VDRV VIN BOOT UVLO VCIN Q1 HS Power MOSFET DBoot DISB# GH Level-Shift GH Logic 10µA 20k PHASE VCIN Dead-Time RUP_PWM Input 3-State Logic PWM Control VSWH VDRV RDN_PWM GL GL Logic THWN# VCIN Q2 LS Power MOSFET Temp. Sense 10µA CGND Figure 2. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 PGND ZCD_EN# DrMOS Block Diagram www.fairchildsemi.com 2 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Application Circuit Figure 3. Bottom View Figure 4. Top View Pin Definitions Pin # Name Description 1 ZCD_EN# When ZCD_EN#=HIGH, the low-side driver is the inverse of the PWM input. When ZCD_EN#=LOW, diode emulation is enabled. This pin has a 10µA internal pull-up current source. Do not add a noise filter capacitor. 2 VCIN IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND. 3 VDRV Power for the gate driver. Minimum 1µF ceramic capacitor is recommended to be connected as close as possible from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 GH 7 PHASE 8 NC No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience. 9 - 14, 42 VIN Power input. Output stage supply voltage. 15, 29 - 35, 43 VSWH Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. 16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET. 36 GL 38 THWN# Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. 39 DISB# Output disable. When LOW, this pin disables power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a three-state 5V PWM signal from the controller. For manufacturing test only. This pin must float; it must not be connected to any pin. Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. For manufacturing test only. This pin must float; it must not be connected to any pin. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com 3 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Pin Configuration Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCIN Supply Voltage Referenced to CGND -0.3 7.0 V VDRV Drive Voltage Referenced to CGND -0.3 7.0 V VDISB# Output Disable Referenced to CGND -0.3 7.0 V VPWM PWM Signal Input Referenced to CGND -0.3 7.0 V Referenced to CGND -0.3 7.0 V Low Gate Manufacturing Test Pin Referenced to CGND -0.3 7.0 V Thermal Warning Flag Referenced to CGND -0.3 7.0 V Power Input Referenced to PGND, CGND -0.3 30.0 V Referenced to VSWH, PHASE -0.3 7.0 V VZCD_EN# ZCD Enable Signal Input VGL VTHWN# VIN VBOOT Bootstrap Supply VGH High Gate Manufacturing Test Pin VPHS PHASE VSWH Switch Node Input VBOOT Bootstrap Supply ITHWN# THWN# Sink Current IO(AV) Output Current(1) θJPCB 30.0 V -0.3 7.0 V Referenced to CGND -0.3 30.0 V Referenced to CGND -0.3 30.0 V Referenced to PGND, CGND (DC Only) -0.3 30.0 V Referenced to PGND, <20ns -8.0 Referenced to VDRV,<20ns -0.1 33.0 V 22.0 V 25.0 V 7.0 mA fSW=300kHz, VIN=12V, VO=1.0V 50 fSW=1MHz, VIN=12V, VO=1.0V 45 Junction-to-PCB Thermal Resistance (Fairchild Evaluation Board) 3 Ambient Temperature Range TJ Maximum Junction Temperature ESD -0.3 Referenced to VDRV TA TSTG Referenced to CGND Referenced to VSWH, PHASE -40 Storage Temperature Range Electrostatic Discharge Protection -55 Human Body Model, JESD22-A114 2000 Charged Device Model, JESD22-C101 2000 A °C/W +125 °C +150 °C +150 °C V Note: 1. IO(AV) is rated using Fairchild’s DrMOS evaluation board, at TA = 25°C, with natural convection cooling. This rating is limited by the peak DrMOS temperature, TJ = 150°C, and varies depending on operating conditions and PCB layout. This rating can be changed with different application settings. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VCIN Control Circuit Supply Voltage 4.5 5.0 5.5 V VDRV Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V (2) VIN Output Stage Supply Voltage 3.0 12.0 24.0 V Note: 2. Operating at high VIN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com 4 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Absolute Maximum Ratings Typical values are VIN = 12V, VCIN = 5V, VDRV = 5V, and TA = TJ = +25°C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit Basic Operation IQ Quiescent Current IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float VUVLO UVLO Threshold VCIN Rising VUVLO_HYS UVLO Hysteresis 2 mA 3.3 V 0.35 V PWM Input (VCIN = VDRV = 5V ±10%) RUP_PWM Pull-Up Impedance VPWM=5V 20 kΩ RDN_PWM Pull-Down Impedance VPWM=0V 20 kΩ VIH_PWM PWM High Level Voltage 3.15 3.80 4.45 V VTRI_HI 3-State Upper Threshold 3.10 3.75 4.40 V VTRI_LO 3-State Lower Threshold 1.05 1.40 1.90 V VIL_PWM PWM Low Level Voltage 0.70 1.00 1.30 V 2.20 2.50 tD_HOLD-OFF 3-State Shut-Off Time VHiZ_PWM 150 3-State Open Voltage tPWM-OFF_MIN PWM Minimum Off Time ns 2.80 70 V ns PWM Input (VCIN = VDRV = 5V ±5%) RUP_PWM Pull-Up Impedance VPWM=5V 20 kΩ RDN_PWM Pull-Down Impedance VPWM=0V 20 kΩ VIH_PWM PWM High Level Voltage 3.35 3.80 4.25 V VTRI_HI 3-State Upper Threshold 3.30 3.75 4.20 V VTRI_LO 3-State Lower Threshold 1.10 1.40 1.75 V VIL_PWM PWM Low Level Voltage 0.74 1.00 1.26 V tD_HOLD-OFF 3-State Shut-Off Time VHiZ_PWM 150 3-State Open Voltage 2.30 tPWM-OFF_MIN PWM Minimum Off Time 2.50 ns 2.70 V 70 ns 2 V DISB# Input VIH_DISB High-Level Input Voltage VIL_DISB Low-Level Input Voltage IPLD 0.8 Pull-Down Current tPD_DISBL Propagation Delay PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW tPD_DISBH Propagation Delay PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH V 10 µA 220 ns 520 ns ZCD_EN# Input VIH_ZCD_EN High-Level Input Voltage VIL_ZCD_EN Low-Level Input Voltage IPLU 2 V 0.8 Pull-Up Current V 10 µA tPD_ZLGLL Propagation Delay PWM=GND, Delay Between ZCD_EN# from HIGH to LOW to GL from HIGH to LOW 1800 ns tPD_ZHGLH Propagation Delay PWM=GND, Delay Between ZCD_EN# from LOW to HIGH to GL from LOW to HIGH 20 ns Continued on the following page… © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com 5 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Electrical Characteristics Typical values are VIN = 12V, VCIN = 5V, VDRV = 5V, and TA = TJ = +25°C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit Thermal Warning Flag TACT Activation Temperature 150 °C TRST Reset Temperature 135 °C 60 Ω 0.8 Ω RTHWN Pull-Down Resistance 5kΩ Resistor Pull-up to VCIN High-Side Driver (fSW = 1000kHz, IOUT = 30A, TA = +25°C) RSOURCE_GH Output Impedance, Sourcing Source Current=50mA RSINK_GH Output Impedance, Sinking Sink Current=50mA 0.6 Ω tR_GH Rise Time GH=10% to 90% 10 ns tF_GH Fall Time GH=90% to 10% 10 ns tD_DEADON LS to HS Deadband Time GL Going LOW to GH Going HIGH, 1.7V GL to 10% GH 20 ns tPD_PLGHL PWM LOW Propagation Delay PWM Going LOW to GH Going LOW, VIL_PWM to 90% GH 20 ns tPD_PHGHH PWM HIGH Propagation Delay (ZCD_EN# =0) PWM Going HIGH to GH Going HIGH, VIH_PWM to 10% GH (ZCD_EN# =0, ID_LS>0) 25 ns tPD_TSGHH Exiting 3-State Propagation Delay PWM (From 3-State) Going HIGH to GH Going HIGH, VIH_PWM to 10% GH 35 ns 0.9 Ω Low-Side Driver (fSW = 1000kHz, IOUT = 30A, TA = +25°C) RSOURCE_GL Output Impedance, Sourcing Source Current=50mA RSINK_GL Output Impedance, Sinking Sink Current=50mA 0.4 Ω tR_GL Rise Time GL=10% to 90% 15 ns tF_GL Fall Time GL=90% to 10% 10 ns SW Going LOW to GL Going HIGH, 1.7V SW to 10% GL 20 ns tD_DEADOFF HS to LS Deadband Time tPD_PHGLL PWM-HIGH Propagation Delay PWM Going HIGH to GL Going LOW, VIH_PWM to 90% GL 20 ns tPD_TSGLH Exiting 3-State Propagation Delay PWM (From 3-State) Going LOW to GL Going HIGH, VIL_PWM to 10% GL 30 ns tGL-ON_MIN GL Minimum On Time in DCM VZCD_EN#=0V 350 ns VF Forward-Voltage Drop IF=1mA 0.6 V VR Breakdown Voltage IR=1mA Boot Diode © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 22 V www.fairchildsemi.com 6 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Electrical Characteristics FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module V IH_PWM V IL_PWM PWM 90% GL 1.7V 10% 90% GH to VSWH 1.7V 10% VSWH t PD t PD PHGLL PLGHL tD_DEADOFF t D_DEADON Figure 5. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 PWM Timing Diagram www.fairchildsemi.com 7 55 50 50 45 45 40 Module Output Current, IOUT (A) Module Output Current, IOUT (A) Test Conditions: VIN=12V or 19V, VOUT=1V, VCIN=5V, VDRV=5V, LOUT=250nH, TA=25°C, and natural convection cooling, unless otherwise specified. 40 FSW = 300kHz 35 30 25 FSW = 1000kHz 20 15 10 VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V 5 30 FSW = 300kHz 25 20 FSW = 1000kHz 15 10 5 VIN = 19V, VDRV & VCIN = 5V, VOUT = 1V 0 0 0 25 Figure 6. 50 75 100 PCB Temperature, T PCB (°C) 125 0 150 Safe Operating Area for 12VIN Figure 7. 50 75 100 125 150 Safe Operating Area for 19VIN 12 12Vin 300kHz 10 12Vin 500kHz VDRV & VCIN = 5V, VOUT = 1V Module Power Loss, PLMOD (W) 11 12Vin 800kHz 9 12Vin 1000kHz 8 7 6 5 4 3 2 1 11 19Vin 300kHz 10 19Vin 500kHz VDRV & VCIN = 5V, VOUT = 1V 19Vin 800kHz 9 19Vin 1000kHz 8 7 6 5 4 3 2 1 0 0 0 5 10 15 20 25 30 35 Module Output Current, IOUT (A) 40 45 50 0 5 Power Loss vs. Output Current for 12VIN Figure 9. Figure 8. 10 15 20 25 30 35 Module Output Current, IOUT (A) 40 45 50 Power Loss vs. Output Current for 19VIN 1.15 1.6 VDRV & VCIN = 5V, VOUT = 1V, FSW = 300kHz, IOUT = 30A VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V, IOUT = 30A Normalized Module Power Loss 1.5 Normalized Module Power Loss 25 PCB Temperature, T PCB (°C) 12 Module Power Loss, PLMOD (W) 35 1.4 1.3 1.2 1.1 1.0 0.9 100 200 Figure 10. 300 400 500 600 700 800 900 Module Switching Frequency, FSW (kHz) 1.05 1.00 0.95 1000 1100 4 Power Loss vs. Switching Frequency © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 1.10 6 Figure 11. 8 10 12 14 16 Module Input Voltage, VIN (V) 18 20 Power Loss vs. Input Voltage www.fairchildsemi.com 8 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics Test Conditions: VIN=12V, VOUT=1V, VCIN=5V, VDRV=5V, LOUT=250nH, TA=25°C, and natural convection cooling, unless otherwise specified. 1.25 1.7 VIN = 12V, VOUT = 1V, FSW = 300kHz, IOUT = 30A 1.6 Normalized Module Power Loss Normalized Module Power Loss 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 1.5 1.4 1.3 1.2 1.1 1.0 VIN = 12V, VDRV & VCIN = 5V, FSW = 300kHz, IOUT = 30A 0.9 4.0 4.5 5.0 5.5 Driver Supply Voltage, VDRV & VCIN (V) Figure 12. 6.0 0.5 Power Loss vs. Driver Supply Voltage 3.5 4.0 Power Loss vs. Output Voltage 35 VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V, IOUT = 0A Driver Supply Current, IDRV + ICIN (mA) VIN = 12V, VDRV & VCIN = 5V, FSW = 300kHz, VOUT = 1V, IOUT = 30A Normalized Module Power Loss 1.5 2.0 2.5 3.0 Module Output Voltage, VOUT (V) Figure 13. 1.01 1.00 0.99 0.98 0.97 0.96 0.95 200 250 Figure 14. 300 350 400 Output Inductor, LOUT (nH) 450 30 25 20 15 10 5 500 100 Power Loss vs. Output Inductor 200 Figure 15. 12 300 400 500 600 700 800 900 Module Switching Frequency, FSW (kHz) 1000 1100 Driver Supply Current vs. Switching Frequency 1.10 VIN = 12V, VDRV & VCIN = 5V, VOUT = 1V VIN = 12V, VOUT = 1V, FSW = 300kHz, IOUT = 0A 11 Normalized Driver Supply Current Driver Supply Current, IDRV + ICIN (mA) 1.0 10 9 8 7 6 1.05 1.00 FSW = 1000kHz 0.95 0.90 FSW = 300kHz 0.85 4.0 Figure 16. 4.5 5.0 5.5 Driver Supply Voltage, VDRV & VCIN (V) 6.0 0 Driver Supply Current vs. Driver Supply Voltage © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 Figure 17. 5 10 15 20 25 30 35 Module Output Current, IOUT (A) 40 45 50 Driver Supply Current vs. Output Current www.fairchildsemi.com 9 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics 3.6 4.5 3.5 4.0 PWM Threshold Voltage, VPWM (V) Driver Supply Voltage, VCIN (V) Test Conditions: VCIN=5V, VDRV=5V, TA=25°C, and natural convection cooling, unless otherwise specified. UVLOUP 3.4 3.3 3.2 3.1 3.0 UVLODN 2.9 -55 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) Figure 18. VHIZ_PWM 3.0 2.5 2.0 VTRI_LO 1.5 1.0 VIL_PWM 4.50 150 UVLO Threshold vs. Temperature 4.75 5.00 5.25 Driver Supply Voltage, VCIN (V) Figure 19. 5.50 PWM Threshold vs. Driver Supply Voltage 2.0 4.5 VCIN = 5V ZCD_EN# Threshold Voltage, VZCD_EN# (V) VIH_PWM 4.0 PWM Threshold Voltage, VPWM (V) VTRI_HI 3.5 0.5 2.8 VTRI_HI 3.5 3.0 VHIZ_PWM 2.5 2.0 VTRI_LO 1.5 1.0 VIL_PWM 0.5 TA = 25°C 1.8 VIH_ZCD_EN# 1.6 1.4 VIL_ZCD_EN# 1.2 1.0 -55 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) Figure 20. 150 4.50 PWM Threshold vs. Temperature 4.75 5.00 5.25 Driver Supply Voltage, VCIN (V) Figure 21. 1.8 5.50 ZCD_EN# Threshold vs. Driver Supply Voltage -2.0 VCIN = 5V VCIN = 5V ZCD_EN# Pull-Up Current, IPLU (uA) ZCD_EN# Threshold Voltage, VZCD_EN# (V) VIH_PWM TA = 25°C 1.7 VIH_ZCD_EN# 1.6 1.5 1.4 VIL_ZCD_EN# 1.3 -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 1.2 -55 0 25 55 100 125 -55 150 Driver IC Junction Temperature, T J (oC) Figure 22. ZCD_EN# Threshold vs. Temperature © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 0 25 55 100 125 150 Driver IC Junction Temperature, T J (oC) Figure 23. ZCD_EN# Pull-Up Current vs. Temperature www.fairchildsemi.com 10 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics Test Conditions: VCIN=5V, VDRV=5V, TA=25°C, and natural convection cooling, unless otherwise specified. 1.8 2.0 VCIN = 5V 1.8 DISB# Threshold Voltage, VDISB# (V) DISB# Threshold Voltage, VDISB# (V) TA = 25°C VIH_DISB# 1.6 1.4 VIL_DISB# 1.2 1.0 1.7 1.5 1.4 VIL_DISB# 1.3 1.2 4.50 4.75 5.00 5.25 Driver Supply Voltage, VCIN (V) Figure 24. 5.50 -55 DISB# Threshold vs. Driver Supply Voltage Figure 25. 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) 150 DISB# Threshold vs. Temperature 700 14 IF = 1mA Boot Diode Forward Voltage, VF (mV) VCIN = 5V DISB# Pull-Down Current, IPLD (uA) VIH_DISB# 1.6 13 12 11 10 9 8 650 600 550 500 450 400 350 300 7 -55 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) Figure 26. -55 150 DISB# Pull-Down Current vs. Temperature © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 Figure 27. 0 25 55 100 125 Driver IC Junction Temperature, T J (oC) 150 Boot Diode Forward Voltage vs. Temperature www.fairchildsemi.com 11 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics The FDMF3030 is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1MHz. Three-State PWM Input The FDMF3030 incorporates a three-state 5V PWM input gate drive design. The three-state gate drive has both logic HIGH level and LOW level, along with a three-state shutdown window. When the PWM input signal enters and remains within the three-state window for a defined hold-off time (tD_HOLD-OFF), both GL and GH are pulled LOW. This enables the gate drive to shut down both high-side and low-side MOSFETs to support features such as phase shedding, which is common on multi-phase voltage regulators. VCIN and Disable (DISB#) The VCIN pin is monitored by an Under-Voltage Lockout (UVLO) circuit. When VCIN rises above ~3.3V, the driver is enabled. When VCIN falls below ~2.95V, the driver is disabled (GH, GL=0). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < VIL_DISB), which holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > VIH_DISB). Table 1. When exiting a valid three-state condition, the FDMF3030 follows the PWM input command. If the PWM input goes from three-state to LOW, the low-side MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 29. The FDMF3030 design allows for short propagation delays when exiting the three-state window (see Electrical Characteristics). UVLO and Disable Logic UVLO DISB# 0 Exiting Three-State Condition Driver State X Disabled (GH, GL=0) 1 0 Disabled (GH, GL=0) 1 1 Enabled (see Table 2) 1 Open Disabled (GH, GL=0) Low-Side Driver The low-side driver (GL) is designed to drive a groundreferenced, low-RDS(ON), N-channel MOSFET. The bias for GL is internally connected between the VDRV and CGND pins. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW. Note: 3. DISB# internal pull-down current source is 10µA. Thermal Warning Flag (THWN#) The FDMF3030 provides a thermal warning flag (THWN#) to warn of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN# output returns to a highimpedance state once the temperature falls to the reset temperature (135°C). For use, the THWN# output requires a pull-up resistor, which can be connected to VCIN. THWN# does NOT disable the DrMOS module. HIGH THWN# Logic State High-Side Driver The high-side driver (GH) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the three-state window for longer than the three-state hold-off time, tD_HOLD-OFF. 135°C Reset 150°C Temperature Activation Temperature Normal Operation Thermal Warning LOW TJ_driver IC Figure 28. THWN Operation © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com 12 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Functional Description The driver IC advanced design ensures minimum MOSFET dead-time, while eliminating potential shootthrough (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 29 provides the relevant timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes V IH_PWM To prevent overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the GH-to-PHASE pin pair. When the PWM signal goes LOW, Q1 begins to turn off after a propagation delay (tPD_PLGHL). Once the voltage across GH-to-PHASE falls below 1.7V, Q2 begins to turn on after adaptive delay tD_DEADOFF. V IH_PWM V IH_PWM V IL V IH_PWM V TRI_HI V TRI_HI V TRI_LO V IL_PWM PWM tR_GH PWM less than t D_HOLD‐OFF GH to VSWH tF_GH 90% tD_HOLD‐OFF 10% V IN CCM DCM DCM V OUT 1.7V VSWH GL 90% 1.7V tPD_PHGLL tD_DEADON 90% 10% 10% tPD_PLGHL tR_GL tF_GL tD_DEADOFF Enter 3‐State tPD_TSGHH tD_HOLD‐OFF Enter 3 ‐State Exit 3‐State tPD_TSGHH Exit 3‐ State less than t D_HOLD‐OFF tD_HOLD‐OFF tPD_TSGLH Enter 3 ‐State Exit 3‐State Notes: tPD_xxx = propagation delay from external signal (PWM, ZCD_EN#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS Vgs (GL) going LOW) tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS Vgs (GL) LOW to HS Vgs (GH) HIGH) Exiting 3‐state PWM tPD_TSGHH = PWM 3‐state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_TSGLH = PWM 3‐state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (ZCD_EN# held LOW) ZCD_EN# Dead Times tD_DEADON = LS VGS fall to HS VGS rise, LS‐comp trip value (~1.7V GL) to 10% HS VGS tPD_ZLGLL = ZCD_EN# fall to LS VGS fall, VIL_ZCD_EN to 90% LS VGS tPD_ZHGLH = ZCD_EN# rise to LS VGS rise, VIH_ZCD_EN to 10% LS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW‐comp trip value (~1.7V VSWH) to 10% LS VGS Figure 29. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 PWM and 3-StateTiming Diagram www.fairchildsemi.com 13 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module HIGH, Q2 begins to turn off after a propagation delay (tPD_PHGLL). Once the GL pin is discharged below 1.7V, Q1 begins to turn on after adaptive delay tD_DEADON. Adaptive Gate Drive Circuit The Zero Cross Detection Mode allows for higher converter efficiency when operating in light-load conditions. When ZCD_EN# is pulled LOW; the low-side MOSFET gate signal pulls LOW when internal circuitry detects positive LS MOSFET drain current, preventing discharge of the output capacitors as the filter inductor current attempts reverse current flow – known as “Diode Emulation” Mode. When the ZCD_EN# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode, which allows for gating of the low-side MOSFET. Table 2. ZCD_EN# Logic DISB# PWM ZCD_EN# GH GL 0 X X 0 0 1 3-State X 0 0 1 0 0 0 0 (IL<0),1 (IL > 0)(4) 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 Note: 4. GL = 0, when IL < 0 (Inductor current is negative and flowing in to the DrMOS VSWH node). GL = 1 when IL > 0 (Inductor current is positive and flowing out of the DrMOS VSWH node). ZCD_EN# V IH_ZCD_EN V IL_ZCD_EN V IL_ZCD_EN V IH_PWM VIH_PWM VIL_PWM PWM 90% 1.7V GH to VSWH 1 0% DCM DCM (IL = 0) IL > 0 VOUT VSWH GL 90% 90% 1.7V tPD_PHGLL tD_DEADON 10% tPD_PLGHL tD_DEADOFF 10% Delay from ZCD_EN# going high to LS V GS high Figure 30. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 tPD_ZHGLH I L < 0 detected and GL transitions low. tPD_ZLGLL tPD_PHGLL Delay from ZCD_EN# going low to LS V GS low ZCD_EN# Timing Diagram www.fairchildsemi.com 14 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module When the ZCD_EN# pin is pulled LOW, the low-side MOSFET is gated off automatically during positive LS MOSFET drain current. If the ZCD_EN# pin is pulled LOW by the PWM controller to support light-load PowerSaving Mode, FDMF3030 can actively turn off the lowside MOSFET when it detects the zero crossing of the inductor current. The low-side MOSFET turns on when inductor current is positive (LS MOSFET drain current is negative) and turns off when inductor current is negative (LS MOSFET drain current is positive). Zero-crossing detection of the inductor current and low-side MOSFET on and off are automatically performed on a cycle-bycycle basis. Normally this pin is active LOW. See Figure 30 for timing delays. Zero Cross Detection Mode (ZCD_EN#) Supply Capacitor Selection VCIN Filter For the supply inputs (VCIN), a local ceramic bypass capacitor is recommended to reduce noise and to supply the peak current. Use at least a 1µF X7R or X5R capacitor. Keep this capacitor close to the VCIN pin and connect it to the GND plane with vias. The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFET. In most cases, it can be connected directly to VCIN, the pin that provides power to the logic section of the driver. For additional noise immunity, an RC filter can be inserted between the VDRV and VCIN pins. Recommended values would be 10Ω and 1µF. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 31. A bootstrap capacitance of 100nF X7R or X5R capacitor is usually adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor may be required when operating above 15VIN and is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. RBOOT values from 0.5Ω to 3.0Ω are typically effective in reducing VSWH overshoot. V 5V A I5V R VCIN C VDRV Power loss calculations are: PIN=(VIN x IIN) + (V5V x I5V) (W) (1) PSW=VSW x IOUT (W) (2) POUT=VOUT x IOUT (W) (3) PLOSS_MODULE=PIN - PSW (W) (4) PLOSS_BOARD=PIN - POUT (W) (5) EFFIMODULE=100 x PSW/PIN (%) (6) EFFIBOARD=100 x POUT/PIN (%) (7) C VIN C VCIN A IIN VIN VIN DISB# PWM Input Measurement and Calculation Refer to Figure 31 for power loss testing method. VCIN VDRV DISB# Power Loss and Efficiency R BOOT BOOT PWM OFF FDMF 6705 FDMF3030 C BOOT IOUT VSWH ON ZCD_END# Open Drain Output A L OUT PHASE THWN# CGND Figure 31. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 V V SW PGND VOUT C OUT Circuit Diagram and Power Loss Measurement www.fairchildsemi.com 15 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Application Information may be required when operating above 15VIN and is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. RBOOT can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative VSWH ringing. Inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise trade-offs must be considered. RBOOT values from 0.5 to 3.0 are typically effective in reducing VSWH overshoot. Figure 32 and Figure 33 provide an example of a proper layout for the FDMF3030 and critical components. All of the high-current paths; such as VIN, VSWH, VOUT, and GND copper; should be short and wide for low inductance and resistance. This aids in achieving a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. Recommendations for PCB Designers Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This reduces the highcurrent power loop inductance and the input current ripple induced by power MOSFET switching operation. The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing. The VSWH copper trace serves two purposes. In addition to being the high-frequency current path from the DrMOS package to the output inductor, it serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, high-current flow between the DrMOS and inductor. The short and wide trace minimizes electrical losses as well as the DrMOS temperature rise. The VSWH node is a high-voltage and high-frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace acts as a heat sink for the lower MOSFET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission. GND pad and PGND pins should be connected to the GND copper plane with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs and should be avoided. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode. An output inductor should be located close to the FDMF3030 to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS. The ZCD_EN# and DISB# pins have weak internal pullup and pull-down current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary. PowerTrench® MOSFETs are used in the output stage and minimize ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The selected resistor and capacitor need to be the proper size for power dissipation. Use multiple vias on the VIN and VOUT copper areas to interconnect top, inner, and bottom layers to distribute current flow and heat conduction. Do not put many vias on the VSWH copper to avoid extra parasitic inductance and noise on the switching waveform. As long as efficiency and thermal performance are acceptable, place only one VSWH copper on the top layer and use no vias on the VSWH copper to minimize switch node parasitic noise. Vias should be relatively large and of reasonably low inductance. Critical high-frequency components, such as RBOOT, CBOOT, RC snubber, and bypass capacitors; should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they can be connected from the backside through a network of lowinductance vias. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the VCIN-to-CGND, VDRV-toCGND, and BOOT-to-PHASE pin pairs to ensure clean and stable power. Routing width and length should be considered as well. Include a trace from the PHASE pin to the VSWH pin to improve noise margin. Keep this trace as short as possible. The layout should include the option to insert a smallvalue series boot resistor between the boot capacitor and BOOT pin. The boot-loop size, including RBOOT and CBOOT, should be as small as possible. The boot resistor © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com 16 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module PCB Layout Guidelines FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module PCB Layout Guidelines (Continued) Figure 32. Figure 33. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 PCB Layout Example (Top View) PCB Layout Example (Bottom View) www.fairchildsemi.com 17 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module Physical Dimensions B 0.10 C PIN#1 INDICATOR 6.00 2X 5.80 A 4.50 30 21 31 6.00 20 0.40 2.50 0.65 0.25 1.60 0.10 C 11 40 2X 1 SEE 0.60 DETAIL 'A' 0.50 TYP TOP VIEW 10 0.35 0.15 2.10 0.40 21 FRONT VIEW 4.40±0.10 (2.20) 0.10 C A B C 0.05 0.30 30 0.20 (40X) 31 20 0.50 PIN #1 INDICATOR 0.20 MAY APPEAR AS OPTIONAL 2.40±0.10 (0.70) 1.50±0.10 11 10 0.40 2.00±0.10 (0.20) 0.50 (40X) 0.30 40 1 2.00±0.10 0.50 NOTES: UNLESS OTHERWISE SPECIFIED (0.20) BOTTOM VIEW A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-220, DATED MAY/2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV3 1.10 0.90 0.10 C 0.08 C 0.30 0.20 2.10 LAND PATTERN RECOMMENDATION 0.05 0.00 DETAIL 'A' C SEATING PLANE SCALE: 2:1 Figure 34. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com 18 FDMF3030 — Extra-Small, High-Performance, High-Frequency DrMOS Module © 2012 Fairchild Semiconductor Corporation FDMF3030 • Rev. 1.0.0 www.fairchildsemi.com 19