FDMF8704V tm High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Benefits General Description Fully optimized system efficiency. Higher efficiency levels are achievable compared with conventional discrete components. The FDMF8704V is a fully optimized integrated Driver plus MOSFET power stage solution for high current synchronous buck DC-DC applications. The device integrates a driver IC and two Power MOSFETs into a space saving, MLP 8x8, 56-pin package. Fairchild Semiconductor’s integrated approach optimizes the complete switching power stage with regards to driver to FET dynamic performance, system inductance and overall solution ON resistance. Package parasitics and problematical layouts associated with conventional discrete solutions are greatly reduced. This integrated approach results in significant board space saving, therefore maximizing footprint power density. This solution is based on the Intel™ DrMOS specification. Space savings of up to 50% PCB versus discrete solutions. Higher frequency of operation. Simpler system design and board layout. Reduced time in component selection and optimization. Features 7V to 20V Input Voltage Range Output current to 32A 1MHz switching frequency capable Applications Internal adaptive gate drive Low Side FET with Integrated Schottky Diode Desktop and server VR11.x V-core and non V-core buck converters. CPU/GPU power train in game consoles and high end desktop systems. Low profile SMD package High-current DC-DC Point of Load (POL) converters. RoHS Compliant Networking and telecom microprocessor voltage regulators. Small form factor voltage regulator modules. Peak Efficiency >90% Output disable for lost phase shutdown Integrated 5V regulator Powertrain Application Circuit 7 - 20V REGOUT REGFB VAUX VCIN VIN CVIN DISB PWM Input DISB BOOT PWM HSEN VSWH CGND CVCIN CBOOT OUTPUT COUT PGND Figure 1. Powertrain Application Circuit Ordering Information Part Current Rating Max [A] Input Voltage Typical [V] Frequency Max [KHz] Device Marking FDMF8704V 32 12-19 1000 FDMF8704V ©2007 Fairchild Semiconductor Corporation FDMF8704V Rev. G 1 www.fairchildsemi.com FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator November 2007 CGND HSEN VAUX VCIN BOOT CGND NC VIN VIN TEST PAD 1 VIN VIN VIN VIN 1 PWM 56 DISB REGFB NC REGOUT CGND VSWH VSWH VSWH VSWH VSWH VSWH VSWH VSWH 43 14 15 VIN VIN VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND PGND 28 PGND B (VIN) A (CGND) C (VSWH) 29 VSWH VSWH VSWH TEST PAD 2 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND 42 Figure 2. MLP 8x8 56L Bottom View Pin Description Pin Name Function 1, 6, 51, A CGND IC Ground. Ground return for driver IC. 2 HSEN High Side FET Enable. Must be connected to BOOT pin. 3 VAUX Auxiliary Power for 5V regulator Op-Amp. 4 VCIN IC Supply. +5V chip bias power. Bypass with a 1µF ceramic capacitor. 5 BOOT Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect to bootstrap capacitor. 7, 53 NC No Connect. Switch Node Input. SW Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. 21, 40-50, C VSWH 8, 9, 11-20, B VIN 10 TEST PAD 1 22-38 PGND 39 TEST PAD 2 For manufacturing test only. LDRV pin. This pin must be floated. Must not be connected to any pin. 52 REGOUT Regulator Driver Output. An external NPN transistor is used to generate the 5V output voltage with internal controller. 54 REGFB Regulation Sense Input. The internal resistor divider will set this voltage to be regulated at 5V. 55 DISB Output Disable. When low, this pin disable FET switching (HDRV and LDRV are held low). 56 PWM PWM Signal Input. This pin accepts a logic-level PWM signal from the controller. FDMF8704V Rev. G Power Input. Output stage supply voltage. For manufacturing test only. HDRV pin. This pin must be floated. Must not be connected to any pin. Power Ground. Output stage ground. Source pin of low side MOSFET(s). 2 www.fairchildsemi.com FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter Min. Max. Units VCIN, PWM, DISB to PGND -0.3 6 V VIN to PGND -0.3 24 V BOOT to VSWH -0.3 6 V VAUX to PGND -0.3 20 V VSWH to PGND -1.0 24 V BOOT to PGND -0.3 30 V IO(AV) VIN = 12V, VO = 1.3V, fsw = 1MHz, TPCB = 100°C 32 A IO(PK) VIN = 12V, tPULSE = 10µs 65 A RθJPCB Junction to PCB Thermal Resistance (note 1) 5 °C/W PD TPCB = 100°C (note 1) 10 W 150 °C Operating and Storage Junction Temperature Range -55 Note 1: Package power dissipation based on 4 layers, 2 square inch, 2 oz. copper pad. RθJPCB is the steady state junction to PCB thermal resistance with PCB temperature referenced at VSWH pin. Recommended Operating Range The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Parameter Min. Typ. Max. Units VCIN Control Circuit Supply Voltage 4.5 5 5.5 V VIN Output Stage Supply Voltage 7 12 20 V VOUT Output Voltage 0.8 1.3 3.2 V Electrical Characteristics VIN = 12V, VCIN = 5V, TA = 25°C unless otherwise noted. Parameter Operating Voltage Range Symbol Conditions VCC Control Circuit Supply Current ICC PWM Input High Voltage VIH(PWM) Min. Typ. Max. Units 4.5 V 5 5.5 fSW = 0Hz, VDISB = 5V 1 3 fSW = 1MHz, VDISB = 5V 50 2.4 PWM Input Low Voltage VIL(PWM) PWM Input Current IIL(PWM) -2 2.4 DISB Input High Voltage VIHDISB) DISB Input Low Voltage VIL(DISB) DISB Input Current IDISB Auxiliary Input Voltage Operating Range VAUX Regulator Output Voltage VREGOUT tPDH(DISB-LDRV)(2) Propagation Delay tPDL(LDRV)(2) (2) V 0.8 V 2 µA V 0.8 V -2 2 µA 7 20 V 4.75 tPDL(DISB-LDRV)(2) mA 5 5.25 V 8 ns 6 ns VIN = 12V, VOUT = 1.3V, 9 ns fsw = 1MHz, IO = 30A 22 ns tPDH(LDRV)(2) 12 ns tPDH(HDRV)(2) 20 ns tPDL(HDRV) Note 2: tPDL(LDRV/HRDV) refers to HIGH-to-LOW transition, tPDH(LDRV/HDRV) refers to LOW-to-HIGH transition. FDMF8704V Rev. G 3 www.fairchildsemi.com FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Absolute Maximum Rating REGFB REGOUT VAUX HSEN BOOT HDRV VIN REF VCIN Q1 DISB R R PWM VSWH Q2 VCIN CGND LDRV PGND Figure 3. Functional Block Diagram Functional Description Adaptive Gate Drive Circuit The FDMF8704V is a driver plus FET module optimized for synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1MHz. The driver IC embodies an advanced design that ensures minimum MOSFET dead-time while eliminating potential shootthrough (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. Refer to Figure 4 and 5 for the relevant timing waveforms. To prevent overlap during the lowto-high switching transition (Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage at the LDRV pin. When the PWM signal goes HIGH, Q2 will begin to turn OFF after some propagation delay (tPDL(LDRV)). Once the LDRV pin is discharged below ~1.2V, Q1 begins to turn ON after adaptive delay tPDH(HDRV). To preclude overlap during the high-to-low transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the SW pin. When the PWM signal goes LOW, Q1 will begin to turn OFF after some propagation delay (tPDL(HDRV)). Once the VSWH pin falls below ~2.2V, Q2 begins to turn ON after adaptive delay tPDH(LDRV). Additionally, VGS of Q1 is monitored. When VGS(Q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in Q2 being driven ON after tPDH(LDRV), regardless of SW state. This function is implemented to ensure CBOOT is recharged each switching cycle, particularly for cases where the power converter is sinking current and SW voltage does not fall below the 2.2V adaptive threshold. Secondary delay tPDH(HDRV) is longer than tPDH(LDRV). Low-Side Driver The low-side driver (LDRV) is designed to drive a ground referenced low RDS(ON) N-channel MOSFET. The bias for LDRV is internally connected between VCIN and CGND. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB = 0V), LDRV is held low. High-Side Driver The high-side driver (HDRV) is designed to drive a floating Nchannel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the external diode and external bootstrap capacitor (CBOOT). During start-up, VSWH is held at PGND, allowing CBOOT to charge to VCIN through the internal diode. When the PWM input goes high, HDRV will begin to charge the high-side MOSFET's gate (Q1). During this transition, charge is removed from CBOOT and delivered to Q1's gate. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VC(BOOT), which provide sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to VSWH. CBOOT is then recharged to VCIN when VSWH falls to PGND. HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low. FDMF8704V Rev. G 4 www.fairchildsemi.com FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Functional Block Diagram FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Timing Diagram VIH(DISB) DISB VIL(DISB) tPDH(DISB) tPDL(DISB) LDRV / HDRV Figure 4. Output Disable Timing VIH(PWM) PWM VIL(PWM) tPDL(LDRV) LDRV 1.2V tPDH(HDRV) HDRV-SW tPDL(HDRV) tPDH(LDRV) SW 2.2V Figure 5. Adaptive Gate Drive Timing FDMF8704V Rev. G 5 www.fairchildsemi.com VIN = 12V, VCIN = 5V, TA = 25°C unless otherwise noted. 10 35 VIN = 12V VOUT = 1.3V L = 0.33uH 30 8 20 PLOSS, W ILOAD, A 25 15 10 VIN = 12V VOUT = 1.3V fSW = 1MHz L = 0.33uH 5 fSW = 1MHz 6 4 fSW = 500KHz 2 0 0 0 25 50 75 100 o PCB Temperature, C 125 0 150 Figure 6. Safe Operating Area PLOSS (NORMALIZED) 0.90 0.80 20 25 30 1.10 1.05 VOUT = 1.3V IOUT = 30A L = 0.33uH fSW = 1MHz 1.00 0.95 0.70 300 400 500 600 700 800 fSW, KHz 900 1000 1100 6 1200 Figure 8. Power Loss vs. Switching Frequency 8 10 12 Input Voltage, V 14 16 Figure 9. Power Loss vs. Input Voltage 1.15 1.6 1.10 1.4 PLOSS (NORMALIZED) PLOSS (NORMALIZED) 15 ILOAD, A 1.15 VIN = 12V VOUT = 1.3V IOUT = 30A L = 0.33uH 1.00 1.05 1.00 10 Figure 7. Module Power Loss vs. Output Current 1.10 PLOSS (NORMALIZED) 5 VIN = 12V VOUT = 1.3V IOUT = 30A L = 0.33uH fSW = 1MHz 0.95 VIN = 12V IOUT = 30A L = 0.33uH fSW = 1MHz 1.2 1.0 0.8 4.5 5.0 5.5 Driver Supply Voltage, V 6.0 0.8 Figure 10. Power Loss vs. Driver Supply Voltage FDMF8704V Rev. G 1.2 1.6 2.0 2.4 Output Voltage, V 2.8 3.2 Figure 11. Power Loss vs. Output Voltage 6 www.fairchildsemi.com FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Typical Characteristics VIN = 12V, VCIN = 5V, TA = 25°C unless otherwise noted. 1.06 1.0 VCIN = 5V DISB = 5V 1.04 Driver Suppy Current , mA PLOSS (NORMALIZED) 0.9 1.02 VIN = 12V VOUT = 1.3V IOUT = 30A fSW = 1MHz 1.00 0.8 PWM = 5V 0.7 0.6 PWM = 0V 0.5 0.98 0.4 0.0 0.2 0.4 0.6 Output Inductance, uH 0.8 1.0 -50 Figure 12. Power Loss vs. Output Inductance 0 25 50 Temperature, oC 75 100 125 Figure 13. Driver Supply Current vs. Temperature 1.83 50 VCIN = 5V VCIN = 5V 40 PWM Threshold Voltage, V Driver Suppy Current , mA -25 30 20 10 1.81 VIH 1.79 VIL 1.77 1.75 0 0 200 400 600 800 -50 1000 fSW, KHz Figure 14. Driver Supply Current vs. Frequency -25 0 25 50 Temperature, oC 75 100 125 Figure 15. PWM Threshold Voltage vs. Temperature 1.90 DISB Threshold Voltage, V VCIN = 5V 1.85 VIH 1.80 1.75 VIL 1.70 1.65 -50 -25 0 25 50 Temperature, oC 75 100 125 Figure 16. DISB Threshold Voltage vs. Temperature FDMF8704V Rev. G 7 www.fairchildsemi.com FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Typical Characteristics bootstrap capacitance of 100nF, X7R or X5R capacitor is adequate. Supply Capacitor Selection For the supply input (VCIN) of the FDMF8704V, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. Use at least a 1µF, X7R or X5R capacitor. Keep this capacitor close to the FDMF8704V VCIN and CGND pins. The peak surge current rating of the boot diode should be checked in-circuit, since this is dependent on the equivalent impedance of the entire bootstrap circuit, including the PCB traces. Boot diode must be sized big enough to carry the forward charge current. Refer to Figure 14 for boot diode average forward current. Bootstrap Circuit The bootstrap diode must have low VF and low reverse current leakage. Breakdown voltage of the bootstrap diode must be greater than the BOOT to VSWH voltage. The bootstrap circuit uses a charge storage capacitor (CBOOT) and the external schottky diode, as shown in Figure 18. A Typical Application NPN-TR VIN 12V VAUX REG REGFB VCIN VIN PWM BOOT HSEN DISB CGND VSWH PGND FDMF8704V NPN-TR VAUX REG REGFB VCIN VIN PWM VCC EN PWM1 PWM2 PWM Controller PWM3 PWM4 GND BOOT HSEN DISB CGND VSWH PGND FDMF8704V VOUT NPN-TR VAUX REG REGFB VCIN VIN PWM Signal GND Power GND BOOT HSEN DISB CGND VSWH PGND FDMF8704V NPN-TR VAUX REG REGFB VIN VCIN PWM BOOT HSEN DISB CGND VSWH PGND FDMF8704V Figure 17. Typical Application FDMF8704V Rev. G 8 www.fairchildsemi.com FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Application Information 2. It is critical that the VSWH copper has minimum area for lower switching noise emission. VSWH copper trace should also be wide enough for high current flow. Other signal routing path, such as PWM IN and BOOT signal, should be considered with care to avoid noise pickup from VSWH copper area. Refer to Figure 18 for module power loss testing method. Power loss calculation are as follows: (a) PIN (b) POUT (c) PLOSS = (VIN x IIN) + (VCIN x ICIN) (W) = VO x IOUT (W) = PIN - POUT (W) 3. Output inductor location should be as close as possible to the FDMF8704V for lower power loss due to copper trace. PCB Layout Guideline 4. Snubber for suppressing ringing and spiking of VSWH voltage should be placed near the FDMF8704V. The resistor and capacitor need to be of proper size for power dissipation. Figure 19. shows a proper layout example of FDMF8704V and critical parts. All of high current flow path, such as VIN, VSWH, VOUT and GND copper, should be short and wide for better and stable current flow, heat radiation and system performance. 5. Place boot diode, ceramic bypass capacitor and boot capacitor as close to VCIN and BOOT pin of FDMF8704V in order to supply stable power. Routing width and length should also be considered Following is a guideline which the PCB designer should consider: 6. Use multiple Vias on each copper area to interconnect each top, inner and bottom layer to help smooth current flow and heat conduction. Vias should be relatively large and of reasonable inductance. 1. Input bypass capacitors should be close to VIN and GND pin of FDMF8704V to help reduce input current ripple component induced by switching operation. VIN IIN ICIN A A CCIN CVIN VIN DISB DISB VCIN BOOT HSEN PWM Input VCIN PWM CGND CBOOT IOUT A VSWH V VO PGND OUTPUT COUT Figure 18. Power Loss Measurement Block Diagram Figure 19. Typical PCB Layout Example (Top View) FDMF8704V Rev. G 9 www.fairchildsemi.com FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Module Power Loss Measurement and Calculation (DATUM A) Bayan Lepas FIZ 11900, Penang, Malaysia FDMF8704V Rev. G 10 www.fairchildsemi.com FDMF8704V High Efficiency / High Frequency FET plus Driver Multi-chip Module with Internal Voltage Regulator Dimensional Outline and Pad layout TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ SyncFET™ ® Power220® ® Power247 The Power Franchise® POWEREDGE® Power-SPM™ PowerTrench® TinyBoost™ Programmable Active Droop™ TinyBuck™ ® QFET TinyLogic® QS™ TINYOPTO™ QT Optoelectronics™ TinyPower™ ® Quiet Series™ TinyPWM™ RapidConfigure™ TinyWire™ Fairchild® SMART START™ Fairchild Semiconductor® μSerDes™ ® SPM FACT Quiet Series™ UHC® STEALTH™ FACT® Ultra FRFET™ SuperFET™ FAST® UniFET™ SuperSOT™-3 FastvCore™ VCX™ ® ®* SuperSOT™-6 FlashWriter SuperSOT™-8 * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I32 © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com