FDMF6704 - XSTM DrMOS The Xtra Small High Performance, High Frequency DrMOS Module Benefits tm General Description The XSTM DrMOS family is Fairchild’s next-generation fullyoptimized ultra-compact integrated MOSFET plus driver power stage solution for high current, high frequency synchronous buck DC-DC applications. The FDMF6704 DrMOS integrates a driver IC, two power MOSFETs and a bootstrap Schottky diode into a thermally enhanced compact 6 mm x 6 mm MLP package. With an integrated approach, the complete switching power stage is optimized with regards to driver and MOSFET dynamic performance, system inductance and RDS(ON). This greatly reduces the package parasitics and layout challenges associated with conventional discrete solutions. The driver IC incorporates advanced features such as SMOD. PWM input is Tri-State compatible. A 5 V gate drive and an improved PCB interface [Low Side MOSFET exposed pad] ensure higher performance. This product is compatible with the new Intel 6 mm x 6 mm DrMOS specification. Ultra compact size - 6 mm x 6 mm MLP, 44 % space saving compared to conventional MLP 8 mm x 8 mm DrMOS packages. Fully optimized system efficiency. Clean voltage waveforms with reduced ringing. High frequency operation. Compatible with a wide variety of PWM controllers in the market. Features Ultra- compact thermally enhanced 6 mm x 6 mm MLP package 84 % smaller than conventional discrete solutions. Synchronous driver plus FET multichip module. High current handling of 35 A. Over 93 % peak efficiency. Applications Tri-State PWM input. Fairchild's PowerTrench® 5 technology MOSFETs for clean voltage waveforms and reduced ringing. Compact blade servers V-core, non V-core and VTT DC-DC converters. Optimized for high switching frequencies of up to 1 MHz. Skip mode SMOD [low side gate turn off] input. Desktop computers V-core, non V-core and VTT DC-DC converters. Fairchild SyncFETTM [integrated Schottky diode] technology in the low side MOSFET. Workstations V-core, non V-core and VTT DC-DC converters. Integrated bootstrap Schottky diode. Adaptive gate drive timing for shoot-through protection. Gaming Motherboards V-core, non V-core and VTT DC-DC converters. Driver output disable function [DISB# pin]. Gaming consoles. Undervoltage lockout (UVLO). High-current DC-DC Point of Load (POL) converters. Fairchild Green Packaging and RoHS compliant. Low profile SMD package. Networking and telecom microprocessor voltage regulators. Power Train Application Circuit 5V CVDRV CVCIN 12 V CVIN VDRV VCIN DISB# VIN DISB# PWM Input OFF ON BOOT PWM SMOD# CGND CBOOT PHASE VSWH OUTPUT COUT PGND Figure 1. Power Train Application Circuit Ordering Information Part Current Rating @ 350 kHz [A] Input Voltage Typical [V] Frequency Max [kHz] Device Marking FDMF6704 35 8-14 1000 FDMF6704 ©2008 Fairchild Semiconductor Corporation FDMF6704 Rev.D 1 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module September 2008 VCIN VDRV BOOT HDRV VIN Q1 DISB# Overlap VSWH Control PWM VDRV SMOD# Q2 CGND LDRV PGND Figure 2. Functional Block Diagram SMOD# VCIN VDRV BOOT CGND HDRV PHASE NC VIN VIN Pin Configuration 1 PWM DISB# NC CGND LDRV VSWH VSWH VSWH VSWH VSWH 10 40 11 (VIN) (CGND) (VSWH) 20 31 21 VSWH VSWH PGND PGND PGND PGND PGND PGND PGND PGND 30 VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND Figure 3. 6mm x 6mm, 40L MLP Bottom View FDMF6704 Rev. D 2 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Functional Block Diagram Pin Name 1 SMOD# 2 VCIN Function When SMOD# = HI, low side driver is inverse of PWM input. When SMOD# = Low, low side driver is disabled. IC bias supply. Minimum 1 F ceramic capacitor is recommended from this pin to CGND. 3 VDRV Power for low side driver. Minimum 1 F ceramic capacitor is recommended to be connected as close as possible from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor from this pin to PHASE. 5, 37 CGND IC ground. Ground return for driver IC. 6 HDRV For manufacturing test only. This pin must be floated. Must not be connected to any pin. 7 PHASE Switch node pin for easy bootstrap capacitor routing. Electrically shorted to VSWH pin. 8, 38 NC No connect. 9-14 VIN Power input. Output stage supply voltage. 15, 29-35 VSWH Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. 16-28 PGND Power ground. Output stage ground. Source pin of low side MOSFET(s). 36 LDRV For manufacturing test only. This pin must be floated. Must not be connected to any pin. 39 DISB# Output disable. When low, this pin disable FET switching (HDRV and LDRV are held low). 40 PWM PWM Signal Input. This pin accepts a Tri-state logic-level PWM signal from the controller. Absolute Maximum Rating Parameter Min Max Units VCIN, VDRV, DISB#, PWM, SMOD#, LDRV to CGND 6 V VIN to PGND, CGND 27 V BOOT, HDRV to VSWH 6 V BOOT, VSWH, HDRV to GND 27 V BOOT to VDRV 22 V IO(AV) VIN = 12 V, VO = 1.3 V fSW = 350 kHz 35 A fSW = 1 MHz 32 A IO(peak) RθJPCB Junction to PCB Thermal Resistance Operating and Storage Junction Temperature Range -55 80 A 3.75 °C/W 150 °C Recommended Operating Range Parameter VCIN VIN Control Circuit Supply Voltage Output Stage Supply Voltage Min Typ Max Units 4.5 5 5.5 V 12 14 V 8 * * May be operated at lower input voltage. See figure 8. FDMF6704 Rev. D 3 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Pin Description VIN = 12 V, TA = 25 °C unless otherwise noted. Parameter Operating Quiescent Current Symbol IQ Conditions Min Typ Max PWM = GND 2 PWM = VCIN 2 Units mA VCIN UVLO UVLO Threshold 3.0 UVLO COMP Hysteresis 3.2 3.4 V 0.2 V 10 k PWM Input Sink Impedance Source Impedance 10 Tri-State Rising Threshold VCIN = 5 V 3.2 VCIN = 5 V 1.2 Hysteresis 3.4 k 3.6 100 Tri-State Falling Threshold 1.4 V mV 1.6 V Hysteresis 100 mV Tri-State Pin Open 2.5 V Tri-State Shut Off Time 100 ns SMOD# and DISB# Input High Level Input Voltage 2 V Low Level Input Voltage Input Bias Current -2 0.8 V 2 A PWM = GND, delay between SMOD# or DISB# from HI to LO to LDRV from HI to LO. 15 ns 10 % to 90 % 25 ns Fall Time 90 % to 10 % 20 ns Deadband Time tDTHH LDRV going LO to HDRV going HI, 10 % to 10 % 25 ns Propagation Delay tPDHL PMW going LO to HDRV going LO 10 ns 10 % to 90 % 25 ns Fall Time 90 % to 10 % 20 ns Deadband Time tDTLH VSWH going LO to LDRV going HI, 10 % to 10 % 20 ns Propagation Delay tPDLL PWM going HI to LDRV going LO 10 ns Delay between HDRV from HI to LO and LDRV from LO to HI. 250 ns Propagation Delay Time High Side Driver Rise Time Low Side Driver Rise Time 250 ns Time Out Circuit 250 ns Time Delay FDMF6704 Rev. D 4 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Electrical Characteristics Circuit Description SMOD The FDMF6704 is a driver plus FET module optimized for synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1 MHz. The SMOD (Skip Mode) function allows for higher converter efficiency under light load conditions. During SMOD, the LS FET is disabled and it prevents discharging of output caps. When the SMOD# pin is pulled high, the sync buck converter will work in synchronous mode. When the SMOD# pin is pulled low, the LS FET is turned off. The SMOD function does not have internal current sensing. This SMOD# pin is connected to a PWM controller which enables or disables the SMOD automatically when the controller detects light load condition. Normally this pin is Active Low. PWM When the PWM input goes high, the high side MOSFET turns on. When it goes low, the low side MOSFET turns on. When it is open, both the low side and high side MOFET will turn off. Adaptive Gate Drive Circuit The DISB# input is combined with the PWM signal to control the driver output. In a typical multiphase design, DISB# will be a shared signal used to turn on all phases. The individual PWM signals from the controller will be used to dynamically enable or disable individual phases. The driver IC embodies an advanced design that ensures minimum MOSFET dead-time while eliminating potential shoot-through (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. Refer to Figure 4 for the relevant timing waveforms. Low-Side Driver The low-side driver (LDRV) is designed to drive a ground referenced low RDS(ON) N-channel MOSFET. The bias for LDRV is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB# = 0 V), LDRV is held low. To prevent overlap during the low-to-high switching transition (Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage at the LDRV pin. When the PWM signal goes HIGH, Q2 will begin to turn OFF after some propagation delay (tPDLL). Once the LDRV pin is discharged below 1 V, Q1 begins to turn ON after adaptive delay tDTHH. High-Side Driver To preclude overlap during the high-to-low transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 will begin to turn OFF after some propagation delay (tPDHL). Once the VSWH pin falls below 1 V, Q2 begins to turn ON after adaptive delay tDTLH. The high-side driver (HDRV) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal diode and external bootstrap capacitor (CBOOT). During start-up, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes high, HDRV will begin to charge the high-side MOSFET's gate (Q1). During this transition, charge is removed from CBOOT and delivered to Q1's gate. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN +VC(BOOT), which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low. FDMF6704 Rev. D Additionally, VGS of Q1 is monitored. When VGS(Q1) is discharged low, a secondary adaptive delay is initiated, which results in Q2 being driven ON after 250 ns, regardless of VSWH state. This function is implemented to ensure CBOOT is recharged each switching cycle, particularly for cases where the power convertor is sinking current and VSWH voltage does not fall below the 1 V adaptive threshold. The 250 ns secondary delay is longer than tDTLH. 5 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Description of Operation FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Tristate PWM Input tDTHH tDTLH 90 % 1V DrvL DrvLLOW HDRV to SW Timeout SW 1V tPDHL SW_Low tPDLL 250 ns Hold off Time Figure 4. Adaptive Gate Drive Timing FDMF6704 Rev. D 6 www.fairchildsemi.com VIN = 12V, VCIN = 5V, TA = 25°C unless otherwise noted. 35 12 30 10 8 PLOSS, W ILOAD, A 25 VIN = 12 V VOUT = 1.3 V L = 440 nH 20 15 fSW = 1 MHz 6 4 10 VIN = 12 V VOUT = 1.3 V fSW = 1 MHz L = 440 nH 5 fSW = 350 kHz 2 0 0 0 25 50 75 100 125 0 150 5 10 15 Figure 5. Safe Operating Area 1.40 PLOSS (NORMALIZED) PLOSS (NORMALIZED) 1.12 1.00 1.10 1.08 1.06 1.04 VOUT = 1.3 V IOUT = 30 A L = 440 nH fSW = 350 kHz 1.02 0.90 1.00 0.98 300 400 500 600 700 800 900 1000 6 8 10 fSW, kHz 1.07 1.30 1.04 PLOSS (NORMALIZED) PLOSS (NORMALIZED) 1.40 1.01 0.98 VIN = 12 V VOUT = 1.3 V IOUT = 30 A L = 440 nH fSW = 350 kHz 4.8 16 VIN = 12 V IOUT = 30 A L = 440 nH fSW = 350 kHz 1.20 1.10 1.00 0.90 5.1 5.4 5.7 0.80 0.8 6.0 Driver Supply Voltage, V 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2 Output Voltage, V Figure 9. Power Loss vs. Driver Supply Voltage FDMF6704 Rev. D 14 Figure 8. Power Loss vs. Input Voltage 1.10 0.89 4.5 12 Input Voltage, V Figure 7. Power Loss vs. Switching Frequency 0.92 35 1.14 1.10 0.95 30 1.16 1.20 0.80 200 25 Figure 6. Module Power Loss vs. Output Current VIN = 12 V VOUT = 1.3 V IOUT = 30 A L = 440 nH 1.30 20 ILOAD, A o PCB Temperature, C Figure 10. Power Loss vs. Output Voltage 7 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Typical Characteristics VIN = 12V, VCIN = 5V, TA = 25°C unless otherwise noted. 1.045 45 1.040 40 Driver Supply Current, mA PLOSS (NORMALIZED) 1.035 1.030 1.025 1.020 1.015 1.010 VIN = 12 V VOUT = 1.3 V IOUT = 30 A fSW = 350 kHz 1.005 1.000 0.995 220 VCIN = 5 V 35 30 25 20 15 10 5 275 330 385 0 200 440 300 400 500 600 Figure 11. Power Loss vs. Output Inductance 800 900 1000 Figure 12. Driver Supply Current vs. Frequency 50 60 fSW = 1 MHz 49 55 Driver Supply Current, mA Driver Supply Current, mA 700 fSW, kHz Output Inductance, nH 50 45 40 35 VCIN = 5 V fSW = 1 MHz 48 47 46 45 44 43 42 41 30 4.5 4.8 5.0 5.3 5.5 5.8 40 -50 6.0 -25 0 Driver Supply Voltage, V PWM Tri-state Threshold Voltage, V PWM Tri-state Threshold Voltage, V 5.0 4.0 3.5 3.0 TRI STATE 2.0 1.5 1.0 0.0 4.5 OFF STATE 5.0 5.5 4.5 125 150 6.0 VCIN = 5 V ON STATE 4.0 3.5 3.0 2.5 TRI STATE 2.0 1.5 1.0 0.5 0.0 -40 OFF STATE 25 85 125 150 o Driver Supply Voltage, V Temperature, C Figure 15. PWM Tri-state Threshold Voltage vs. Driver Supply Voltage FDMF6704 Rev. D 100 Figure 14. Driver Supply Current vs. Temperature ON STATE 0.5 75 o 5.0 2.5 50 Temperature, C Figure 13. Driver Supply Current vs. Drive Supply Voltage 4.5 25 Figure 16. PWM Tri-state Threshold Voltage vs. Temperature 8 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Typical Characteristics VIN = 12V, VCIN = 5V, TA = 25°C unless otherwise noted. 2.2 2.0 SMOD# Threshold Voltage, V SMOD# Threshold Voltage, V 2.2 VIH 1.8 1.6 VIL 1.4 1.2 4.8 5.0 5.3 5.5 5.8 2.0 VIH 1.8 1.6 VIL 1.4 1.2 1.0 -50 1.0 4.5 VCIN = 5 V 6.0 -25 0 25 50 75 100 125 150 o Driver Supply Voltage, V Temperature, C Figure 17. SMOD# Threshold Voltage vs. Driver Supply Voltage Figure 18. SMOD# Threshold Voltage vs. Temperature 2.2 2.2 2.0 2.0 DISB# Threshold Voltage, V DISB# Threshold Voltage, V VCIN = 5 V VIH 1.8 1.6 VIL 1.4 1.2 1.0 4.5 4.8 5.0 5.3 5.5 5.8 1.6 VIL 1.4 1.2 1.0 -50 6.0 Driver Supply Voltage, V -25 0 25 50 75 100 125 150 o Temperature, C Figure 19. DISB# Threshold Voltage vs. Driver Supply Voltage FDMF6704 Rev. D VIH 1.8 Figure 20. DISB# Threshold Voltage vs. Temperature 9 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Typical Characteristics Supply Capacitor Selection VCIN Filter For the supply input (VCIN) of the FDMF6704, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. Use at least a 1 F, X7R or X5R capacitor. Keep this capacitor close to the FDMF6704 VCIN and PGND pins. The VDRV pin provides power to the gate drive of the high side and low side power FET. In most cases, it can be connected directly to VCIN, the pin that provides power to the logic section of the driver. For additional noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommended values would be 10 Ohms and 1 F. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 21. A bootstrap capacitance of 100nF, X7R or X5R capacitor is adequate. Typical Application VIN 12V V5V 5V VDRV PWM DISB# SMOD# VIN CGND VCIN BOOT PHASE VSWH CBOOT PGND FDMF6704 VCC EN SMOD# PWM1 PWM Controller PWM2 VDRV PWM DISB# SMOD# VIN CGND VCIN BOOT PHASE VSWH CBOOT PGND FDMF6704 VOUT PWM3 PWM4 CGND Signal GND Power GND VDRV PWM DISB# SMOD# VIN CGND VCIN BOOT PHASE VSWH CBOOT PGND FDMF6704 VDRV PWM DISB# SMOD# VIN CGND VCIN BOOT PHASE VSWH CBOOT PGND FDMF6704 Figure 21. Typical Application FDMF6704 Rev. D 10 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Application Information also be wide enough for high current flow. Other signal routing path, such as PWM IN and BOOT signal, should be considered with care to avoid noise pickup from VSWH copper area. Refer to Figure 22 for module power loss testing method. Power loss calculation are as follows: 3. Output inductor location should be as close as possible to the FDMF6704 for lower power loss due to copper trace. (a) PIN = (VIN x IIN) + (V5V x I5V) (W) (b) POUT = VO x IOUT (W) = PIN - POUT (W) (c) PLOSS (d) Efficiency = 100 x POUT/PIN (%) 4. The PowerTrench® 5 MOSFETs used in the output stage are very effective at minimizing ringing. In most cases, no snubber will be required. If a snubber is used, it should be placed near the FDMF6704. The resistor and capacitor need to be of proper size for power dissipation. PCB Layout Guideline 5. Place ceramic bypass capacitor and boot capacitor as close to VCIN and BOOT pin of FDMF6704 in order to supply stable power. Routing width and length should also be considered. Figure 23 shows a proper layout example of FDMF6704 and critical parts. All of high current flow path, such as VIN, VSWH, VOUT and GND copper, should be short and wide for better and stable current flow, heat radiation and system performance. 6. Ringing at the Boot pin is most effectively controlled by close placement of the capacitor. Do not add an additional Boot to PGND capacitor. This may lead to excess current flow through the Boot diode. Following is a guideline which the PCB designer should consider: 7. Use multiple Vias on each copper area to interconnect each top, inner and bottom layer to help smooth current flow and heat conduction. Vias should be relatively large and of reasonable inductance. 1. Input bypass capacitors should be close to VIN and PGND pin of FDMF6704 to help reduce input current ripple component induced by switching operation. 2. It is critical that the VSWH copper has minimum area for lower switching noise emission. VSWH copper trace should V5V A I5V CVCIN CVDRV IIN A VIN CVIN VDRV VCIN DISB# PWM Input SMOD# DISB# VIN BOOT PWM CBOOT PHASE VSWH SMOD# CGND PGND IOUT V VO A VOUT COUT Figure 22. Power Loss Measurement Block Diagram Figure 23. Typical PCB Layout Example (Top View) FDMF6704 Rev. D 11 www.fairchildsemi.com FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Module Power Loss and Efficiency Measurement and Calculation FDMF6704 High Frequency, High Efficiency, Ultra Compact DrMOS Module Dimensional Outline and Pad layout FDMF6704 Rev. D 12 www.fairchildsemi.com TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I36 © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com