ONSEMI NCP3170

NCP3170
Synchronous PWM
Switching Converter
The NCP3170 is a flexible synchronous PWM Switching Buck
Regulator. The NCP3170 operates from 4.5 V to 18 V, sourcing up to
3 A and is capable of producing output voltages as low as 0.8 V. The
NCP3170 also incorporates current mode control. To reduce the
number of external components, a number of features are internally set
including soft start, power good detection, and switching frequency.
The NCP3170 is currently available in an SOIC−8 package.
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1
Features
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SOIC−8 NB
CASE 751
4.5 V to 18 V Operating Input Voltage Range
90 mW High−Side, 25 mW Low−Side Switch
FMEA Fault Tolerant During Pin Short Test
3 A Continuous Output Current
Fixed 500 kHz and 1 MHz PWM Operation
Cycle−by−Cycle Current Monitoring
1.5% Initial Output Accuracy
Internal 4.6 ms Soft−Start
Short−Circuit Protection
Turn on Into Pre−bias
Power Good Indication
Light Load Efficiency
Thermal Shutdown
These are Pb−Free Devices
MARKING DIAGRAM
8
3170x
ALYW
G
1
3170x
A
L
Y
W
G
PIN CONNECTIONS
Typical Applications
•
•
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•
•
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•
Set Top Boxes
DVD/ Blu−ray™ Drives and HDD
LCD Monitors and TVs
Cable Modems
PCIe Graphics Cards
Telecom/Networking/Datacom Equipment
Point of Load DC/DC Converters
VIN
PGND
VIN
VSW
AGND
FB
EN
COMP
C1
22 mF
VIN
PG
ORDERING INFORMATION
CC
VSW
3.3 V
R1
COMP
FB1
AGND
PGND
C2, C3
22 mF
R2
Package
Shipping†
NCP3170ADR2G
SOIC−8 2500 / Tape & Reel
(Pb−Free)
NCP3170BDR2G
SOIC−8 2500 / Tape & Reel
(Pb−Free)
L1 4.7 mH
NCP3170
PG
(Top View)
Device
EN
= Specific Device Code
x = A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
RC
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 1
1
Publication Order Number:
NCP3170/D
NCP3170
VIN
VDD
EN
UVLO
Power
Control
(PC)
POR
VCW
VCL
Soft Start
Reference
Σ
ORing
Circuit
FB
Driver
Voltage
Clamp
Oscillator
+
+
−
0.030V/A
Current
Sense
Slope
Compensation
Pulse by
Pulse
Current
Limit
S SETQ
R CLRQ
−
VIN
COMP
Soft Start
Complete
998 mV
867 mV
728 mV
PG
logic
PDRV
HS
+
−
VCW
+
−
−
+
VSW
hs
VCL
NDRV
LS
Zero
Current
Detection
Over
Temperature
Protection
VSW
AGND
PGND
Figure 2. NCP3170 Block Diagram
PIN FUNCTION DESCRIPTION
Pin
Pin Name
1
PGND
The power ground pin is the high current path for the device. The pin should be soldered to a large copper
area to reduce thermal resistance. PGND needs to be electrically connected to AGND.
Description
2
VIN
The input voltage pin powers the internal control circuitry and is monitored by multiple voltage comparators.
The VIN pin is also connected to the internal power PMOS switch and linear regulator output. The VIN pin
has high di/dt edges and must be decoupled to ground close to the pin of the device.
3
AGND
The analog ground pin serves as small−signal ground. All small−signal ground paths should connect to the
AGND pin and should also be electrically connected to power ground at a single point, avoiding any high
current ground returns.
4
FB
Inverting input to the OTA error amplifier. The FB pin in conjunction with the external compensation serves to
stabilize and achieve the desired output voltage with current mode compensation.
5
COMP
The loop compensation pin is used to compensate the transconductance amplifier which stabilizes the operation of the converter stage. Place compensation components as close to the converter as possible. Connect
a RC network between COMP and AGND to compensate the control loop.
6
EN
Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the device. Do not leave
it open.
7
PG
Power good is an open drain 500 mA pull down indicating output voltage is within the power good window. If
the power good function is not used, it can be connected to the VSW node to reduce thermal resistance. Do
not connect PG to the VSW node if the application is turning on into pre−bias.
8
VSW
The VSW pin is the connection of the drains of the internal N and P MOSFETS. At switch off, the inductor will
drive this pin below ground as the body diode and the NMOS conducts with a high dv/dt.
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NCP3170
ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 3, unless otherwise noted)
Rating
Symbol
VMAX
VMIN
Unit
VIN
20
−0.3
V
VPAG
0.3
−0.3
V
FB
6
−0.3
V
COMP
6
−0.3
V
EN
VIN + 0.3 V
−0.3
V
PG Voltage
PG
VIN + 0.3 V
−0.3
V
VSW to AGND or PGND
VSW
VIN + 0.3 V
−0.7
V
VSWST
VIN + 10 V
−5
V
Main Supply Voltage Input
Voltage between PGND and AGND
PWM Feedback Voltage
Error Amplifier Voltage
Enable Voltage
VSW to AGND or PGND for 35ns
Junction Temperature (Note 1)
TJ
+150
°C
Operating Ambient Temperature Range
TA
−40 to +85
°C
Storage Temperature Range
Tstg
− 55 to +150
°C
PD
RqJA
RqJC
1.15
87
37.8
W
°C/W
°C/W
RF
260 peak
°C
Thermal Characteristics (Note 2)
SOIC−8 Plastic Package
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance Junction−to−Air
Thermal Resistance Junction−to−Case
Lead Temperature Soldering (10 sec):
Reflow (SMD styles only) Pb−Free (Note 3)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The maximum package power dissipation limit must not be exceeded.
PD +
T J(max) * T A
R qJA
2. The value of qJA is measured with the device mounted on 2in x 2in FR−4 board with 2oz. copper, in a still air environment with TA = 25°C.
The value in any given application depends on the user’s specific board design.
3. 60−180 seconds minimum above 237°C.
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Main Supply Voltage Input
Min
Max
Unit
4.5
18
V
Power Good Pin Voltage
PG
4.5
18
V
Switch Pin Voltage
VSW
−0.3
18
V
Enable Pin Voltage
EN
0
18
V
Comp Pin Voltage
COMP
−0.1
5.5
V
FB
−0.1
5.5
V
Feedback Pin Voltage
Power Ground Pin Voltage
PGND
−0.1
−0.1
V
Junction Temperature Range
TJ
−40
125
°C
Operating Temperature Range
TA
−40
85
°C
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NCP3170
ELECTRICAL CHARACTERISTICS (TA = 25°C, VIN = VEN = 12 V, VOUT = 3.3 V for min/max values unless otherwise noted (Note 7))
Characteristic
Input Voltage Range
Conditions
Min
(Note 5)
4.5
Typ
Max
Unit
18
V
SUPPLY CURRENT
VIN = EN = 12 V VFB = 0.8 V
(Note 5)
1.7
1.7
2.0
2.0
mA
EN = 0 V (Note 5)
13
17
mA
VIN UVLO Threshold
VIN Rising Edge (Note 5)
4.41
V
VIN UVLO Threshold
VIN Falling Edge (Note 5)
4.13
V
Quiescent Supply Current
NCP3170A
NCP3170B
Shutdown Supply Current
UNDER VOLTAGE LOCKOUT
MODULATOR
Oscillator Frequency
NCP3170A
NCP3170B
Maximum Duty Ratio
NCP3170A
NCP3170B
Minimum Duty Ratio
NCP3170A
NCP3170B
Enable = VIN
VIN Soft Start Ramp Time
450
900
500
1000
550
1100
kHz
91
90
96
96
%
VIN = 12 V
6.0
4.0
11
11.5
%
VFB = VCOMP
3.5
6.0
ms
(Note 4)
4.0
6.0
A
TA = 25°C
0.792
4.6
OVER CURRENT
Current Limit
PWM COMPENSATION
VFB Feedback Voltage
Line Regulation
(Note 4)
0.808
1
GM
AOL DC gain
(Note 4)
40
Unity Gain BW (COUT = 10 pF)
(Note 4)
2.0
Input Bias Current (Current Out of FB IB Pin)
0.8
V
%
201
mS
55
dB
MHz
(Note 4)
286
nA
IEAOP Output Source Current
VFB = 0 V
20.1
mA
IEAOM Output Sink Current
VFB = 2 V
21.3
mA
(Note 5)
1.41
V
Power Good High On Threshold
875
mV
Power Good High Off Threshold
859
mV
Power Good Low On Threshold
712
mV
Power Good Low Off Threshold
728
mV
Over Voltage Protection Threshold
998
mV
VIN = 12 V, IPG = 500 mA
0.195
V
High−Side Switch On−Resistance
VIN = 12 V
VIN = 4.5 V
90
100
130
150
mW
Low−Side Switch On−Resistance
VIN = 12 V
VIN = 4.5 V
25
29
35
39
mW
(Notes 4 and 6)
164
°C
43
°C
ENABLE
Enable Threshold
POWER GOOD
Power Good Low Voltage
PWM OUTPUT STAGE
THERMAL SHUTDOWN
Thermal Shutdown
Hysteresis
4.
5.
6.
7.
Guaranteed by design
Ambient temperature range of −40°C to +85°C.
This is not a protection feature.
The device is not guaranteed to operate beyond the maximum operating ratings.
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NCP3170
TYPICAL PERFORMANCE CHARACTERISTICS
(Circuit from Figure 1, TA = 25°C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified)
Figure 3. Light Load (DCM) Operation 1 ms/DIV
Figure 4. Full Load (CCM) Operation 1 ms/DIV
Figure 5. Start−Up into Full Load 1 ms/DIV
Figure 6. Short−Circuit Protection 200 ms /DIV
Figure 7. 50% to 100% Load Transient 100 ms/DIV
Figure 8. 3.3 V Turn on into 1 V Pre−Bias 1 ms /DIV
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NCP3170
TYPICAL PERFORMANCE CHARACTERISTICS
(Circuit from Figure 1, TA = 25°C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified)
30
2.1
24
21
18
15
Input Voltage = 12 V
12
9
6
3
0
−50 −30
10
30
50
70
90
110
Input Voltage = 4.5 V
1.5
−10
10
30
50
70
90
110 130
Figure 10. NCP3170 Enabled Current vs.
Temperature
503
Input Voltage = 18 V
SWITCHING FREQUENCY (kHz)
BANDGAP REFERENCE (mV)
1.6
Figure 9. ICC Shut Down Current vs.
Temperature
803
Input Voltage = 12 V
801
800
Input Voltage = 4.5 V
799
798
797
−50 −30
−10
10
30
50
70
90
110
502
Input Voltage = 18 V
Input Voltage = 4.5 V
501
Input Voltage = 12 V
500
499
498
497
496
−50 −30
130
−10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Bandgap Reference Voltage vs.
Temperature
Figure 12. Switching Frequency vs.
Temperature
880
TRIP VOLTAGE AT FB PIN (mV)
735
TRIP VOLTAGE AT FB PIN (mV)
1.7
TEMPERATURE (°C)
804
Under Voltage Protection Rising
725
720
715
1.8
TEMPERATURE (°C)
805
730
Input Voltage = 12 V
1.3
−50 −30
130
806
802
1.9
1.4
Input Voltage = 4.5 V
−10
Input Voltage = 18 V
2.0
Input Voltage = 18 V
CURRENT DRAW (mA)
CURRENT DRAW (mA)
27
Under Voltage Protection Falling
710
705
−50 −30
−10
10
30
50
70
90
110
875
Over Voltage Protection Falling
870
865
Over Voltage Protection Rising
860
855
−50 −30
130
−10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Input Under Voltage Protection at
12 V vs. Temperature
Figure 14. Input Over Voltage Protection at
12 V vs. Temperature
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NCP3170
TYPICAL PERFORMANCE CHARACTERISTICS
(Circuit from Figure 1, TA = 25°C, VIN = VEN = 12 V, VOUT = 3.3 V unless otherwise specified)
40
LOW SIDE MOSFET RDS(on) (mW)
HIGH SIDE MOSFET RDS(on) (mW)
130
120
110
Input Voltage = 4.5 V
100
90
Input Voltage = 12 V, 18 V
80
70
60
−50 −30
−10
10
30
50
70
90
110
Input Voltage = 4.5 V
25
Input Voltage = 12 V, 18 V
20
−10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. High Side MOSFET RDS(on) vs.
Temperature
Figure 16. Low Side MOSFET RDS(on) vs.
Temperature
1001.5
TRIP VOLTAGE AT FB PIN (mV)
Input Voltage = 12 V
Input Voltage = 4.5 V
205
200
Input Voltage = 18 V
195
190
185
180
−50 −30
−10
10
30
50
70
90
110
130
1001.0
1000.5
1000.0
999.5
999.0
Input Voltage = 4.5 V
998.5
Input Voltage = 18 V
998.0
Input Voltage = 12 V
997.5
997.0
996.5
−50 −30
−10
10
30
50
70
90
110 130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Transconductance vs. Temperature
Figure 18. Over Voltage Protection vs.
Temperature
4.45
TRIP VOLTAGE AT FB PIN (mV)
TRANSCONDUCTANCE (mS)
30
15
−50 −30
130
215
210
35
4.40
Input Under Voltage Protection Rising
4.35
4.30
4.25
4.20
4.15
Input Under Voltage Protection Falling
4.10
4.05
−50 −30
−10
10
30
50
70
90
110
130
TEMPERATURE (°C)
Figure 19. Input Under Voltage Protection vs.
Temperature
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NCP3170
NCP3170A Efficiency and Thermal Derating
100
100
90
90
70
Vo = 1.8 V
60
80
Vo = 5 V
Vo = 3.3 V
EFFICIENCY (%)
EFFICIENCY (%)
80
Vo = 1.2 V
50
40
30
20
0
0
1
2
Vo = 1.8 V
Vo = 1.2 V
60
Vo = 3.3 V
50
40
30
20
12 V, 500 kHz
Efficiency
10
70
5 V, 500 kHz
Efficiency
10
0
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 20. Efficiency (VIN = 12 V) vs. Load
Current
Figure 21. Efficiency (VIN = 5 V) vs. Load Current
Thermal derating curves for the SOIC−8 package part under typical input and output conditions based on the evaluation board.
The ambient temperature is 25°C with natural convection (air speed < 50LFM) unless otherwise specified.
5
IOUT, AMBIENT TEMPERATURE (°C)
IOUT, AMBIENT TEMPERATURE (°C)
5
4
1.2 V, 1.8 V,
3.3 V
3
2
1
0
25
35
45
55
65
75
TA, AMBIENT TEMPERATURE (°C)
85
4
1.2 V, 1.8 V,
3.3 V, 5.0 V
3
2
1
0
25
Figure 22. 500 kHz Derating Curves at 5 V
35
45
55
65
75
TA, AMBIENT TEMPERATURE (°C)
Figure 23. 500 kHz Derating Curves at 12 V
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NCP3170
NCP3170B Efficiency and Thermal Derating
100
100
90
90
80
Vo = 3.3 V
70
Vo = 5 V
EFFICIENCY (%)
EFFICIENCY (%)
80
Vo = 1.8 V
60
Vo = 1.2 V
50
40
30
20
0
0
1
2
Vo = 1.8 V
Vo = 1.2 V
60
Vo = 3.3 V
50
40
30
20
12 V, 1 MHz
Efficiency
10
70
5 V, 1 MHz
Efficiency
10
0
3
0
1
2
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 24. 12 V, 1 MHz Efficiency
Figure 25. 5 V, 1 MHz Efficiency
Thermal derating curves for the SOIC−8 package part under typical input and output conditions based on the evaluation board.
The ambient temperature is 25°C with natural convection (air speed < 50 LFM) unless otherwise specified.
5
IOUT, AMBIENT TEMPERATURE (°C)
IOUT, AMBIENT TEMPERATURE (°C)
5
4
1.2 V,
1.8 V
3
3.3 V
2
1
0
25
35
45
55
65
75
85
4
1.2 V,
1.8 V
3
3.3 V
2
5.0 V
1
0
25
TA, AMBIENT TEMPERATURE (°C)
35
45
55
65
75
85
TA, AMBIENT TEMPERATURE (°C)
Figure 26. 1 MHz Derating Curves at 5 V Input
Figure 27. 1 MHz Derating Curves at 12 V Input
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NCP3170
DETAILED DESCRIPTION
The NCP3170 is a current−mode, step down regulator
with an integrated high−side PMOS switch and a low−side
NMOS switch. It operates from a 4.5 V to 18 V input voltage
range and supplies up to 3 A of load current. The duty ratio
can be adjusted from 8% to 92% allowing a wide output
voltage range. Features include enable control, Power−On
Reset (POR), input under voltage lockout, fixed internal soft
start, power good indication, over voltage protection, and
thermal shutdown.
The enable pin can be used to delay a turn on by
connecting a capacitor as shown in Figure 30.
4.5 V − 18 V
Rbias
EN
NCP3170
C1DLY
Enable and Soft−Start
An internal input voltage comparator not shown in
Figure 28 will force the part to disable below the minimum
input voltage of 4.13 V. The input under voltage disable
feature is used to prevent improper operation of the
converter due to insufficient voltages. The converter can be
turned on by tying the enable pin high and the part will
default to be input voltage enabled. The enable pin should
never be left floating.
4.5 V − 18 V
VIN
C1IN
AGND
Figure 30. Delay Enable
If the designer would like to add hysteresis to the enable
threshold it can be added by use of a bias resistor to the
output. The hysteresis is created once soft start has initiated.
With the output voltage rising, current flows into the enable
node, raising the voltage. The thresholds for enable as well
as hysteresis can be calculated using Equation 1.
VIN
C1IN
VIN HYS + VIN Start * EN TH ) R1 UV
EN
ƪ
NCP3170
V OUT * EN TH
ƪ
AGND
VIN Start + EN TH
1)
Figure 28. Input Voltage Enable
ENTH
VINSTART
R1UV
R2UV
R3UV
VOUT
If an adjustable Under Voltage Lockout (UVLO)
threshold is required, the EN pin can be used. The trip
voltage of the EN pin comparator is 1.38 V typical. Upon
application of an input voltage greater than 4.41 V, the VIN
UVLO will release and the enable will be checked to
determine if switching can commence. Once the 1.38 V trip
voltage is crossed, the part will enable and the soft start
sequence will initiate. If large resistor values are used, the
EN pin should be bypassed with a 1 nF capacitor to prevent
coupling problems from the switch node.
4.5 V − 18 V
=
=
=
=
=
=
R3 UV
R1 UV
4.5 V − 18 V
R2 UV
(eq. 1)
ǒR2UV ) R3UVǓ
R2 UV
R3 UV
ƫ
VIN
C1IN
R1UV
VIN
EN
R3UV
R1UV
Vout
C1UV
ƫ
EN TH
Enable Threshold
Input Voltage Start Threshold
High Side Resistor
Low Side Resistor
Hysteresis Bias Resistor
Regulated Output Voltage
C1IN
EN
*
NCP3170
R2UV
AGND
NCP3170
R2UV
Figure 31. Added Hysteresis to the Enable UVLO
AGND
Figure 29. Input Under Voltage Lockout Enable
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NCP3170
pin is held low until the FB pin voltage surpasses the internal
reference voltage, at which time the COMP pin is allowed
to respond to the OTA error signal. Since the bottom of the
PWM ramp is at 0.6 V there will be a slight delay between
the time the internal reference voltage passes the FB voltage
and when the part starts to switch. Once the COMP error
signal intersects with the bottom of the ramp, the high side
switch is turned on followed by the low side switch. After the
internal reference voltage has surpassed the FB voltage, soft
start proceeds normally without output voltage discharge.
The part can be enabled with standard TTL or high voltage
logic by using the configuration below.
4.5 V − 18 V
VIN
C1IN
R1LOG
EN
C1LOG
R2LOG
NCP3170
Power Good
AGND
The output voltage of the buck converter is monitored at
the feedback pin of the output power stage. Two
comparators are placed on the feedback node of the OTA to
monitor the operating window of the feedback voltage as
shown in Figure 34. All comparator outputs are ignored
during the soft start sequence as soft start is regulated by the
OTA since false trips would be generated. Further, the PG
pin is held low until the comparators are evaluated. PG state
does not affect the switching of the converter. After the soft
start period has ended, if the feedback is below the reference
voltage of comparator 1 (VFB < 0.726), the output is
considered operational undervoltage (OUV). The device
will indicate the under voltage situation by the PG pin
remaining low with a 100 kW pull−up resistance. When the
feedback pin voltage rises between the reference voltages of
comparator 1 and comparator 2 (0.726 < VFB < 0.862), then
the output voltage is considered power good and the PG pin
is released. Finally, if the feedback voltage is greater than
comparator 2 (VFB > 0.862), the output voltage is considered
operational overvoltage (OOV). The OOV will be indicated
by the PG pin remaining low. A block diagram of the OOV
and OUV functionality as well as a graphical representation
of the PG pin functionality is shown in Figures 34
through 36.
Figure 32. Logic Turn−on
The enable can also be used for power sequencing in
conjunction with the Power Good (PG) pin as shown in
Figure 33. The enable pin can either be tied to the output
voltage of the master voltage or tied to the input voltage with
a resistor to the PG pin of the master regulator.
4.5 V − 18 V
VIN
EN
PG
VSW
NCP3170
Vo1
FB
Vo1
AGND
Vo2
4.5 V − 18 V
VIN
VSW
Vo2
EN
NCP3170
FB
AGND
FB
Figure 33. Enable Two Converter Power Sequencing
800 mV
−
Once the part is enabled, the internal reference voltage is
slewed from ground to the set point of 800 mV. The slewing
process occurs over a 4.5 ms period, reducing the current
draw from the upstream power source, reducing stress on
internal MOSFETS, and ensuring the output inductor does
not saturate during start−up.
12 V
+
comp 2
+
862 mV
−
726 mV
+
100kW
SOFT
Start
Complete
PG
−
comp 1
Figure 34. OOV and OUV System
Pre−Bias Start−up
When starting into a pre−bias load, the NCP3170 will not
discharge the output capacitors. The soft start begins with
the internal reference at ground. Both the high side switch
and low side switches are turned off. The internal reference
slowly raises and the OTA regulates the output voltage to the
divided reference voltage. In a pre−biased condition, the
voltage at the FB pin is higher than the internal reference
voltage, so the OTA will keep the COMP voltage at ground
potential. As the internal reference is slewed up, the COMP
Hysteresis = 14 mV
OOV
Voov = 862 mV
Power Good
Hysteresis = 14 mV
Vref = 0.8 V
Vouv = 726 mV
OUV
Figure 35. OOV and OUV Window
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NCP3170
Protection Features
0.862 V
Over Current Protection
0.8 V
Current is limited to the load on a pulse by pulse basis.
During each high side on period, the current is compared
against an internally set limit. If the current limit is
exceeded, the high side and low side MOSFETS are shutoff
and no pulses are issued for 13.5 ms. During that time, the
output voltage will decay and the inductor current will
discharge. After the discharge period, the converter will
initiate a soft start. If the load is not released, the current will
build in the inductor until the current limit is exceeded, at
which time the high side and low side MOSFETS will be
shut off and the process will continue. If the load has been
released, a normal soft start will commence and the part will
continue switching normally until the current limit is
exceeded.
0.726
FB Voltage
Softstart Complete
Power Good
Figure 36. OOV and OUV Diagram
If the power good function is not used, it can be connected
to the VSW node to reduce thermal resistance. Do not
connect PG to the VSW node if the application is turning on
into pre−bias.
Switching Frequency
The NCP3170 switching frequency is fixed and set by an
internal oscillator. The practical switching frequency could
range from 450 kHz to 550 kHz for the NCP3170A and
900 kHz to 1.1 MHz for the NCP3170B due to device
variation.
Switch
Node
13.5 ms Hold Time
Current Limit
Inductor
Current
Light Load Operation
Light load operation is generally a load that is 1mA to
300 mA where a load is in standby mode and requires very
little power. During light load operation, the regulator
emulates the operation of a non−synchronous buck
converter and the regulator is allowed to skip pulses. The
non−synchronous buck emulation is accomplished by
detecting the point at which the current flowing in the
inductor goes to zero and turning the low side switch off. At
the point when the current goes to zero, if the low side switch
is not turned off, current would reverse, discharging the
output capacitor. Since the low side switch is shutoff, the
only conduction path is through the body diode of the low
side MOSFET, which is back biased. Unlike traditional
synchronous buck converters, the current in the inductor
will become discontinuous. As a result, the switch node will
oscillate with the parasitic inductances and capacitances
connected to the switch node. The OTA will continue to
regulate the output voltage, but will skip pulses based on the
output load shown in Figure 37.
Figure 38. Over Current Protection
Thermal Shutdown
The thermal limit, while not a protection feature, engages
at 150°C in case of thermal runaway. When the thermal
comparator is tripped at a die temperature of 150°C, the part
must cool to 120°C before a restart is allowed. When thermal
trip is engaged, switching ceases and high side and low side
MOSFETs are driven off. Further, the power good indicator
will pull low until the thermal trip has been released. Once
the die temperature reaches 120°C the part will reinitiate
soft−start and begin normal operation.
Switch
Node
Output
Voltage
6 ms = 166 kHz
Thermal
Comparator
2 ms = 50 kHz
Switch
Node
150C
0V
Inductor
Current
Temperature
Figure 39. Over Temperature Shutdown
Zero Current Point
0A
Feedback
Voltage
COMP
Voltage
120C
IC
Reference Votlage
Ramp Threshold
Figure 37. Light Load Operation
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NCP3170
Over Voltage Protection
Upon the completion of soft start, the output voltage of the
buck converter is monitored at the FB pin of the output
power stage. One comparator is placed on the feedback node
to provide over voltage protection. In the event an over
voltage is detected, the high side switch turns off and the low
side switch turns on until the feedback voltage falls below
the OOV threshold. Once the voltage has fallen below the
OOV threshold, switching continues normally as displayed
in Figure 40.
1.0 V
0.862 V
Figure 41. NCP3170A Safe Operating Area
0.800 V
0.726 V
FB Voltage
Softstart
Complete
Power
Good
Low Side
Switch
Figure 40. Over Voltage Low Side Switch Behavior
Duty Ratio
The duty ratio can be adjusted from 8% to 92% allowing
a wide output voltage range. The low 8% duty ratio limit will
restrict the PWM operation. For example if the application
is converting to 1.2 V the converter will perform normally
if the input voltage is below 15.5 V. If the input voltage
exceeds 15.5 V while supplying 1.2 V output voltage the
converter can skip pulses during operation. The skipping
pulse operation will result in higher ripple voltage than when
operating in PWM mode. Figure 41 and 42 below shows the
safe operating area for the NCP3170A and B respectively.
While not shown in the safe operating area graph, the output
voltage is capable of increasing to the 93% duty ratio
limitation providing a high output voltage such as 16 V. If
the application requires a high duty ratio such as converting
from 14 V to 10 V the converter will operate normally until
the maximum duty ratio is reached. For example, if the input
voltage were 16 V and the user wanted to produce the
highest possible output voltage at full load, a good rule of
thumb is to use 80% duty ratio. The discrepancy between the
usable duty ratio and the actual duty ratio is due to the
voltage drops in the system, thus leading to a maximum
output voltage of 12.8 V rather than 14.8 V. The actual
achievable output to input voltage ratio is dependent on
layout, component selection, and acceptable output voltage
tolerance.
Figure 42. NCP3170B Safe Operating Area
Design Procedure
When starting the design of a buck regulator, it is important
to collect as much information as possible about the behavior
of the input and output before starting the design.
ON Semiconductor has a Microsoft Excel® based design
tool available online under the design tools section of the
NCP3170 product page. The tool allows you to capture your
design point and optimize the performance of your regulator
based on your design criteria.
DESIGN PARAMETERS
Design Parameter
Input Voltage (VIN)
Output Voltage (VOUT)
9 V to 16 V
3.3 V
Input Ripple Voltage (VCCRIPPLE)
200 mV
Output Ripple Voltage (VOUTRIPPLE)
20 mV
Output Current Rating (IOUT)
3A
Operating Frequency (FSW)
500 kHz
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Example Value
NCP3170
The buck converter produces input voltage (VIN) pulses
that are LC filtered to produce a lower DC output voltage
(VOUT). The output voltage can be changed by modifying
the on time relative to the switching period (T) or switching
frequency. The ratio of high side switch on time to the
switching period is called duty ratio (D). Duty ratio can also
be calculated using VOUT, VIN, the Low Side Switch Voltage
Drop (VLSD), and the High Side Switch Voltage Drop
(VHSD).
D+
T OFF
T
V IN * V HSD ) V LSD
V OUT
D+
=
=
=
=
=
=
=
=
=
T
(1 * D ) +
V OUT ) V LSD
D+
D
FSW
T
TOFF
TON
VIN
VHSD
VLSD
VOUT
T ON
1
T
V IN
³ 27.5% +
17
(eq. 2)
15
(eq. 3)
13
[
3.3 V
(eq. 4)
12 V
Duty ratio
Switching frequency
Switching period
High side switch off time
High side switch on time
Input voltage
High side switch voltage drop
Low side switch voltage drop
Output voltage
4.7 mH +
V OUT
I OUT
ra
F SW
34%
4.7 mH
4.4 V
10
500 kHz
13
16 19 22 25 28 31 34
RIPPLE CURRENT RATIO (%)
37
40
Figure 43. Inductance vs. Current Ripple Ratio
When selecting an inductor, the designer must not exceed
the current rating of the part. To keep within the bounds of
the part’s maximum rating, a calculation of the RMS current
and peak current are required.
I RMS + I OUT
3.01 A + 3 A
IOUT
IRMS
ra
(eq. 5)
Ǹ1 ) ra12 ³
2
Ǹ
= Output current
= Inductor RMS current
= Ripple current ratio
3.51 A + 3 A
IOUT
IPK
ra
(eq. 6)
(1 * 27.5%)
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14
(eq. 7)
34% 2
1)
³
12
ǒ1 ) raǓ ³
I PK + I OUT
(1 * D ) ³
12 V
3.0 A
7V
7
1
DI
= Ripple current
IOUT
= Output current
ra
= Ripple current ratio
Using the ripple current rule of thumb, the user can
establish acceptable values of inductance for a design using
Equation 6.
L OUT +
18 V
9
3
When selecting an inductor, the designer may employ a
rule of thumb for the design where the percentage of ripple
current in the inductor should be between 10% and 40%.
When using ceramic output capacitors, the ripple current can
be greater because the ESR of the output capacitor is smaller,
thus a user might select a higher ripple current. However,
when using electrolytic capacitors, a lower ripple current
will result in lower output ripple due to the higher ESR of
electrolytic capacitors. The ratio of ripple current to
maximum output current is given in Equation 5.
DI
I OUT
11
5
Inductor Selection
ra +
= Duty ratio
= Switching frequency
= Output current
= Output inductance
= Ripple current ratio
19
INDUCTANCE (mH)
F SW +
D
FSW
IOUT
LOUT
ra
2
ǒ
Ǔ
34%
1)
2
= Output current
= Inductor peak current
= Ripple current ratio
(eq. 8)
NCP3170
A standard inductor should be found so the inductor will
be rounded to 4.7 mH. The inductor should support an RMS
current of 3.01 A and a peak current of 3.51 A. A good
design practice is to select an inductor that has a saturation
current that exceeds the maximum current limit with some
margin.
The final selection of an output inductor has both
mechanical and electrical considerations. From a
mechanical perspective, smaller inductor values generally
correspond to smaller physical size. Since the inductor is
often one of the largest components in the regulation system,
a minimum inductor value is particularly important in space
constrained applications. From an electrical perspective, the
maximum current slew rate through the output inductor for
a buck regulator is given by Equation 9.
SlewRate LOUT +
1.85
LOUT
VIN
VOUT
V IN * V OUT
L OUT
LP CU_DC + I RMS
61 mW +
1.02 A +
D
FSW
IPP
LOUT
VOUT
=
=
=
=
=
L OUT
3.3 V
4.7 mH
(1 * D )
F SW
6.73 mW
LP tot + LP CU_DC ) LP CU_AC ) LP Core ³
67 mW + 61 mW ) 5 mW ) 1 mW
LPCore
LPCU_AC
LPCU_DC
LPtot
(eq. 9)
=
=
=
=
(eq. 12)
Inductor core power dissipation
Inductor AC power dissipation
Inductor DC power dissipation
Total inductor losses
Output Capacitor Selection
The important factors to consider when selecting an
output capacitor are DC voltage rating, ripple current rating,
output ripple voltage requirements, and transient response
requirements.
The output capacitor must be able to operate properly for
the life time of a product. When selecting a capacitor it is
important to select a voltage rating that is de−rated to the
guaranteed operating life time of a product. Further, it is
important to note that when using ceramic capacitors, the
capacitance decreases as the voltage applied increases; thus
a ceramic capacitor rated at 100 mF 6.3 V may measure
100 mF at 0 V but measure 20 mF with an applied voltage of
3.3 V depending on the type of capacitor selected.
The output capacitor must be rated to handle the ripple
current at full load with proper derating. The capacitor RMS
ratings given in datasheets are generally for lower switching
frequencies than used in switch mode power supplies, but a
multiplier is given for higher frequency operation. The RMS
current for the output capacitor can be calculated below:
Equation 9 implies that larger inductor values limit the
regulator’s ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply the load current until the
inductor current reaches the output load current level.
Reduced inductance to increase slew rates results in larger
values of output capacitance to maintain tight output voltage
regulation. In contrast, smaller values of inductance increase
the regulator’s maximum achievable slew rate and decrease
the necessary capacitance at the expense of higher ripple
current. The peak−to−peak ripple current for NCP3170 is
given by the following equation:
V OUT
(eq. 11)
The core losses and AC copper losses will depend on the
geometry of the selected core, core material, and wire used.
Most vendors will provide the appropriate information to
make accurate calculations of the power dissipation at which
point the total inductor losses can be captured by the
equation below:
= Output inductance
= Input voltage
= Output voltage
I PP +
3.01 2
DCR ³
DCR
= Inductor DC resistance
IRMS
= Inductor RMS current
LPCU_DC = Inductor DC power dissipation
³
12 V * 3.3 V
A
+
ms
4.7 mH
2
³
(1 * 27.5%)
(eq. 10)
500 kHz
Duty ratio
Switching frequency
Peak−to−peak current of the inductor
Output inductance
Output voltage
CO RMS + I OUT
ra
³
Ǹ12
34%
0.294 A + 3.0 A
Ǹ12
CoRMS
IOUT
ra
From Equation 10, it is clear that the ripple current
increases as LOUT decreases, emphasizing the trade−off
between dynamic response and ripple current.
The power dissipation of an inductor falls into two
categories: copper and core losses. Copper losses can be
further categorized into DC losses and AC losses. A good
first order approximation of the inductor losses can be made
using the DC resistance as shown below:
(eq. 13)
= Output capacitor RMS current
= Output current
= Ripple current ratio
The maximum allowable output voltage ripple is a
combination of the ripple current selected, the output
capacitance selected, the Equivalent Series Inductance
(ESL), and Equivalent Series Resistance (ESR).
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NCP3170
The main component of the ripple voltage is usually due
to the ESR of the output capacitor and the capacitance
selected, which can be calculated as shown in Equation 14:
ǒ
V ESR_C + I OUT
ra
10.89 mV + 3
34%
Ǔ
1
CO ESR )
8
F SW
ǒ
8
500 kHz
5 mW )
C OUT
1
DV OUT−ESR + I TRAN
7.5 mV + 1.5 A
CoESR
³
ITRAN
DVOUT_ESR
Ǔ
44 mF
CoESR
= Output capacitor ESR
COUT
= Output capacitance
FSW
= Switching frequency
IOUT
= Output current
ra
= Ripple current ratio
VESR_C = Ripple voltage from the capacitor
V ESLON +
D
1.84 mV +
133.5 mV +
COUT
D
FSW
FCROSS
ITRAN
LOUT
VIN
VOUT
DVOUT_DIS
³
(eq. 15)
0.7 mV +
27.5%
ESL
I PP
F SW
(1 * D )
1 nH
1.1 A
ǒITRANǓ
2
F CROSS
(1.5)
2
=
=
=
=
=
=
=
=
=
2
50 kHz
2
L OUT
C OUT
F SW
ǒVIN * VOUTǓ
4.7 mH
500 kHz
44 mF
ǒ12 V * 3.3 VǓ
³
(eq. 18)
Output capacitance
Duty ratio
Switching frequency
Loop cross over frequency
Output transient current
Output inductor value
Input voltage
Output voltage
Voltage deviation of VOUT due to the
effects of capacitor discharge
In a typical converter design, the ESR of the output
capacitor bank dominates the transient response. Please note
that DVOUT_DIS and DVOUT_ESR are out of phase with each
other, and the larger of these two voltages will determine the
maximum deviation of the output voltage (neglecting the
effect of the ESL). It is important to note that the converters
frequency response will change when the NCP3170 is
operating in synchronous mode or non−synchronous mode
due to the change in plant response from CCM to DCM. The
effect will be a larger transient voltage excursion when
transitioning from no load to full load quickly.
1 nH @ 1.01 A @ 500 kHz
V ESLOFF +
D
ESL
FSW
IPP
F SW
= Output capacitor Equivalent Series
Resistance
= Output transient current
= Voltage deviation of VOUT due to the
effects of ESR
DV OUT−DIS +
The impedance of a capacitor is a function of the
frequency of operation. When using ceramic capacitors, the
ESR of the capacitor decreases until the resonant frequency
is reached, at which point the ESR increases; therefore the
ripple voltage might not be what one expected due to the
switching frequency. Further, the method of layout can add
resistance in series with the capacitance, increasing ripple
voltage.
The ESL of capacitors depends on the technology chosen,
but tends to range from 1 nH to 20 nH, where ceramic
capacitors have the lowest inductance and electrolytic
capacitors have the highest. The calculated contributing
voltage ripple from ESL is shown for the switch on and
switch off below:
I PP
(eq. 17)
5 mW
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is given by
the following equation:
(eq. 14)
ESL
CO ESR ³
³
(eq. 16)
500 kHz
(1 * 27.5%)
Input Capacitor Selection
= Duty ratio
= Capacitor inductance
= Switching frequency
= Peak−to−peak current
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize losses and input voltage
ripple. The RMS value of the input ripple current is:
ǸD (1 * D) ³
Iin
+I
The output capacitor is a basic component for fast
response of the power supply. For the first few microseconds
of a load transient, the output capacitor supplies current to
the load. Once the regulator recognizes a load transient, it
adjusts the duty ratio, but the current slope is limited by the
inductor value.
During a load step transient, the output voltage initially
drops due to the current variation inside the capacitor and the
ESR (neglecting the effect of the ESL).
RMS
OUT
1.34 A + 3 A
D
IinRMS
IOUT
Ǹ27.5%
(eq. 19)
(1 * 27.5%)
= Duty ratio
= Input capacitance RMS current
= Load current
The equation reaches its maximum value with D = 0.5 at
which point the input capacitance RMS current is half the
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NCP3170
output current. Loss in the input capacitors can be calculated
with the following equation:
P CIN + CIN ESR
IinRMS
PCIN
PDS
PRR
2
(eq. 20)
ǒ1.34 AǓ 2
18 mW + 10 mW
CINESR
ǒIinRMSǓ
P SW_TOT + P SW ) P DS ) P RR
The first term for total switching losses from Equation 24
are the losses associated with turning the high−side
MOSFET on and off and the corresponding overlap in drain
voltage and current.
Due to large di/dt through the input capacitors, electrolytic
or ceramics should be used. If a tantalum capacitor must be
used, it must be surge protected, otherwise capacitor failure
could occur.
P SW + P TON ) P TOFF +
PCOND
PD_HS
PSW_TOT
1
2
ǒIOUT
V IN
ǒtRISE ) tFALLǓ
Power MOSFET Dissipation
Power dissipation, package size, and the thermal
environment drive power supply design. Once the
dissipation is known, the thermal impedance can be
calculated to prevent the specified maximum junction
temperatures from being exceeded at the highest ambient
temperature.
Power dissipation has two primary contributors:
conduction losses and switching losses. The high−side
MOSFET will display both switching and conduction
losses. The switching losses of the low side MOSFET will
not be calculated as it switches into nearly zero voltage and
the losses are insignificant. However, the body diode in the
low−side MOSFET will suffer diode losses during the
non−overlap time of the gate drivers.
Starting with the high−side MOSFET, the power
dissipation can be approximated from:
P D_HS + P COND ) P SW_TOT
= High side MOSFET drain to source losses
= High side MOSFET reverse recovery
losses
= High side MOSFET switching losses
= High side MOSFET total switching losses
PSW
PSW_TOT
= Input capacitance Equivalent Series
Resistance
= Input capacitance RMS current
= Power loss in the input capacitor
(eq. 24)
FSW
IOUT
PSW
PTON
PTOFF
tFALL
tRISE
VIN
=
=
=
=
=
=
=
=
F SWǓ
(eq. 25)
Switching frequency
Load current
High side MOSFET switching losses
Turn on power losses
Turn off power losses
MOSFET fall time
MOSFET rise time
Input voltage
When calculating the rise time and fall time of the high
side MOSFET, it is important to know the charge
characteristic shown in Figure 44.
(eq. 21)
= Conduction losses
= Power losses in the high side MOSFET
= Total switching losses
Vth
The first term in Equation 21 is the conduction loss of the
high−side MOSFET while it is on.
ǒ
Ǔ
P COND + I RMS_HS
2
R DS(on)_HS
(eq. 22)
IRMS_HS
= RMS current in the high side MOSFET
RDS(ON)_HS = On resistance of the high side MOSFET
PCOND
= Conduction power losses
Figure 44. High Side MOSFET Total Charge
Using the ra term from Equation 5, IRMS becomes:
I RMS_HS + I OUT
D
ra
IOUT
IRMS_HS
=
=
=
=
Ǹ ǒ
D
1)
Ǔ
ra 2
12
t RISE +
(eq. 23)
IG1
QGD
RHSPU
RG
tRISE
VCL
VTH
Duty ratio
Ripple current ratio
Output current
High side MOSFET RMS current
The second term from Equation 21 is the total switching
loss and can be approximated from the following equations.
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Q GD
I G1
+
Q GD
ǒVCL * VTHǓńǒRHSPU ) RGǓ
(eq. 26)
= Output current from the high−side gate drive
= MOSFET gate to drain gate charge
= Drive pull up resistance
= MOSFET gate resistance
= MOSFET rise time
= Clamp voltage
= MOSFET gate threshold voltage
NCP3170
t FALL +
IG2
QGD
RG
RHSPD
tFALL
VCL
VTH
Q GD
I G2
+
Q GD
ǒVCL * VTHǓńǒRHSPD ) RGǓ
I RMS_LS + I OUT
(eq. 27)
D
IOUT
IRMS_LS
ra
= Output current from the low−side gate
drive
= MOSFET gate to drain gate charge
= MOSFET gate resistance
= Drive pull down resistance
= MOSFET fall time
= Clamp voltage
= MOSFET gate threshold voltage
COSS
FSW
PDS
VIN
=
=
=
=
1
2
V IN 2
C OSS
F SW
P BODY + V FD
FSW
IOUT
NOLHL
(eq. 28)
NOLLH
MOSFET output capacitance at 0 V
Switching frequency
MOSFET drain to source charge losses
Input voltage
PBODY
VFD
Finally, the loss due to the reverse recovery time of the
body diode in the low−side MOSFET is shown as follows:
P RR + Q RR
FSW
PRR
QRR
VIN
V IN
F SW
(eq. 30)
= Low side MOSFET body diode losses
= Low side MOSFET conduction losses
= Low side MOSFET losses
Conduction loss in the low−side MOSFET is described as
follows:
ǒ
Ǔ
P COND + I RMS_LS
2
R DS(on)_LS
2
(eq. 32)
Duty ratio
Load current
RMS current in the low side
Ripple current ratio
I OUT
F SW
ǒNOLLH ) NOLHLǓ
(eq. 33)
= Switching frequency
= Load current
= Dead time between the high−side
MOSFET turning off and the low−side
MOSFET turning on, typically 30 ns
= Dead time between the low−side MOSFET
turning off and the high−side MOSFET
turning on, typically 30 ns
= Low−side MOSFET body diode losses
= Body diode forward voltage drop typically
0.92 V
To create a stable power supply, the compensation network
around the transconductance amplifier must be used in
conjunction with the PWM generator and the power stage.
Since the power stage design criteria is set by the
application, the compensation network must correct the
overall output to ensure stability. The NCP3170 is a current
mode regulator and as such there exists a voltage loop and
a current loop. The current loop causes the inductor to act
like a current source which governs most of the
characteristics of current mode control. The output inductor
and capacitor of the power stage form a double pole but
because the inductor is treated like a current source in closed
loop, it becomes a single pole system. Since the feedback
loop is controlling the inductor current, it is effectively like
having a current source feeding a capacitor; therefore the
pole is controlled by the load and the output capacitance. A
table of compensation values for 500 kHz and 1 MHz is
provided below for two 22 mF ceramic capacitors. The table
also provides the resistor value for CompCalc at the defined
operating point.
The low−side MOSFET turns on into small negative
voltages so switching losses are negligible. The low−side
MOSFET’s power dissipation only consists of conduction
loss due to RDS(on) and body diode loss during non−overlap
periods.
PBODY
PCOND
PD_LS
ǒ1 ) ra12 Ǔ
Compensation Network
(eq. 29)
= Switching frequency
= High side MOSFET reverse recovery
losses
= Reverse recovery charge
= Input voltage
P D_LS + P COND ) P BODY
(1 * D )
The body diode losses can be approximated as:
Next, the MOSFET output capacitance losses are caused
by both the high−side and low−side MOSFETs, but are
dissipated only in the high−side MOSFET.
P DS +
=
=
=
=
Ǹ
(eq. 31)
IRMS_LS
= RMS current in the low side
RDS(ON)_LS = Low−side MOSFET on resistance
PCOND
= High side MOSFET conduction losses
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NCP3170
VIN
NCP3170A
NCP3170B
Vout
Lout
R1
R2
Rf
Cf
Cc
Rc
Cp
Resistance for
(V)
(V)
(mF)
(kW)
(kW)
(kW)
(pF)
(nF)
(kW)
(pF)
Current Gain
12
0.8
1.8
24.9
NI
NI
NI
NI
NI
15
3.6
12
1.0
2.5
24.9
100
1
150
15
0.825
NI
4
12
1.1
2.5
24.9
66.5
1
150
10
2
NI
20
12
1.2
2.5
24.9
49.9
1
150
10
2
NI
20
12
1.5
3.6
24.9
28.7
1
150
10
2.49
NI
20
12
1.8
3.6
24.9
20
1
150
10
2.49
NI
20
12
2.5
4.7
24.9
11.8
1
150
8.2
3.74
NI
25
12
3.3
4.7
24.9
7.87
1
150
6.8
4.99
NI
27
12
5.0
7.2
24.9
4.75
1
150
3.9
10
NI
27
12
10.68
7.2
24.9
2.05
1
150
3.9
10
NI
30
18
14.8
7.2
24.9
1.43
1
150
6.8
6.98
NI
30
5
0.8
1.8
24.9
NI
NI
NI
NI
NI
15
15
5
1.0
2.5
24.9
100
1
150
15
0.825
NI
28
5
1.1
2.5
24.9
66.5
1
150
10
2
NI
30
5
1.2
2.5
24.9
49.9
1
150
10
2
NI
30
5
1.5
3.6
24.9
28.7
1
150
10
2.49
NI
30
5
1.8
3.6
24.9
20
1
150
10
2.49
NI
30
5
2.5
3.6
24.9
11.8
1
150
6.8
4.99
NI
50
5
3.3
3.6
24.9
7.87
1
150
6.8
4.99
NI
50
12
1.2
1.5
24.9
49.9
1
82
2.7
6.04
NI
20
12
1.5
1.8
24.9
28.7
1
82
2.7
6.04
NI
22
12
1.8
1.8
24.9
20
1
82
2.7
6.04
NI
22
12
2.5
2.7
24.9
11.8
1
82
1.8
10
NI
32
12
3.3
3.3
24.9
7.87
1
82
1.5
12.1
NI
52
12
5.0
3.3
24.9
4.75
1
82
2.2
8.25
NI
52
12
10.68
1.5
24.9
2.05
1
82
2.2
5.1
NI
52
18
14.8
3.3
24.9
1.43
1
82
2.2
5.1
NI
52
5
0.8
1.0
24.9
NI
NI
NI
15
0.499
NI
20
5
1.0
1.0
24.9
100
NI
NI
6.8
1.69
NI
28
5
1.1
1.0
24.9
66.5
NI
NI
3.9
3.61
NI
42
5
1.2
1.5
24.9
49.9
1
82
2.7
6.04
NI
55
5
1.5
1.5
24.9
28.7
1
82
2.7
6.04
NI
55
5
1.8
1.5
24.9
20
1
82
1.8
10
NI
55
5
2.5
1.8
24.9
11.8
1
82
1.8
10
NI
55
5
3.3
1.8
24.9
7.87
1
82
1.8
10
NI
55
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19
NCP3170
The amplitude ratio can be calculated using the following
equation:
To compensate the converter we must first calculate the
current feedback
ǒ
Vout
Vin ) 32
Vin
Ǔ
) 1.46
M+
Ǔ
3.3 V
) 1.46 mW
12 V
12 V ) 32
7.299 +
(eq. 34)
L OUT
Y+
³
VIN
ǒ
F SW
500 kHz
Vo
VREF
Y
4.7 mH
FSW
= Switching Frequency
LOUT
= Output inductor value
M
= Current feedback
Vin
= Input Voltage
VOUT
= Output Voltage
The un−scaled gain of the converter also needs to be
calculated as follows:
VO
M*0.5*M
)
3.0 A
3.3 V
A
FSW
IOUT
LOUT
M
VIN
VOUT
COESR
COUT
FZESR
V OUT
=
=
=
=
=
=
=
7.299*0.5*7.299
)
4.7 mH
FP +
3.3 V
A
COUT
FP
Un−scaled gain
Switching Frequency
Output Current
Output inductor value
Current feedback
Input Voltage
Output Voltage
A
Vout
ǒ
32
33.061 +
FSW
G
LOUT
IOUT
M
VIN
VOUT
ǒ
Vin
32
Ǔ
³
(eq. 36)
) 1.46
2p
0.005 mW
A
C OUT
44 mF
³
(eq. 39)
1
2p
0.339 W
44 mF
= Un−scaled gain
= Output capacitor
= Current mode pole frequency
A
3.3 V
) 1.46 mW
12 V
Ǔ
=
=
=
=
=
=
=
(eq. 38)
The two equations above define the bode plot that the
power stage has created or open loop response of the system.
The next step is to close the loop by considering the feedback
values. The closed loop crossover frequency should be less
than 1/10 of the switching frequency, which would place the
maximum crossover frequency at 50 kHz.
Figure 45 shows a pseudo Type III transconductance error
amplifier.
Next the DC gain of the plant must be calculated.
G+
³
1
1
2p
10.664 kHz +
12 V
500 kHz
C OUT
CO ESR
= Output capacitor ESR
= Output capacitor
= Output capacitor zero ESR frequency
(eq. 35)
1
1
2p
723 kHz +
V IN
FSW
L OUT
0.339 W +
= Output voltage
= Regulator reference voltage
= Amplitude ratio
FZ ESR +
1
I OUT
(eq. 37)
The ESR of the output capacitor creates a “zero” at the
frequency as shown in Equation 38:
12 V
A+
0.8 V
VREF
³ 0.242 +
V OUT
3.3 V
ZIN
IEA
Switching Frequency
DC gain of the plant
Output inductor value
Output current
Current feedback
Input voltage
Output voltage
R1
CF
ZFB
CC
CP
Gm
R2
RC
VREF
Figure 45. Pseudo Type III Transconductance Error
Amplifier
The compensation network consists of the internal error
amplifier and the impedance networks ZIN (R1, R2, and CF)
and external ZFB (RC, CC, and CP). The compensation
network has to provide a closed loop transfer function with
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20
NCP3170
a good starting place for compensation of a power supply.
The values can be adjusted in real time using the
compensation tool CompCalc
http://www.onsemi.com/pub/Collateral/COMPCALC.ZIP
The first pole to crossover at the desired frequency should
be setup at FPO to decrease at −20 dB per decade:
the highest 0 dB crossing frequency to have fast response
and the highest gain in DC conditions, so as to minimize load
regulation issues. A stable control loop has a gain crossing
with −20 dB/decade slope and a phase margin greater than
45°. Include worst−case component variations when
determining phase margin. To start the design, a resistor
value should be chosen for R1 from which all other
components can be chosen. A good starting value is 24.9 kW.
The NCP3170 allows the output of the DC−DC regulator
to be adjusted down to 0.8 V via an external resistor divider
network. The regulator will maintain 0.8 V at the feedback
pin. Thus, if a resistor divider circuit was placed across the
feedback pin to VOUT, the regulator will regulate the output
voltage proportional to the resistor divider network in order
to maintain 0.8 V at the FB pin.
F PO +
F CROSS
G
50 kHz
1.512 kHz +
Fcross
FPO
33.061
³
(eq. 41)
³
= Cross over frequency
= Pole frequency to meet crossover
frequency
= DC gain of the plant
G
The crossover combined compensation network can be
used to calculate the transconductance output compensation
network as follows:
CC +
5.12 nF +
Figure 46. Feedback Resistor Divider
CC
FPO
gm
y
The relationship between the resistor divider network
above and the output voltage is shown in Equation 40:
R2 + R1
R1
R2
VOUT
VREF
=
=
=
=
ǒ
V REF
Ǔ
(eq. 40)
V OUT * V REF
=
=
=
=
2.925 kW +
CC
COUT
FP
RC
The most frequently used output voltages and their
associated standard R1 and R2 values are listed in the table
below.
OUTPUT VOLTAGE SETTINGS
VO (V)
R1 (kW)
R2 (kW)
0.8
24.9
Open
1.0
24.9
100
1.1
24.9
66.5
1.2
24.9
49.9
1.5
24.9
28.7
1.8
24.9
20
2.5
24.9
11.8
3.3
24.9
8.06
5.0
24.9
4.64
=
=
=
=
CP +
75.2 pF +
CP
FESR
RC
2p
2
gm
F PO
p
0.242
2p
³
(eq. 42)
200 ms
1.512 kHz
Compensation capacitor
Pole frequency
Transconductance of amplifier
Amplitude ratio
RC +
Top resistor divider
Bottom resistor divider
Output voltage
Regulator reference voltage
y
1
2p
CC
FP
³
(eq. 43)
1
2p
5.12 nF
1.512 kHz
Compensation capacitance
Output capacitance
Current mode pole frequency
Compensation resistor
1
RC
F ESR
³
(eq. 44)
1
2p
2.925 kW
723 kHz
= Compensation pole capacitor
= Capacitor ESR zero frequency
= Compensation resistor
If the ESR frequency is greater than the switching
frequency, a CF compensation capacitor may be needed for
stability as the output LC filter is considered high Q and thus
will not give the phase boost at the crossover frequency.
Further at low duty cycles due to some blanking and filtering
of the current signal the current gain of the converter is not
constant and the current gain is small. Thus adding CF and
RF can give the needed phase boost.
The compensation components for the Pseudo Type III
Transconductance Error Amplifier can be calculated using
the method described below. The method serves to provide
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21
NCP3170
CF +
127 pF +
2p
R1 ) R2
(R1 * RF ) R2 * RF ) R2 * R1)
2p
(24.9 kW * 1 kW ) 7.87 kW * 1 kW ) 7.87 kW * 24.9 kW)
F cross
³
(eq. 45)
24.9 kW ) 7.87 kW
CF
Fcross
gm
R1
R2
RF
= Compensation pole capacitor
= Cross over frequency
= Transconductance of amplifier
= Top resistor divider
= Bottom resistor divider
= Feed through resistor
50 kHz
From the above equation, it is clear that the inrush current
is dependent on the type of load that is connected to the
output. Two types of load are considered in Figure 48: a
resistive load and a stepped current load.
Inrush
Current
Load
Calculating Input Inrush Current
XCP3170
The input inrush current has two distinct stages: input
charging and output charging. The input charging of a buck
stage is usually controlled, but there are times when it is not
and is limited only by the input RC network, and the output
impedance of the upstream power stage. If the upstream
power stage is a perfect voltage source and switches on
instantaneously, then the input inrush current can be
depicted as shown in Figure 47 and calculated as:
OR
Figure 48. Load Connected to the Output Stage
If the load is resistive in nature, the output current will
increase with soft start linearly which can be quantified in
Equation 49.
IPK
I CLR_RMS +
Figure 47. Input Charge Inrush Current
V IN
I ICinrush_PK1 +
1.2 kA +
I ICinrush_RMS1 +
12.58 A +
V IN
CIN ESR
12 V
0.316
0.01
CIN
CINESR
tDELAY_TOTAL
VIN
=
=
=
=
CIN ESR
Ǹ
ICLR_RMS
ICR_PK
ROUT
VOUT
(eq. 46)
12
0.01
Ǹ
5
0.316
5
191 mA +
CIN ESR
C IN
1
Ǹ3
1
Ǹ3
=
=
=
=
V OUT
I CR_PK +
R OUT
3.3 V
300 mA +
10 W
COUT
CLOAD
D
ICL
IOCinrush_RMS
tSS
VOUT
10 W
(eq. 47)
0.01 W
ǒCOUT ) CLOADǓ
=
=
=
=
=
=
=
3.3 V
3.3 V
t DELAY_TOTAL
22mF
1 ms
Output
Voltage
Output capacitor
Output capacitor ESR
Total delay interval
Input Voltage
t SS
R OUT
RMS resistor current
Peak resistor current
Output resistance
Output voltage
Output
Current
Once the tDELAY_TOTAL has expired, the buck converter starts
to switch and a second inrush current can be calculated:
I OCinrush_RMS +
V OUT
V OUT
D
) I CL
Ǹ3
tss
D
Figure 49. Resistive Load Current
(eq. 48)
Total converter output capacitance
Total load capacitance
Duty ratio of the load
Applied load at the output
RMS inrush current during start−up
Soft start interval
Output voltage
http://onsemi.com
22
(eq. 49)
NCP3170
Alternatively, if the output load has an under voltage
lockout, turns on at a defined voltage level, and draws a
constant current, then the RMS connected load current is:
I CL1 +
492 mA +
IOUT
VOUT
VOUT_TO
Ǹ
V OUT * V OUT_TO
Ǹ
V OUT
VIN
C1
22 mF
I OUT
(eq. 50)
PG
Cc
1A
3.3 V
3.3 V
COMP
R1
DRIVE
FB1
C2,
C3
22 mF
R2
PGND
Rc
= Output current
= Output voltage
= Output voltage load turn on
Figure 51. Buck Converter Current Paths
The first loop shown in blue activates when the high side
switch turns on. When the switch turns on, the edge of the
current waveform is provided by the bypass capacitor. The
remainder of the current is provided by the input capacitor.
Slower currents are provided by the upstream power supply
which fills up the input capacitor when the high side switch
is off. The current flows through the high side MOSFET and
to the output, charging the output capacitors and providing
current to the load. The current returns through a PCB
ground trace where the output capacitors are connected, the
regulator is grounded, and the input capacitors are grounded.
The second loop starts from the inductor to the output
capacitors and load, and returns through the low side
MOSFET. Current flows in the second loop when the low
side NMOSFET is on. The designer should note that there
are locations where the red line and the blue line overlap;
these areas are considered to have DC current. Areas
containing a single blue line indicate that AC currents flow
and transition very quickly. The key to power supply layout
is to focus on the connections where the AC current flows.
A good rule of thumb is that for every inch of PCB trace,
20 nH of inductance exists. When laying out a PCB,
minimizing the AC loop area reduces the noise of the circuit
and improves efficiency. A ground plane is strongly
recommended to connect the input capacitor, output
capacitor, and PGND pin of the NCP3170. Drawing the real
high power current flow lines on the recommended layout is
important so the designer can see where the currents are
flowing.
3.3. V
1.0 V
VSW L1 4.7 mH
EN
Cbypass
0.1 mF
AGND
3.3 V * 2.5 V
Output
Voltage
Output
Current
VIN
Input
Current
t
tss
Figure 50. Voltage Enable Load Current
If the inrush current is higher than the steady state input
current during max load, then an input fuse should be rated
accordingly using I2t methodology.
Thermal Management and Layout
Consideration
In the NCP3170 buck regulator high pulsing current flows
through two loops as shown in the figure below.
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23
NCP3170
temperature, minimum airflow, maximum input voltage,
maximum loading, and component variations (i.e., worst
case MOSFET RDS(on)). Several layout tips are listed below
for the best electric and thermal performance. Figure 53
illustrates a PCB layout example of the NCP3170.
1. The VSW pin is connected to the internal PFET
and NFET drains, which are a low resistance
thermal path. Connect a large copper plane to the
VSW pin to help thermal dissipation. If the PG pin
is not used in the design, it can be connected to the
VSW plane, further reducing the thermal
impedance. The designer should ensure that the
VSW thermal plane is rounded at the corners to
reduce noise.
2. The user should not use thermal relief connections
to the VIN and the PGND pins. Construct a large
plane around the PGND and VIN pins to help
thermal dissipation.
3. The input capacitor should be connected to the
VIN and PGND pins as close as possible to the IC.
4. A ground plane on the bottom and top layers of the
PBC board is preferred. If a ground plane is not
used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin
noise coupling to the AGND pin.
5. Create copper planes as short as possible from the
VSW pin to the output inductor, from the output
inductor to the output capacitor, and from the load
to PGND.
6. Create a copper plane on all of the unused PCB
area and connect it to stable DC nodes such as:
VIN, GND, or VOUT.
7. Keep sensitive signal traces far away from the
VSW pins or shield them.
Figure 52. Recommended Signal Layout
The NCP3170 is the major source of power dissipation in
the system for which the equations above detailed the loss
mechanisms. The control portion of the IC power
dissipation is determined by the formula below:
PC + IC
ICC
PC
VIN
V IN
(eq. 51)
= Control circuitry current draw
= Control power dissipation
= Input voltage
Once the IC power dissipations are determined, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient temperature. The formula for calculating the
junction temperature with the package in free air is:
TJ + TA ) PD
PD
RqJA
TA
TJ
R qJA
(eq. 52)
= Power dissipation of the IC
= Thermal resistance junction to ambient of
the regulator package
= Ambient temperature
= Junction temperature
The thermal performance of the NCP3170 is strongly
affected by the PCB layout. Extra care should be taken by
users during the design process to ensure that the IC will
operate under the recommended environmental conditions.
As with any power design, proper laboratory testing should
be performed to ensure the design will dissipate the required
power under worst case operating conditions. Variables
considered during testing should include maximum ambient
Figure 53. Recommend Thermal Layout
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24
NCP3170
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
S
M
J
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP3170/D