HCPL-M700/HCPL-M701 Small Outline, 5 Lead, Low Input Current, High Gain Optocouplers Data Sheet Description Features These small outline, low input current, high gain optocouplers are single channel devices in a five lead miniature footprint. They are electrically equivalent to the following Avago optocouplers: • Surface mountable • Very small, low profile JEDEC registered package outline • Compatible with infrared vapor phase reflow and wave soldering processes • High current transfer ratio: 2000% • Low input current capability: 0.5 mA • TTL compatible output: VOL = 0.1 V • Guaranteed ac and dc performance over temperature: 0°C to 70°C • High output current: 60 mA • Recognized under the component program of U.L. (file No. E55361) for dielectric withstand proof test voltage of 3750 Vac, 1 minute • Lead free option “-000E” The SO-5 JEDEC registered (MO-155) package outline does not require “through holes” in a PCB. This package occupies approximately one-fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. These high gain series opto-couplers use a Light Emitting Diode and an integrated high gain photodetector to provide extremely high current transfer ratio between input and output. Separate pins for the photodiode and output stage results in TTL compatible saturation voltages and high speed Applications operation. Where desired the VCC and VO terminals • Ground isolate most logic families: TTL/TTL, CMOS/TTL, CMOS/CMOS, LSTTL/TTL, CMOS/LSTTL may be tied together to achieve conventional photodarlington operation. • Low input current line receiver • EIA RS232C line receiver The HCPL-M701 is for use in CMOS, LSTTL or other • Telephone ring detector low power applications. A 400% minimum current • ac line voltage status indicator: transfer ratio is guaranteed over a 0-70°C operating low input power dissipation range for only 0.5 mA of LED current. • Low power systems: ground isolation The HCPL-M700 is designed for use mainly in TTL applications. Current Transfer Ratio is 300% minimum over 0-70 °C for an LED current of 1.6 mA [1 TTL Unit Load (U.L.)]. A 300% CTR enables operation with 1 U.L. out with a 2.2 kΩ pull-up resistor. Selection for lower input currents down to 250 µA is available upon request. SO-5 Package Standard DIP SO-8 Package HCPL-M700 6N138 HCPL-0700 HCPL-M701 6N139 HCPL-0701 CAUTION: The small device geometries inherent to the design of this bipolar component increase the component’s susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information HCPL-M700 and HCPL-M701 are UL Recognized with 3750 Vrms for 1 minute per UL1577 and are approved under CSA Component Acceptance Notice #5, File CA 88324. Part Number Option RoHS Non RoHS Compliant Compliant HCPL-M700 HCPL-M701 -000E -500E No option #500 Package SO-5 Surface Mount Gull Wing Tape & Reel Quantity X X X 100 per tube 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-M700-500E to order product of Mini-flat Surface Mount 5-pin package in Tape and Reel packaging with RoHS compliant. Example 2: HCPL-M700 to order product of Mini-flat Surface Mount 5-pin package in tube packaging and non RoHS compliant. Option data sheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘. Outline Drawing (JEDEC MO-155) ANODE 1 4.4 ± 0.1 (0.173 ± 0.004) MXXX XXX 7.0 ± 0.2 (0.276 ± 0.008) 6 VCC 5 VOUT CATHODE 3 4 GND 0.4 ± 0.05 (0.016 ± 0.002) 3.6 ± 0.1* (0.142 ± 0.004) 2.5 ± 0.1 (0.098 ± 0.004) 0.102 ± 0.102 (0.004 ± 0.004) 0.15 ± 0.025 (0.006 ± 0.001) 7° MAX. 1.27 BSC (0.050) 0.71 MIN. (0.028) MAX. LEAD COPLANARITY = 0.102 (0.004) DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006) NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. 2 Land Pattern Recommendation Schematic 6 VCC 4.4 (0.17) ICC + IF ANODE 1.3 (0.05) 2.5 (0.10) 1 VF CATHODE – 3 2.0 (0.080) 5 VO 0.64 (0.025) 8.27 (0.325) Absolute Maximum Ratings (No Derating Required up to 85°C) Storage Temperature ................................................... -55°C to +125°C Operating Temperature ................................................. -40°C to +85°C Average Input Current - IF .......................................................... 20 mA Peak Input Current - IF ............................................................... 40 mA (50% duty cycle, 1 ms pulse width) Peak Transient Input Current - IF ................................................ 1.0 A (≤1 µs pulse width, 300 pps) Reverse Input Voltage - VR ............................................................... 5 V Input Power Dissipation ............................................................. 35 mW Output Current - IO (Pin 5) ......................................................... 60 mA Supply and Output Voltage - VCC (Pin 6-4),VO (Pin 5-4) HCPL-M700 .................................................................... -0.5 V to 7 V HCPL-M701 .................................................................. -0.5 V to 18 V Output Power Dissipation ........................................................ 100 mW Infrared and Vapor Phase Reflow Temperature .................... see below 3 IO 4 GND Solder Reflow Thermal Profile 300 TEMPERATURE (°C) PREHEATING RATE 3°C + 1°C/–0.5°C/SEC. REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK TEMP. 245°C PEAK TEMP. 240°C PEAK TEMP. 230°C 200 2.5°C ± 0.5°C/SEC. SOLDERING TIME 200°C 30 SEC. 160°C 150°C 140°C 30 SEC. 3°C + 1°C/–0.5°C 100 PREHEATING TIME 150°C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 50 0 100 150 200 250 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 260 +0/-5 °C 217 °C RAMP-UP 3 °C/SEC. MAX. Tsmax 150 - 200 °C RAMP-DOWN 6 °C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. tL 60 to 150 SEC. NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 °C, Tsmin = 150 °C 25 t 25 °C to PEAK TIME Note: Non-halide flux should be used. Insulation Related Specifications Parameter Min. External Air Gap (Clearance) Min. External Tracking Path (Creepage) Min. Internal Plastic Gap (Clearance) Tracking Resistance Isolation Group (per DIN VDE 0109) 4 Symbol L(IO1) Value ≥5 Units mm L(IO2) ≥5 mm 0.08 mm 175 IIIa V CTI Conditions Measured from input terminals to output terminals Measured from input terminals to output terminals Through insulation distance conductor to conductor DIN IEC 112/VDE 0303 Part 1 Material Group DIN VDE 0109 Electrical Specifications Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. (See note 6.) Parameter Current Transfer Ratio Symbol Device Min. Typ.* Max. Units HCPLCTR M701 400 2000 3500 500 1600 2600 300 1600 2600 0.1 0.4 0.1 0.4 0.2 0.4 M700 0.1 0.4 M701 0.05 100 M700 0.1 250 M700 Logic Low Output Voltage Logic High Output VOL IOH M701 % Test Conditions Fig. Note IF = 0.5 mA, VO = 0.4 V, VCC = 4.5 V IF = 1.6 mA, V = 0.4 V, VCC = 4.5 V 2, 3 1 IF = 1.6 mA, VO = 0.4 V, VCC = 4.5 V V IF = 1.6 mA, IO = 8 mA, VCC = 4.5 V IF = 5 mA, IO = 15 mA, VCC = 4.5 V IF = 12 mA, IO = 24 mA, VCC = 4.5 V IF = 1.6 mA, IO = 24 mA, VCC = 4.5 V µA IF = 0 mA, VO = VCC = 18 V IF = 0 mA, VO = VCC = 7 V Logic Low Supply Current ICCL 0.4 1.5 mA IF = 1.6 mA, VO = Open, VCC = 18 V Logic High Supply Current ICCH 0.01 10 µA IF = 0 mA, VO = Open, VCC = 18 V VF 1.4 1.7 V Input Forward Voltage 1 TA = 25°C 1.75 4 IF = 1.6 mA IR = 10 µA Input Reverse Breakdown Voltage BVR Temperature Coefficient of Forward Voltage ∆VF/∆TA -1.8 mV/°C Input Capacitance CIN 60 pF InputOutput Insulation VISO Resistance (InputOutput) RI-O 1012 Ω VI-O = 500 VDC 2 Capacitance (InputOutput) CI-O 0.6 pF f = 1 MHz 2 *All 5 typicals at TA = 25°C, VCC = 5 V. 5 3750 VRMS IF = 1.6 mA f = 1 MHz, VF = 0 RH ≤ 50%, t = 1 min, TA = 25°C 2, 3 Switching Specifications Over recommended temperature (TA = 0°C to 70°C), VCC = 5 V, unless otherwise specified. Parameter Propagation Delay Time to Logic Low at Output Sym- Device bol HCPL- Min. tPHL M701 Typ.* Max. Unit 25 75 µs Test Conditions TA = 25°C 100 0.5 2 TA = 25°C IF = 12 mA, RL = 270 Ω TA = 25°C IF = 1.6 mA, RL = 2.2 kΩ TA = 25°C IF = 0.5 mA, RL = 4.7 kΩ 3 M700 5 20 25 Propagation Delay Time to Logic High at Output tPLH M701 10 60 90 1 10 TA = 25°C IF = 12 mA, RL = 270 Ω TA = 25°C IF = 1.6 mA, 15 M700 10 35 50 IF = 0.5 mA, RL = 4.7 kΩ Fig. Note 5, 6, 7 5, 6, 7 RL = 2.2 kΩ Common |CMH| Mode Transient Immunity at Logic High Output 1,000 10,000 V/µs IF = 0 mA RL = 2.2 kΩ |VCM| = 10 Vp-p 8 4, 5 Common |CML| Mode Transient Immunity at Logic Low Output 1,000 10,000 V/µs IF = 1.6 mA RL = 2.2 kΩ |VCM| = 10 Vp-p 8 4, 5 *All typicals at TA = 25°C. Notes: 1. dc CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100. 2. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together. 3. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 µA). 4. Common transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on the rising edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the falling edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). 5. In applications where dV/dt may exceed 50,000 V/µs (such as static discharge) a series resistor, RCC, should be included to protect the detector IC from destructively high surge currents. The recommended value is RCC = 220 Ω. 6. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 is recommended. 6 3.0 mA 2.5 mA 2.0 mA 1.5 mA 1.0 mA 0.5 mA TA = 25°C VCC = 5.0 V 0 0 2.0 1.0 Figure 1. dc Transfer Characteristics. TA = 25°C + VF – 1.0 0.1 0.01 0.001 1.1 1.2 1.3 1.4 1.5 VF – FORWARD VOLTAGE – V Figure 4. Input Diode Forward Current vs. Forward Voltage. 7 tp – PROPAGATION DELAY – µs IF – FORWARD CURRENT – mA 10 800 VCC = 5.0 V VO = 0.4 V 400 0 0.1 1.0 1.6 26 24 RL = 2.2 kΩ I = 1.6 mA 22 F 1/f = 50 µs 20 18 16 tPLH 14 12 10 8 6 4 tPHL 2 0 0 10 20 30 40 50 60 70 80 90 100 TA – TEMPERATURE – °C Figure 5. Propagation Delay vs. Temperature. 10 TA = 70°C 1.0 TA = 25°C 0.1 TA = 0°C 0.01 0.01 10 Figure 2. Current Transfer Ratio vs. Forward Current. 1000 IF 1200 IF – FORWARD CURRENT – mA VO – OUTPUT VOLTAGE – V 100 70° C 1600 0.1 1 10 IF – INPUT DIODE FORWARD CURRENT – mA Figure 3. Output Current vs. Input Diode Forward Current. 100.0 TA = 25°C tf TIME – µs 25 100 0° C 25° C 2000 IO – OUTPUT CURRENT – mA 4.0 mA 3.5 mA CTR – CURRENT TRANSFER RATIO – % IO – OUTPUT CURRENT – mA 5.0 mA 50 4.5 mA tr 10.0 (SEE FIGURE 7 FOR TEST CIRCUIT) IF ADJUSTED FOR VOL = 2 V 1.0 0.1 1.0 10 RL – LOAD RESISTANCE – kΩ Figure 6. Non-Saturated Rise and Fall Times vs. Load Resistance. IF 0 5V VO PULSE GEN. ZO = 50 Ω tr = 5 ns IF +5 V 1 6 RL 10% DUTY CYCLE 1/f 100 µs (SATURATED RESPONSE) 1.5 V tPHL tPLH VO 5V 90% 90% 10% VO 0.1µF 1.5 V VOL (NONSATURATED RESPONSE) 5 3 IF MONITOR 4 CL = 15 pF* RM * INCLUDES PROBE AND FIXTURE CAPACITANCE 10% tf tr Figure 7. Switching Test Circuit. IF tr, tf = 16 ns VCM 10 V 90% 90% 10% 0V RCC (SEE NOTE 5) +5 V 220 Ω B 1 10% 6 RL A tr tf VO 5 VO 5V 0.1µF 4 3 SWITCH AT A: IF = 0 mA VO VFF VOL SWITCH AT B: IF = 1.6 mA VCM + – PULSE GEN. Figure 8. Test Circuit for Transient Immunity and Typical Waveforms. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0548EN AV02-0238EN May 11, 2007