SFH6318 SFH6319 LOW CURRENT, HIGH GAIN OPTOCOUPLER Package Dimensions in Inches (mm) .120±.002 (3.05±.05) FEATURES • Industry Standard SOIC-8 Surface Mountable Package • High Current Transfer Ratio, 800% • Low Input Current, 0.5mA • High Output Current, 60mA • Isolation Test Voltage, 2500 VACRMS • TTL Compatible Output, VOL=0.1 V • Adjustable Bandwidth-Access to Base • Underwriters Lab File #E52744 APPLICATIONS • Logic Ground Isolation-TTL/TTL, TTL/CMOS, CMOS/CMOS, CMOS/TTL • EIA RS 232C Line Receiver • Low Input Current Line Receiver-Long Lines, Party Lines • Telephone Ring Detector • 117 VAC Line Voltage Status Indication-Low Input Power Dissipation • Low Power Systems-Ground Isolation DESCRIPTION Very high current ratio together with 2500 VAC isolation are achieved by coupling an LED with an integrated high gain photodetector in a SOIC-8 package. Separate pins for the photodiode and output stage enable TTL compatible saturation voltages with high speed operation. Photodarlington operation is achieved by tying the VCC and VO terminals together. Access to the base terminal allows adjustment to the gain bandwidth. The SFH6318 is ideal for TTL applications since the 300% minimum current transfer ratio with an LED current of 1.6 mA enables operation with one unit load-in and one unit load-out with a 2.2 KW pull-up resistor. The SFH6319 is best suited for low power logic applications involving CMOS and low power TTL. A 400% current transfer ratio with only 0.5 mA of LED current is guaranteed from 0°C to 70°C. Caution: Due to the small geometries of this device, it should be handled with Electrostatic Discharge (ESD) precautions. Proper grounding would prevent damage further and/or degradation which may be induced by ESD. NC 1 CL .154±.002 (.391±.05) .240 (6.10) Anode 2 7 VB Cathode 3 6 V0 .192±.005 (4.88±.13) .004 (.10) .008 (.20) 5 GND NC 4 .016 (.41) Pin 1 8 VCC .015±.002 (.38±.05) 40° .008 (.20) 5° max. .021 (.53) .050 (1.27) typ. .020±.004 (.15±.10) 2 plcs. R.010 (.25) max. 7° .058±.005 (1.49±.13) .125±.005 (3.18±.13) Lead Coplanarity ±.0015 (.04) max. TOLERANCE: ±.005 (unless otherwise noted) Maximum Ratings (25°) Emitter Reverse Input Voltage....................................................................... 3 V Supply and Output Voltage, VCC (pin 8-5), VO (pin 6-5) SFH6318 ........................................................................... –0.5 to 7 V SFH6319 ......................................................................... –0.5 to 18 V Input Power Dissipation .............................................................. 35 mW Derate Linearly above 50°C Free Air Temperature......................................................... 0.7 mW/°C Average Input Current.................................................................. 20 mA Peak Input Current....................................................................... 40 mA (50% Duty Cycle-1 ms pulse width) Peak Transient Input Current (tp≤1 µsec, 300 pps) .................................................................. 1.0 A Detector (Si Photodiode + Photodarlington) Output Current IO (pin 6) ............................................................. 60 mA Emitter-Base Reverse Voltage (pin 5-7)......................................... 0.5 V Output Power Dissipation ......................................................... 150 mW Derate Linearly from 25°C ................................................... 2 mW/°C Package Storage Temperature .................................................. –55°C to +125°C Operating Temperature ................................................. –40°C to +85°C Lead Soldering Temperature (t=10 sec.) ..................................... 260°C Junction Temperature .................................................................. 100°C Ambient Temperature Range ...................................... –55°C to +100°C Isolation Test Voltage between Emitter and Detector ...................................................2500 VACRMS (refer to climate DIN 40046, part 2, Nov. 74) Pollution Degree (DIN VDE 0110).........................................................2 Creepage Distance ......................................................................≥4 mm Clearance ....................................................................................≥4 mm Comparative Tracking Index per DIN IEC 112/VDE 0303, part 1 .............................................. 175 Isolation Resistance VIO=500 V, TA=25°C RISOL ................................................. ≥1012W VIO=500 V, TA=100°C RISOL ............................................... ≥1011W 1 Electro-Optical Characteristics (TA=0°C to 70°C, TA=25°C-Typical, unless otherwise specified) Parameter Symbol Device Min Typ Max Units Test Conditions Note Current Transfer Ratio CTR SFH6318 300 1600 2600 % IF=1.6 mA, VO=0.4 V, VCC=4.5 V 1,2 SFH6319 400 500 1600 2000 2600 3500 % IF=0.5 mA, VO=0.4 V, VCC=4.5 V IF=1.6 mA, VO=0.4 V, VCC=4.5 V 1,2 SFH6318 0.1 0.4 V IF=1.6 mA, IO=4.8 mA, VCC=4.5 V 2 SFH6319 0.1 0.15 0.25 0.4 0.4 0.4 V IF=1.6 mA, IO=8 mA, VCC=4.5 V IF=5 mA, IO=15 mA, VCC=4.5 V IF=12 mA, IO=24 mA, VCC=4.5 V 2 SFH6318 0.1 250 µA IF=0 mA, VO=VCC=7 V 2 SFH6319 0.05 100 µA IF=0 mA, VO=VCC=18 V 2 Logic Low Output Voltage Logic High Output Current VOL IOH Logic Low Supply Current ICCL 0.2 1.5 mA IF=1.6 mA, VO=OPEN, VCC=18 V 2 Logic High Supply Current ICCH 0.01 10 µA IF=0 mA, VO=OPEN, VCC=18 V 2 Input Forward Voltage VF 1.4 1.7 V IF=1.6 mA, TA=25°C Temperature Coefficient, Forward Voltage ∆VF/∆TA –1.8 mV/ °C IF=1.6 mA Input Capacitance CIN 25 pF f=1 MHz, VF=0 Resistance (Input-Output) RI-O 1012 1011 Ω Ω VIO=500 VDC, TA=25°C VIO=500 VDC, TA=100°C 3 Capacitance (Input-Output) CI-O 0.6 pF f=1 MHz 3 Switching Specifications (TA=25°C) Parameter Symbol Device Propagation Delay Time To Logic Low at Output tPHL Propagation Delay Time To Logic High at Output tPLH Min Typ Max Units Test Conditions Note SFH6318 2 10 µs IF=1.6 mA, RL=2.2 KΩ SFH6319 6 0.6 25 1 µs IF=0.5 mA, RL=4.7 KΩ IF=12 mA, RL=270 Ω SFH6318 2 35 µs IF=1.6 mA, RL=2.2 KΩ SFH6319 4 1.5 60 7 µs IF=0.5 mA, RL=4.7 KΩ IF=12 mA, RL=270 Ω 2,4 2,4 Common Mode Transient Immunity at Logic High Level Output | CMH | 1K V/µs IF=0 mA, RL=2.2 KΩ VCM=10 Vp-p 5,6 Common Mode Transient Immunity at Logic Low Level Output | CML| 1K V/µs IF=1.6 mA, RL=2.2 KΩ VCM=10 Vp-p 5,6 Notes 1. DC current transfer ratio is defined as the ratio of output collector current, IO, to the forward LED input current, IF times 100%. 2. Pin 7 open. 3. Device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together. 4. Using a resistor between pin 5 and 7 will decrease gain and delay time. 5. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a logic high state (i.e. VO>2.0 V) common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e. VO<0.8 V). 6. In applications where dv/dt may exceed 50,000 V/µs (such as state discharge) a series resistor, RCC should be included to protect IC from destruc kΩ. Refer to Figure 2. tively high surge currents. The recommended value is RCC≅ IV 0.15 IF(mA) 2 SFH6318/6319 Figure 1. Switching test circuit IF 10% Duty Cycle 1/f<100 µs 0 5V VO (Saturated Response) 1.5 V Pulse Generator ZO=50 Ω tr=5 ns 1.5 V VOL tPLH tPHL VO 90% (Non-Saturated Response) 10% tf IF 8 2 7 +5 V RL IF=Monitor 5V 90% 1 3 6 4 5 VO 0.1 µF CL=15pF Rm 10% tr Figure 2. Test circuit for transient immunity and typical waveforms RCC (see Note 6) VCM 90% 90% 0 V 10% 5V Switch at A: IF=0 mA VO Switch at B: IF=1.6 mA 2 7 3 6 4 5 +5 V 220 Ω 0.1 µF RL tf A VO 8 IF 10% tr tf + tf=16 ns 1 VO B VFF + VOL VCM – Pulse Generator 3 SFH6318/6319