PRELIMINARY CY24133 MediaClock™ Digital TV Clock Generator with VCXO Features Benefits • Low jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • VCXO with analog adjust Large ±150-ppm range, better linearity • 3.3V operation Enables application compatibility Frequency Table Part Number Outputs CY24133-1 2 Input Frequency Range Output Frequency Range 27-MHz pullable Crystal per Cypress Specification 3.072-, 4.096-, 6.144-, 11.2896-, 12.288-MHz-selectable output frequencies and 27-MHz reference output Logic Block Diagram XIN Q OSC XOUT Φ CLKOUT VCO Output Multiplexer and Dividers P VCXO PLL REFCLK FS0 FS1 ROM FS2 AVDD VDD AVSS VSS VDDL VSSL Pin Configuration CY24133-1 16-pin TSSOP Cypress Semiconductor Corporation Document #: 38-07497 Rev. ** • XIN VDD AVDD 1 16 XOUT 2 15 NC 3 14 VCXO 4 NC VSS AVSS 5 13 12 VSSL 6 11 VDDL FS2 FS1 7 10 FS0 8 9 REFCLK CLKOUT 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 3, 2003 CY24133 PRELIMINARY Pin Description Name Pin Number Description XIN 1 Reference Crystal Input VDD 2 Voltage Supply AVDD 3 Analog Voltage Supply VCXO 4 Input Analog Control Voltage for VCXO AVSS 5 Analog Ground VSSL 6 Output Clock Ground FS2 7 Frequency Select 2 FS1 8 Frequency Select 1 CLKOUT 9 Configurable Clock Output 1 at VDDL level FS0 10 Frequency Select 0 VDDL 11 Clock Output Voltage Supply REFCLK 12 Reference Clock Output at VDDL level VSS 13 Ground NC 14 No Connect NC 15 No Connect 16 Reference Crystal Output [1] XOUT Frequency Select Table—CY24133-1 FS2 FS1 FSO CLKOUT REFCLK 0 0 0 3.072 27 0 0 1 4.096 27 0 1 0 6.144 27 0 1 1 11.2896 27 1 0 0 12.288 27 1 0 1 off off 1 1 0 off off 1 1 1 off off Pullable Crystal Specifications Parameter CRload Name Min. Crystal Load Capacitance Typ. Max. Unit 14 pF C0/C1 250 50 Ω 70 °C Crystal Accuracy +20 ppm Stability over temperature and aging +50 ppm ESR Equivalent Series Resistance To Operating Temperature Crystal Accuracy TTs 35 0 Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage –0.5 7.0 V VDDL I/O Supply Voltage –0.5 7.0 V –65 125 °C 125 °C Temperature[2] TS Storage TJ Junction Temperature Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07497 Rev. ** Page 2 of 5 CY24133 PRELIMINARY Absolute Maximum Conditions (continued) Parameter Description Min. Max. Unit Digital Inputs AVSS – 0.3 AVDD + 0.3 V Analog Input referred to AVDD AVSS – 0.3 AVDD + 0.3 V Electrostatic Discharge 2 kV Recommended Operating Conditions Parameter Description AVDD/VDD/VDDL Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance VDD/VDDL=3.3V fREF Reference Frequency Min. Typ. Max. 3.135 3.3 3.456 V 70 °C 15 pF 0 Unit 27 MHz DC Electrical Specifications Parameter[3] Name Description Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD/VDDL = 3.3V 12 24 mA IOL Output Low Current VOL = 0.5, VDD/VDDL = 3.3V 12 24 mA 0.7 VIH Input High Voltage CMOS levels VIL Input Low Voltage CMOS levels CIN Input Capacitance Frequency Select Pins f∆XO VCXO pullability range VVCXO VCXO input range IDD Supply Current VDD 0.3 VDD 7 pF +150 ppm 0 AVDD/VDD/VDDL Current AVDD V 18 25 mA Typ. Max. Unit 55 AC Electrical Specifications Parameter[3] Name Description Min. DC Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 V/ns t9 Clock Jitter Peak-to-Peak period jitter on CLKOUT 350 ps t10 PLL Lock Time Measured from VDD = 3.0V 3 % ms Test and Measurement Set-up VDDs Outputs 0.1 µF DUT CLOAD GND Note: 3. Guaranteed by design, not 100% tested. Document #: 38-07497 Rev. ** Page 3 of 5 CY24133 PRELIMINARY Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t4 t3 V DD 80% of V DD 20% of VDD Clock Output 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24133ZC-1 Z16 16-pin TSSOP Commercial 3.3V CY24133ZC-1T Z16 16-pin TSSOP – Tape and Reel Commercial 3.3V Package Drawing and Dimensions 16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091-** MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07497 Rev. ** Page 4 of 5 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY24133 PRELIMINARY Document History Page Document Title: CY24133 MediaClock™ Digital TV Clock Generator with VCXO Document Number: 38-07497 REV. ** ECN NO. Issue Date 121554 02/17/03 Document #: 38-07497 Rev. ** Orig. of Change CKN Description of Change New Data Sheet Page 5 of 5