CY26114 One-PLL Clock Generator Features Benefits • Integrated phase-locked loop Internal PLL with up to 333 MHz internal operation • Low skew, low jitter, high accuracy outputs Meets critical timing requirements in complex system designs • 3.3V Operation with 2.5 V Output Option Enables application compatibility Part Number Outputs Input Frequency Output Frequency Range CY26114 4 25MHz Crystal Input 2 copies of 100MHz, 1 copy of 50MHz, 1 copy 25/33/50/66MHz (frequency selectable) Logic Block Diagram XIN Q OSC. Pin Configurations Φ VCO XOUT OUTPUT MULTIPLEXER AND DIVIDERS P 100MHz 16-pin TSSOP 100MHz PLL 50MHz 25/33/50/66MHz (frequency selectable) FS0 FS1 VDDL VDD AVDD AVSS VSS VSSL XIN VDD 1 16 XOUT 2 15 AVDD FS0 3 14 CLK4 CLK3 4 13 VSS AVSS 5 12 N/C VSSL 6 11 VDDL LCLK1 LCLK2 7 10 8 9 FS1 N/C CLK4 Frequency Select Options FS1 FS0 CLK 4 Units 0 0 25 MHz 0 1 33 MHz 1 0 50 MHz 1 1 66 MHz Cypress Semiconductor Corporation Document #: 38-07098 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY26114 Pin Definitions Name Pin Number Description XIN 1 Reference Crystal Input VDD 2 Voltage Supply AVDD 3 Analog Voltage Supply FS0 4 Frequency Select 0 AVSS 5 Analog Ground VSSL 6 LCLK Ground LCLK1 7 100-MHz output clock at VDDL Level LCLK2 8 100-MHz output clock at VDDL Level N/C 9 No Connect FS1 10 Frequency Select 1 VDDL 11 LCLK Voltage Supply (2.5V or 3.3V) N/C 12 No Connect VSS 13 Ground CLK3 14 50-MHz output clock CLK4 15 25/33/50/66-MHz clock output (frequency selectable) XOUT 16 Reference Crystal Output Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage –0.5 7.0 V VDDL I/O Supply Voltage 7.0 V TJ Junction Temperature 125 °C Digital Inputs AVSS – 0.3 AVDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDDL VSS – 0.3 VDDL +0.3 Electro-Static Discharge 2 V kV Recommended Operating Conditions Parameter Description Min. Typ. VDD VDDL Operating Voltage 3.0 Operating Voltage 2.375 TA Ambient Temperature 0 CLOAD Max. Load Capacitance fREF Reference Frequency tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Max. Unit 3.3 3.6 V 2.5 2.625 V 70 °C 15 pF 25 0.05 MHz 500 ms Note: 1. Float XOUT if XIN is externally driven. Document #: 38-07098 Rev. *A Page 2 of 5 CY26114 DC Electrical Characteristics Parameter[2] Name Description Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD/VDDL = 3.3V 12 24 mA IOL Output Low Current VOL = 0.5, VDD/VDDL = 3.3V 12 24 mA IOH Output High Current VOH = VDDL – 0.5, VDDL=2.5V 8 16 mA IOL Output Low Current VOL = 0.5, VDDL = 2.5V 8 16 mA VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD 0.7 VDD IVDD Supply Current AVDD/VDD Current 25 mA IVDDL Supply Current VDDL Current (VDDL = 3.6V) 20 mA IVDDL Supply Current VDDL Current (VDDL = 2.625V) 15 mA 0.3 VDD AC Electrical Characteristics Parameter[2] Description Min. Typ. Max. Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD 45 50 55 % t3 Rising Edge Rate Output Clock Rise Time, 20% – 80% of VDD/VDDL = 3.3V 0.8 1.4 V/ns t3 Rising Edge Rate Output Clock Rise Time, 20% – 80% of VDDL = 2.5V 0.6 1.2 V/ns t4 Falling Edge Rate Output Clock Fall Time, 80% – 20% of VDD/VDDL = 3.3V 0.8 1.4 V/ns t4 Falling Edge Rate Output Clock Fall Time, 80% – 20% of VDDL = 2.5V 0.6 1.2 V/ns t5 Skew Delay between related outputs at rising edge 250 t9 Clock Jitter Peak to Peak period jitter 200 ps t10 PLL Lock Time 3 ms ps t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definitions: DC = t2/t1. t3 t4 80% CLK 20% Figure 2. Rise Time and Fall Time Definitions. Note: 2. Not 100% tested. Document #: 38-07098 Rev. *A Page 3 of 5 CY26114 Test Circuit VDD CLK out 0.1 µF OUTPUTS CLOAD AVDD 0.1 µF GND Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY26114ZC Z16 16-Pin TSSOP Commercial 3.3V Document #: 38-07098 Rev. *A Page 4 of 5 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY26114 Document Title: CY26114 One-PLL Clock Generator Document Number: 38-07098 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107333 08/28/01 CKN New Data Sheet *A 121867 12/14/02 RBI Power up requirements added to Operating Conditions Information Document #: 38-07098 Rev. *A Page 5 of 5