CY26111 One-PLL General Purpose Clock Generator Features Benefits • Integrated phase-locked loop Internal PLL with up to 333 MHz internal operation • Low skew, low jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • 3.3V Operation with 2.5V Output Option Enables application compatibility • 16-TSSOP Industry standard package saves on board space Part Number Outputs Input Frequency Output Frequency Range 4 25 MHz 3 x 25 MHz, 1 x 125 MHz CY26111 Logic Block Diagram XIN Q OSC. Pin Configurations Φ CY26111 16-pin TSSOP LCLK1 25 MHz VCO XOUT OUTPUT MULTIPLEXER AND DIVIDERS P PLL LCLK2 25 MHz LCLK3 25 MHz CLK4 125 MHz XIN VDD 1 16 XOUT 2 15 AVDD 3 14 OE 4 13 CLK4 NC VSS AVSS 5 12 N/C VSSL 6 11 VDDL 7 10 8 9 NC LCLK3 LCLK1 LCLK2 OE VDDL VSSL VDD AVDD AVSS VSS Output Pin Default Frequency Unit LCLK1 7 25 MHz LCLK2 8 25 MHz LCLK3 9 25 MHz CLK4 15 125 MHz Cypress Semiconductor Corporation Document #: 38-07095 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY26111 Summary Name Pin Number Description XIN 1 Reference Input VDD 2 Voltage Supply AVDD 3 Analog Voltage Supply OE 4 Output Enable, OE = 0 three-state; OE = 1 active AVSS 5 Analog Ground VSSL 6 LCLK Ground LCLK 1 7 Clock output 1–25 MHz at VDDL level LCLK 2 8 Clock output 2–25 MHz at VDDL level LCLK 3 9 Clock output 3–25 MHz at VDDL level NC 10 No Connect - Reserved VDDL 11 LCLK Voltage Supply (2.5V or 3.3V) NC 12 No Connect - Reserved VSS 13 Ground NC 14 No Connect - Reserved CLK 4 15 Clock output 4 - 125 MHz XOUT[1] 16 Reference Output Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage –0.5 7.0 V VDDL I/O Supply Voltage 7.0 V TJ Junction Temperature 125 °C Digital Inputs AVSS – 0.3V AVDD + 0.3V V Digital Outputs referred to VDD VSS – 0.3V VDD + 0.3V V Digital Outputs referred to VDDL VSS – 0.3V VDDL +0.3V Electro-Static Discharge 2 V kV Recommended Operating Conditions Parameter Description Min. Typ. VDD VDDL Operating Voltage 3.0 Operating Voltage 2.375 TA Ambient Temperature 0 CLOAD Max. Load Capacitance fREF tPU Driven Reference Frequency Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Max. Unit 3.3 3.6 V 2.5 2.625 V 70 °C 15 pF 25 0.05 MHz 500 ms Note: 1. Float XOUT if XIN is externally driven. Document #: 38-07095 Rev. *A Page 2 of 5 CY26111 DC Electrical Characteristics Parameter[1] Name Description IOH Output High Current Min. Typ. VOH = VDD – 0.5, VDD/VDDL = 3.3V 12 24 Max. Unit mA IOL Output Low Current VOL = 0.5, VDD/VDDL = 3.3V 12 24 mA IOH Output High Current VOH = VDDL – 0.5, VDDL = 2.5V 8 16 mA 8 16 IOL Output Low Current VOL = 0.5, VDDL = 2.5V VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD CIN Input Capacitance OE Pin IIZ mA 0.7 VDD 0.3 VDD 7 pF mA µA Input Leakage Current OE Pin IVDD Supply Current AVDD/VDD Current 5 30 IVDDL Supply Current VDDL Current (VDDL=3.6V) 10 mA IVDDL Supply Current VDDL Current (VDDL = 2.625V) 8 mA AC Electrical Characteristics Parameter[1] Name DC Description Min. Typ. Max. Unit Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD 40 50 60 % t3 Rising Edge Slew Rate Output Clock Rise Time, 20% – 80% of VDD/VDDL = 3.3V 0.8 1.4 V/ns t3 Rising Edge Slew Rate Output Clock Rise Time, 20% – 80% of VDDL = 2.5V 0.6 1.2 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% – 20% of VDD/VDDL = 3.3V 0.8 1.4 V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% – 20% of VDDL = 2.5V 0.6 1.2 V/ns t5 Skew Delay between related outputs at rising edge 200 ps t9 Clock Jitter Peak to Peak period jitter 250 ps t10 PLL Lock Time 3 ms Note: 2. Not 100% tested. t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1. t3 t4 80% CLK 20% Figure 2. Rise and Fall Time Definitions. Document #: 38-07095 Rev. *A Page 3 of 5 CY26111 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY26111ZC Z16 16-Pin TSSOP Commercial 3.3V Test Circuit VDD CLK out 0.1 µF OUTPUTS CLOAD AVDD 0.1 µF GND Document #: 38-07095 Rev. *A Page 4 of 5 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY26111 Document Title: CY26111 One-PLL General Purpose Clock Generator Document Number: 38-07095 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107330 08/28/01 CKN New Data Sheet *A 121865 12/14/02 RBI Document #: 38-07095 Rev. *A Power up requirements added to Operating Conditions Information Page 5 of 5