LT1168 Low Power, Single Resistor Gain Programmable, Precision Instrumentation Amplifier DESCRIPTIO U FEATURES The LT ®1168 is a micropower, precision instrumentation amplifier that requires only one external resistor to set gains of 1 to 10,000. The low voltage noise of 10nV/√Hz (at 1kHz) is not compromised by low power dissipation (350µA typical for ±15V supplies). The wide supply range of ±2.3V to ±18V allows the LT1168 to fit into a wide variety of industrial as well as battery-powered applications. The high accuracy of the LT1168 is due to a 20ppm maximum nonlinearity and 0.4% max gain error (G = 10). Previous monolithic instrumentation amps cannot handle a 2k load resistor whereas the nonlinearity of the LT1168 is specified for loads as low as 2k. The LT1168 is laser trimmed for very low input offset voltage (40µV max), drift (0.3µV/°C), high CMRR (90dB, G = 1) and PSRR (103dB, G = 1). Low input bias currents of 250pA max are achieved with the use of superbeta processing. The output can handle capacitive loads up to 1000pF in any gain configuration while the inputs are ESD protected up to 13kV (human body). The LT1168 with two external 5k resistors passes the IEC 1000-4-2 level 4 specification. The LT1168 is a pin-for-pin improved second source for the AD620 and INA118. The LT1168, offered in 8-pin PDIP and SO packages, requires significantly less PC board area than discrete op amp resistor designs. These advantages make the LT1168 the most cost effective solution for precision instrumentation amplifier applications. Supply Current: 530µA Max Meets IEC 1000-4-2 Level 4 (±15kV) ESD Tests with Two External 5k Resistors Single Gain Set Resistor: G = 1 to 10,000 Gain Error: G = 10, 0.4% Max Input Offset Voltage Drift: 0.3µV/°C Max Gain Nonlinearity: G = 10, 20ppm Max Input Offset Voltage: 40µV Max Input Bias Current: 250pA Max PSRR at AV =1: 103dB Min CMRR at AV = 1: 90dB Min Wide Supply Range: ±2.3V to ±18V 1kHz Voltage Noise: 10nV/√Hz 0.1Hz to 10Hz Noise: 0.28µVP-P Available in 8-Pin PDIP and SO Packages ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ ■ ■ Bridge Amplifiers Strain Gauge Amplifiers Thermocouple Amplifiers Differential to Single-Ended Converters Differential Voltage to Current Converters Data Acquisition Battery-Powered and Portable Equipment Medical Instrumentation Scales , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO Single Supply* Pressure Monitor 1 3 8 3.5k 3.5k 3.5k + 40k 7 REF R1 G = 200 249Ω 6 LT1168 1 2 5 – 4 IN ADC LTC®1286 20k 3 40k 2 + 1/2 LT1112 1 DIGITAL DATA OUTPUT NONLINEARITY (100ppm/DIV) 5V 3.5k Gain Nonlinearity BI TECHNOLOGIES 67-8-3 R40KQ, (0.02% RATIO MATCH) AGND – 1168 TA01 G = 1000 RL = 2k VOUT = ±10V OUTPUT VOLTAGE (2V/DIV) 1168 TA01a *See Theory of Operation section 1 LT1168 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage ...................................................... ±20V Differential Input Voltage (Within the Supply Voltage) ..................................................... ±40V Input Voltage (Equal to Supply Voltage) ................ ±20V Input Current (Note 2) ....................................... ±20mA Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4) .. – 40°C to 85°C Specified Temperature Range LT1168AC/LT1168C (Note 5) ............. – 40°C to 85°C LT1168AI/LT1168I ............................. – 40°C to 85°C Storage Temperature Range ................. – 40°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW RG 1 8 RG –IN 2 – 7 +VS +IN 3 + 6 OUTPUT 5 REF –VS 4 LT1168ACN8 LT1168ACS8 LT1168AIN8 LT1168AIS8 LT1168CN8 LT1168CS8 LT1168IN8 LT1168IS8 N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 150°C/ W (N8) TJMAX = 150°C, θJA = 190°C/ W (S8) S8 PART MARKING 1168A 1168AI 1168 1168I Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL G TA = 25°C. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted. PARAMETER CONDITIONS (Note 6) Gain Range G = 1 + (49.4k/RG) Gain Error G=1 G = 10 (Note 7) G = 100 (Note 7) G = 1000 (Note 7) Gain Nonlinearity (Notes 7, 8) LT1168AC/LT1168AI MIN TYP MAX 1 10k LT1168C/LT1168I MIN TYP MAX 1 UNITS 10k 0.008 0.04 0.04 0.08 0.02 0.4 0.5 0.5 0.015 0.05 0.05 0.08 0.03 0.5 0.6 0.6 % % % % VO = ±10V, G = 1 VO = ±10V,G = 10 and 100 VO = ±10V, G = 1000 2 10 20 6 20 40 3 15 25 10 25 60 ppm ppm ppm VO = ±10V, G = 1, RL = 2k VO = ±10V,G = 10 and 100, RL = 2k VO = ±10V, G = 1000, RL = 2k 4 20 40 15 40 75 5 30 50 20 60 90 ppm ppm ppm VOST Total Input Referred Offset Voltage VOST = VOSI + VOSO/G VOSI Input Offset Voltage G = 1000, VS = ±5V to ±15V 15 40 20 60 µV VOSO Output Offset Voltage G = 1, VS = ±5V to ±15V 40 200 50 300 µV IOS Input Offset Current 50 300 60 450 pA IB Input Bias Current 40 250 80 500 pA en Input Noise Voltage, RTI 0.1Hz to 10Hz, G = 1 0.1Hz to 10Hz, G = 1000 Input Noise Voltage Density, RTI fO = 1kHz in RIN 2 2.00 0.28 µVP-P µVP-P 2.00 0.28 10 15 10 15 nV/√Hz Output Noise Voltage Density, RTI fO = 1kHz (Note 9) Input Noise Current fO = 0.1Hz to 10Hz 165 220 165 220 nV/√Hz 5 5 pAP-P Input Noise Current Density fO = 10Hz 74 74 fA/√Hz Input Resistance VIN = ±10V 300 1250 200 1250 GΩ LT1168 ELECTRICAL CHARACTERISTICS TA = 25°C. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted. LT1168AC/LT1168AI MIN TYP MAX LT1168C/LT1168I MIN TYP MAX fO = 100kHz 1.6 1.6 pF Common Mode Input Capacitance fO = 100kHz 1.6 1.6 pF Input Voltage Range G = 1, Other Input Grounded VS = ±2.3V to ±5V VS = ±5V to ±18V SYMBOL PARAMETER CONDITIONS (Note 6) CIN(DIFF) Differential Input Capacitance CIN(CM) VCM CMRR +VS – 1.2 +VS – 1.4 –VS + 1.9 –VS + 1.9 +VS – 1.2 +VS – 1.4 V V 1k Source Imbalance, VCM = 0V to ±10V G=1 G = 10 G = 100 G = 1000 90 106 120 126 95 115 135 140 85 100 110 120 95 115 135 140 dB dB dB dB Power Supply Rejection Ratio VS = ±2.3V to ±18V G=1 G = 10 G = 100 G = 1000 103 122 131 135 108 128 145 150 100 118 126 130 108 128 145 150 dB dB dB dB IS Supply Current VS = ±2.3V to ±18V VOUT Output Voltage Swing RL = 10k VS = ±2.3V to ±5V VS = ±5V to ±18V PSRR Common Mode Rejection Ratio –VS + 1.9 –VS + 1.9 UNITS IOUT Output Current BW Bandwidth G=1 G = 10 G = 100 G = 1000 SR Slew Rate G = 1, VOUT = ±10V Settling Time to 0.01% 10V Step G = 1 to 100 G = 1000 REFIN Reference Input Resistance IREFIN Reference Input Current VREF Reference Voltage Range AVREF Reference Gain to Output 350 –VS + 1.1 –VS + 1.2 20 530 +VS – 1.2 +VS – 1.3 32 –VS + 1.1 –VS + 1.2 20 +VS – 1.2 +VS – 1.3 V V 32 mA kHz kHz kHz kHz 0.5 V/µs 30 200 30 200 µs µs 60 60 kΩ 0.5 VREF = 0V µA 400 200 13 1 400 200 13 1 0.3 530 350 0.3 18 –VS + 1.6 µA 18 +VS – 1.6 –VS + 1.6 1 ± 0.0001 +VS – 1.6 V 1 ± 0.0001 The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C temperature range. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted. SYMBOL PARAMETER ∆G/∆T CONDITIONS (Note 6) MIN LT1168AC TYP MAX MIN LT1168C TYP MAX UNITS Gain Error G=1 G = 10 (Note 7) G = 100 (Note 7) G = 1000 (Note 7) ● ● ● ● 0.01 0.40 0.45 0.50 0.03 1.5 1.6 1.7 0.012 0.500 0.550 0.600 0.04 1.6 1.7 1.8 % % % % Gain Nonlinearity (Notes 7, 8) VOUT = ±10V, G = 1 VOUT = ±10V, G = 10 and 100 VOUT = ±10V, G = 1000 ● ● ● 2 7 25 15 30 60 3 10 30 20 35 80 ppm ppm ppm Gain vs Temperature G < 1000 (Note 7) ● 100 200 100 200 ppm/°C 3 LT1168 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C temperature range. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted. SYMBOL PARAMETER CONDITIONS (Note 6) MIN LT1168AC TYP MAX 60 VOST Total Input Referred Offset Voltage VOSI Input Offset Voltage VS = ±5V to ±15V ● 18 VOSIH Input Offset Voltage Hysteresis (Notes 7, 10) ● 3.0 VOSO Output Offset Voltage VS = ±5V to ±15V ● 60 MIN LT1168C TYP MAX 23 80 UNITS VOST = VOSI + VOSO/G µV µV 3.0 380 70 500 µV µV VOSOH Output Offset Voltage Hysteresis (Notes 7, 10) ● 30 VOSI/T Input Offset Drift (RTI) (Note 9) ● 0.05 0.3 0.06 0.4 µV/°C VOSO/T Output Offset Drift (Note 9) ● 0.7 3 0.8 4 µV/°C 400 120 550 IOS Input Offset Current ● 100 IOS/T Input Offset Current Drift ● 0.3 IB Input Bias Current ● 65 IB/T Input Bias Current Drift ● 1.4 VCM Input Voltage Range 30 0.4 350 105 pA pA/°C 600 1.4 pA pA/°C G = 1, Other Input Grounded VS = ±2.3V to ±5V VS = ±5V to ±18V ● ● –VS + 2.1 –VS + 2.1 1k Source Imbalance, VCM = 0V to ±10V G=1 G = 10 G = 100 G = 1000 ● ● ● ● 88 100 115 117 92 110 120 135 83 97 113 114 92 110 120 135 dB dB dB dB Power Supply Rejection Ratio VS = ±2.3V to ±18V G=1 G = 10 G = 100 G = 1000 ● ● ● ● 102 123 127 129 115 130 135 145 98 118 124 126 115 130 135 145 dB dB dB dB IS Supply Current VS = ±2.3V to ±18V ● VOUT Output Voltage Swing RL = 10k VS = ±2.3V to ±5V VS = ±5V to ±18V ● ● –VS + 1.4 –VS + 1.6 ● 16 25 0.48 CMRR PSRR Common Mode Rejection Ratio +VS – 1.3 –VS + 2.1 +VS – 1.4 –VS + 2.1 390 IOUT Output Current SR Slew Rate G = 1, VOUT = ±10V ● 0.25 VREF Voltage Range (Note 9) ● –VS + 1.6 615 +VS – 1.3 +VS – 1.4 390 +VS – 1.3 –VS + 1.4 +VS – 1.5 –VS + 1.6 16 0.25 V V 615 µA +VS – 1.3 +VS – 1.5 V V 25 mA 0.48 V/µs +VS – 1.6 –VS + 1.6 +VS – 1.6 V The ● denotes the specifications which apply over the – 40°C ≤ TA ≤ 85°C temperature range. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted. (Note 8) SYMBOL PARAMETER MIN LT1168AI TYP MAX MIN LT1168I TYP MAX UNITS Gain Error G=1 G = 10 (Note 7) G = 100 (Note 7) G = 1000 (Note 7) ● ● ● ● 0.014 0.600 0.600 0.600 0.04 1.9 2.0 2.1 0.015 0.700 0.700 0.700 0.05 2.0 2.1 2.2 % % % % GN Gain Nonlinearity (Notes 7, 8) VO = ±10V, G = 1 VO = ±10V, G = 10 and 100 VO = ±10V, G = 1000 ● ● ● 3 10 30 20 35 70 5 15 35 25 40 100 ppm ppm ppm ∆G/∆T Gain vs Temperature G < 1000 (Note 7) ● 100 200 100 200 ppm/°C 4 CONDITIONS (Note 6) LT1168 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the – 40°C ≤ TA ≤ 85°C temperature range. VS = ±15V, VCM = 0V, RL = 10k unless otherwise noted. (Note 5) SYMBOL PARAMETER CONDITIONS (Note 6) MIN LT1168AI TYP MAX LT1168I TYP MAX UNITS 75 25 100 µV 500 200 600 µV MIN VOST Total Input Referred Offset Voltage VOSI Input Offset Voltage VOSIH Input Offset Voltage Hysteresis ● 3.0 VOSO Output Offset Voltage ● 180 VOSOH Output Offset Voltage Hysteresis (Notes 7, 10) ● 30 VOSI/T Input Offset Drift (RTI) (Note 9) ● 0.05 0.3 0.06 0.4 µV/°C VOSO/T Output Offset Drift (Note 9) ● 0.8 5 1 6 µV/°C IOS Input Offset Current ● 110 550 120 700 IOS/T Input Offset Current Drift ● 0.3 IB Input Bias Current ● 120 500 220 IB/T Input Bias Current Drift ● 1.4 VCM Input Voltage Range VS = ±2.3V to ±5V VS = ±5V to ±18V ● ● –VS + 2.1 –VS + 2.1 CMRR Common Mode Rejection Ratio 1k Source Imbalance, VCM = 0V to ±10V G=1 G = 10 G = 100 G = 1000 ● ● ● ● 86 98 114 116 90 105 118 133 81 95 112 112 90 105 118 133 dB dB dB dB VS = ±2.3V to ±18V G=1 G = 10 G = 100 G = 1000 ● ● ● ● 100 120 125 128 112 125 132 140 95 115 120 125 112 125 132 140 dB dB dB dB PSRR Power Supply Rejection Ratio IS Supply Current VOUT Output Voltage Swing IOUT VOST = VOSI + VOSO/G 20 ● (Notes 7, 10) VS = ±2.3V to ±5V VS = ±5V to ±18V µV 30 0.3 –VS + 2.1 –VS + 2.1 650 pA pA/°C +VS – 1.3 +VS – 1.4 420 650 µA +VS – 1.3 +VS – 1.5 V V –VS + 1.4 –VS + 1.6 Output Current ● 15 22 15 22 mA SR Slew Rate ● 0.22 0.41 0.22 0.42 V/µs VREF Voltage Range ● –VS + 1.6 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be imparied. Note 2: If the input voltage exceeds the supplies, the input current should be limited to less than 20mA. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum. Note 4: The LT1168AC/LT1168C are guaranteed functional over the operating temperature range of – 40°C and 85°C. Note 5: The LT1168AC/LT1168C are guaranteed to meet specified performance from 0°C to 70°C. The LT1168AC/LT1168C are designed, characterized and expected to meet specified performance from – 40°C to 85°C but are not tested or QA sampled at these temperatures. The LT1168AI/LT1168I are guaranteed to meet specified performance from – 40°C to 85°C. +VS – 1.6 –VS + 1.4 –VS + 1.6 V V ● ● (Note 9) +VS – 1.3 +VS – 1.5 pA pA/°C 800 1.4 +VS – 1.3 +VS – 1.4 420 ● µV 3.0 –VS + 1.6 +VS – 1.6 V Note 6: Typical parameters are defined as the 60% of the yield parameter distribution. Note 7: Does not include the tolerance of the external gain resistor RG. Note 8: This parameter is measured in a high speed automatic tester that does not measure the thermal effects with longer time constants. The magnitude of these thermal effects are dependent on the package used, heat sinking and air flow conditions. Note 9: This parameter is not 100% tested. Note 10: Hysteresis in offset voltage is created by package stress that differs depending on whether the IC was previously at a higher or lower temperature. Offset voltage hysteresis is always measured at 25°C, but the IC is cycled to 85°C I-grade (or 70°C C-grade) or – 40°C I-grade (0°C C-grade) before successive measurement. 60% of the parts will pass the typical limit on the data sheet. 5 LT1168 U W TYPICAL PERFOR A CE CHARACTERISTICS Distribution of Output Offset Voltage 60 VS = ±15V 55 T = 25°C A 50 G = 1000 299 N8 (2 LOTS) 337 S0-8 (2 LOTS) 636 TOTAL PARTS 45 PERCENT OF UNITS (%) 40 35 30 25 20 15 40 35 30 25 20 15 10 5 5 40 –20 0 20 –40 INPUT OFFSET VOLTAGE (µV) 1168 G01 20 15 10 5 5 VS = ±15V 40 TA = 30°C G=1 30 4 PARTS FROM 4 LOTS 20 WARMED UP 10 0 –10 –20 –30 –40 –50 –0.35 –0.25 –0.15 –0.05 0.05 INPUT OFFSET VOLTAGE DRIFT (µV/°C) 1 0 –1 –2 –3 –4 –5 0 2 1 TIME (MONTHS) 0 3 2 1 TIME (MONTHS) 3 1168 G05 60 VS = ±15V TA = 25°C G=1 50 1168 G05 Voltage Noise Density vs Frequency VS = ±15V TA = 25°C G = 1000 40 25 SO-8 GAIN (dB) CHANGE IN TOTAL INPUT REFERRED OFFSET VOLTAGE (µV) VS = ±15V 4 TA = 30°C G = 1000 3 4 PARTS FROM 4 LOTS 2 WARMED UP Gain vs Frequency 20 15 N-8 10 30 G = 100 20 G = 10 10 0 G=1 5 –10 0 1 2 3 4 TIME AFTER POWER-ON (MINUTES) 0.2 –0.6 –0.2 –1.0 –1.4 OUTPUT OFFSET VOLTAGE DRIFT (µV/°C) 1168 G03 50 Warm-Up Drift 5 –20 0.01 1000 1/f CORNER = 2Hz GAIN = 1 1 10 FREQUENCY (kHz) 100 1000 VS = ±15V TA = 25°C 100 1/f CORNER = 7Hz GAIN = 10 GAIN = 100, 1000 10 1/f CORNER = 3Hz BW LIMIT GAIN = 100 BW LIMIT GAIN = 1000 1 0.1 1168 G08 1168 G07 6 10 Input Offset Voltage Long-Term Drift 1168 G04 0 15 0 –1.8 60 CHANGE IN INPUT OFFSET VOLTAGE (µV) CHANGE IN OUTPUT OFFSET VOLTAGE (µV) PERCENT OF UNITS (%) VS = ±15V T = –40°C TO 85°C 30 GA= 1000 97 N8 (2 LOTS) 25 49 S0-8 (1 LOT) 146 TOTAL PARTS 30 20 Output Offset Voltage Long-Term Drift 35 35 25 1168 G02 Distribution of Input Offset Voltage Drift 0 –0.45 97 N8 (2 LOTS) 49 S0-8 (1 LOT) 146 TOTAL PARTS 5 0 –60 150 VS = ±15V TA = –40°C TO 85°C 30 G = 1 45 10 0 100 0 50 –150 –100 –50 OUTPUT OFFSET VOLTAGE (µV) 35 299 N8 (2 LOTS) 337 S0-8 (2 LOTS) 636 TOTAL PARTS VOLTAGE NOISE DENSITY (nV/√Hz) PERCENT OF UNITS (%) VS = ±15V 55 T = 25°C A 50 G = 1 Distribution of Output Offset Voltage Drift PERCENT OF UNITS (%) 60 Distribution of Input Offset Voltage 1 10 100 1k FREQUENCY (Hz) 10k 100k 1168 G09 LT1168 U W TYPICAL PERFOR A CE CHARACTERISTICS 0.1Hz to 10Hz Noise Voltage, G=1 0.1Hz to 10Hz Noise Voltage, RTI G = 1000 Current Noise Density vs Frequency 1000 CURRENT NOISE DENSITY (fA/√Hz) VS = ±15V TA = 25°C NOISE VOLTAGE (2µV/DIV) NOISE VOLTAGE (0.2µV/DIV) VS = ±15V TA = 25°C VS = ±15V TA = 25°C RS 100 1/f CORNER = 55Hz 10 1 2 3 4 5 6 TIME (SEC) 7 8 9 1 0 10 2 3 4 5 6 TIME (SEC) 7 8 1168 G10 9 Short-Circuit Current vs Time 50 OUTPUT CURRENT (mA) (SINK) (SOURCE) NOISE CURRENT (5pA/DIV) Output Impedance vs Frequency 1k VS = ±15V 40 TA = 25°C 20 10 TA = 85°C 0 – 10 TA = 85°C – 20 – 30 TA = 25°C – 40 TA = – 40°C – 50 1 2 3 4 5 6 TIME (SEC) 7 8 9 70 60 50 G=1 40 30 VS ±15V TA = 25°C G = 10 20 20 10 G = 100, 1000 10 100 1000 CAPACITIVE LOAD (pF) 10000 1168 G16 10k 100k FREQUENCY (Hz) 0 –200 +IB +IB 1M 1168 G15 Input Offset Current 30 10 0 1k 50 302 N8 (2 LOTS) 313 SO-8 (2 LOTS) 615 TOTAL PARTS 40 OUTPUT VOLTAGE (V) OVERSHOOT (%) 50 VS = ±15V VOUT = ± 50mV RL = ∞ 80 1 Input Bias Current Overshoot vs Capacitive Load 90 10 1168 G14 1168 G13 100 100 0.1 2 1 0 3 TIME FROM OUTPUT SHORT TO GROUND (MINUTES) 10 VS = ±15V TA = 25°C 40 PERCENT OF UNITS (%) 0 VS = ± 15V TA = 25°C G = 1 TO 1000 TA = – 40°C 30 1000 1168 G12 1168 G11 0.1Hz to 10Hz Current Noise VS = ±15V TA = 25°C 10 100 FREQUENCY (Hz) 1 10 OUTPUT IMPEDANCE (Ω) 0 302 N8 (2 LOTS) 313 SO-8 (2 LOTS) 615 TOTAL PARTS 30 20 10 –IB –120 40 120 –40 INPUT BIAS CURRENT (pA) 200 1168 G17 0 –120 –80 0 40 80 –40 INPUT OFFSET CURRENT (pA) 120 1168 G18 7 LT1168 U W TYPICAL PERFOR A CE CHARACTERISTICS Change in Input Bias Current for VCM = 20V 10 302 N8 (2 LOTS) 313 SO-8 (2 LOTS) 615 TOTAL PARTS 6 14 12 10 RINCM = 5TΩ RINCM = 700GΩ 8 6 4 VOUT 0V 0V –2 VOUT –4 –6 –8 –10 0 TO 0.01% 0 2 4 8 12 16 20 24 28 32 34 CHANGE IN INPUT BIAS CURRENT (pA) TO 0.1% 1 SETTLING TIME (µs) G = 100, FALLING EDGE 26 VS = ± 15V TA = 25°C RL = 1k STEP SIZE = 10V G = 10, RISING EDGE 22 20 18 16 10 30 100 300 LOAD CAPACITANCE (pF) 400 Falling Edge Settling Time (0.10%) VS = ±15V VCM = 0V 300 200 0 –5 0.10 –10 0.05 0 0.05 –5 0.10 IOS 100 0 0 IB –100 –200 –10 –300 5µs/DIV –400 –500 –75 –50 –25 1000 0 25 50 TEMPERATURE 75 Rising Edge Settling Time (0.10%) 100 125 Settling Time (0.01%) vs Load Capacitance Undistorted Output Swing vs Frequency 35 0.05 VOUT (V) 0 10 0.05 5 0.10 5µs/DIV t=0 TA = 25°C VS = ±15V RL = 2k CL = 15pF 1168 G25 G = 100, RISING EDGE PEAK-TO-PEAK OUTPUT SWING (V) 0.10 0 32 SETTLING TIME (µs) 5 8 G = 100, FALLING EDGE 34 SETTLING (%) VIN (V) 36 10 1168 G24 t=0 TA = 25°C VS = ±15V RL = 2k CL = 15pF 1168 G23 1168 G22 0 1000 1168 G21 VIN (V) G = 1, RISING EDGE G = 10, FALLING EDGE 100 GAIN VOUT (V) G = 1, FALLING EDGE G = 100, RISING EDGE 10 SETTLING (%) INPUT BIAS AND OFFSET CURRENT (pA) 500 24 1 8 10 12 14 16 18 20 22 24 26 28 30 32 SETTLING TIME (µs) Input Bias and Offset Current vs Temperature 34 28 10 1168 G20 Settling Time (0.1%) vs Load Capacitance 30 100 TO 0.01% 1168 G19 32 VS = ± 15V TA = 25°C ∆VOUT = 10V TO 0.01% TO 0.1% 2 4 0 VS = ±15 G=1 TA = 25°C CL = 30pF RL = 1k 8 OUTPUT STEP (V) PERCENT OF UNITS (%) VS = ±15V 18 VCM = ±10V TA = 25°C 16 Settling Time vs Gain 1000 SETTLING TIME (µs) 20 Settling Time vs Step Size G = 1, RISING EDGE 30 28 G = 10, FALLING EDGE 26 24 G = 10, RISING EDGE 22 VS = ± 15V TA = 25°C RL = 1k STEP SIZE = 10V 20 18 10 G = 1, FALLING EDGE 30 100 300 LOAD CAPACITANCE (pF) 30 G = 10, 100, 1000 25 G=1 VS = ±15V TA = 25°C 20 15 10 5 0 1000 1168 G26 1 10 100 FREQUENCY (kHz) 1000 1168 G27 LT1168 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Voltage Range vs Output Voltage for Various Gains VS = ± 15V 85°C 25°C – 40°C + VS – 1.0 INPUT VOLTAGE RANGE WITH RESPECT TO NEGATIVE SUPPLY (–VS + VIN) + VS + VS – 0.5 + VS – 1.5 + VS – 2.0 + VS – 2.5 – VS + 2.5 – VS + 2.0 – VS + 1.5 – VS + 1.0 – VS + 0.5 – VS 0.01 0.1 1 10 OUTPUT CURRENT (mA) 100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 –15 VS = ±15V TA = 25°C G=1 G=2 VOUT = –VS + 1.2V G = 100 G = 10 G = 100 G = 10 G=2 VOUT = +VS – 1.3V G=1 –VCM = –VS + 1.9V –11 –7 3 –3 VOUT (V) 7 11 1168 G28 Slew Rate vs Temperature 1.0 VS = ±15V 0.8 SINKING CURRENT SLEW RATE (V/µs) OUTPUT CURRENT (mA) 50 40 30 SOURCING CURRENT VS = ±15V VOUT = ±10V G=1 0.6 +SLEW –SLEW 0.4 0.2 20 10 –50 –25 50 25 0 TEMPERATURE (°C) 75 0 –50 100 –25 50 25 0 TEMPERATURE (°C) 1168 G31 5V/DIV 20mV/DIV 5V/DIV 50µs/DIV 100 Large-Signal Transient Response Small-Signal Transient Response Large-Signal Transient Response 75 1168 G30 1168 G29 G=1 VS = ±15V RL = 2k CL = 60pF 15 1168 G43 Output Short-Circuit Current vs Temperature 60 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 –13 –14 –15 +VCM = +VS – 1.4V INPUT VOLTAGE RANGE WITH RESPECT TO POSITIVE SUPPLY (+VS – VIN) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGE (SINK) (SOURCE) Output Voltage Swing vs Load Current G=1 VS = ±15V RL = 2k CL = 60pF 10µs/DIV 1168 G32 G = 10 VS = ±15V RL = 2k CL = 60pF 50µs/DIV 1168 G33 9 LT1168 U W TYPICAL PERFOR A CE CHARACTERISTICS Small-Signal Transient Response Small-Signal Transient Response 20mV/DIV 5V/DIV 20mV/DIV Large-Signal Transient Response 1168 G34 50µs/DIV G = 100 VS = ±15V RL = 2k CL = 60pF 1168 G35 G = 100 VS = ±15V RL = 2k CL = 60pF 20mV/DIV 5V/DIV 200µs/DIV G = 1000 VS = ±15V RL = 2k CL = 60pF 1168 G37 200µs/DIV G = 1000 VS = ±15V RL = 2k CL = 60pF 1168 G36 10µs/DIV Negative Power Supply Rejection Ratio vs Frequency Small-Signal Transient Response Large-Signal Transient Response NEGATIVE POWR SUPPLY REJECTION RATIO (dB) 10µs/DIV G = 10 VS = ±15V RL = 2k CL = 60pF 1168 G38 160 G = 1000 140 G = 100 120 G = 10 100 G=1 80 60 40 20 VS = ±15V TA = 25°C 0 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1168 G39 Common Mode Rejection Ratio vs Frequency (1k Source Imbalance) 160 G = 100 120 G = 10 100 G=1 80 60 40 0 VS = ±15V TA = 25°C 0.1 1 10k 100k 1168 G40 10 G = 100 G = 10 100 G=1 80 60 40 20 1 10 100 1k FREQUENCY (Hz) 0.4 0.3 0.2 VS = ±15V TA = 25°C 1k SOURCE IMBALANCE 0.1 VS = ±15V 0.5 120 0 10 100 1k FREQUENCY (Hz) G = 1000 140 SUPPLY CURRENT (mA) G = 1000 140 20 Supply Current vs Temperature 0.6 160 COMMON MODE REJECTION RATIO (dB) POSITIVE POWR SUPPLY REJECTION RATIO (dB) Positive Power Supply Rejection Ratio vs Frequency 10k 100k 1168 G41 0.1 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1168 G42 LT1168 W BLOCK DIAGRA +VS VB R5 30k + R6 30k 6 OUTPUT A1 – R3 400Ω –IN C1 2 Q1 R1 24.7k – –VS + A3 RG 1 RG 8 –VS VB +VS + R7 30k R8 30k 5 REF A2 – R4 400Ω +IN 3 C2 Q2 –VS R2 24.7k 7 +VS –VS 4 –VS PREAMP STAGE DIFFERENCE AMPLIFIER STAGE 1168 F01 Figure 1. Block Diagram U THEORY OF OPERATIO The LT1168 is a modified version of the three op amp instrumentation amplifier. Laser trimming and monolithic construction allow tight matching and tracking of circuit parameters over the specified temperature range. Refer to the block diagram (Figure 1) to understand the following circuit description. The collector currents in Q1 and Q2 are trimmed to minimize offset voltage drift, thus assuring a high level of performance. R1 and R2 are trimmed to an absolute value of 24.7k to assure that the gain can be set accurately (0.6% at G = 100) with only one external resistor RG. The value of RG in parallel with R1 (R2) determines the transconductance of the preamp stage. As RG is reduced for larger programmed gains, the transconductance of the input preamp stage increases to that of the input transistors Q1 and Q2. This increases the open-loop gain when the programmed gain is increased, reducing the input referred gain related errors and noise. The input voltage noise at gains greater than 50 is determined only by Q1 and Q2. At lower gains the noise of the difference amplifier and preamp gain setting resistors increase the noise. The gain bandwidth product is determined by C1, C2 and the preamp transconductance which increases with programmed gain. Therefore, the bandwidth does not drop proportionally with gain. The input transistors Q1 and Q2 offer excellent matching, which is inherent in NPN bipolar transistors, as well as picoampere input bias current due to superbeta processing. The collector currents in Q1 and Q2 are held constant due to the feedback through the Q1-A1-R1 loop and Q2-A2-R2 loop which in turn impresses the differential input voltage across the external gain set resistor RG. Since the current that flows through RG also flows through R1 and R2, the ratios provide a gained-up differential 11 LT1168 U THEORY OF OPERATIO voltage, G = (R1 + R2)/RG, to the unity-gain difference amplifier A3. The common mode voltage is removed by A3, resulting in a single-ended output voltage referenced to the voltage on the REF pin. The resulting gain equation is: G = (49.4kΩ / RG) + 1 solving for the gain set resistor gives: Input Voltage Range RG = 49.4kΩ /(G – 1) Table 1 shows appropriate 1% resistor values for a variety of gains. Table 1 DESIRED GAIN RG CLOSEST 1% VALUE RESULTANT GAIN 1 Open Open 1 2 49400Ω 49900Ω 1.99 5 12350Ω 12400Ω 4.984 10 5488.89Ω 5490Ω 9.998 20 2600Ω 2610Ω 19.93 50 1008.16Ω 1000Ω 50.4 100 498.99Ω 499Ω 99.998 200 248.24Ω 249Ω 199.4 500 99Ω 100Ω 495 1000 49.95Ω 49.4Ω 1001 Input and Output Offset Voltage The offset voltage of the LT1168 has two components: the output offset and the input offset. The total offset voltage referred to the input (RTI) is found by dividing the output offset by the programmed gain (G) and adding it to the input offset. At high gains the input offset voltage dominates, whereas at low gains the output offset voltage dominates. The total offset voltage is: Total input offset voltage (RTI) = input offset + (output offset/G) Total output offset voltage (RTO) = (input offset • G) + output offset Reference Terminal The reference terminal is one end of one of the four 30k resistors around the difference amplifier. The output 12 voltage of the LT1168 (Pin 6) is referenced to the voltage on the reference terminal (Pin 5). Resistance in series with the REF pin must be minimized for best common mode rejection. For example, a 6Ω resistance from the REF pin to ground will not only increase the gain error by 0.02% but will lower the CMRR to 80dB. The input voltage range for the LT1168 is specified in the data sheet at 1.4V below the positive supply to 1.9V above the negative supply for a gain of one. As the gain increases the input voltage range decreases. This is due to the IR drop across the internal gain resistors R1 and R2 in Figure 1. For the unity gain condition there is no IR drop across the gain resistors R1 and R2, the output of the GM amplifiers is just the differential input voltage at Pin 2 and Pin 3 (level shifted by one VBE from Q1 and Q2). When a gain resistor is connected across Pins 1 and 8, the output swing of the GM cells is now the differential input voltage (level shifted by VBE) plus the differential voltage times the gain (ratio of the internal gain resistors to the external gain resistor across Pins 1 and 8). To calculate how close to the positive rail the input (VIN) can swing for a gain of 2 and a maximum expected output swing of 10V, use the following equation: + VS – VIN = – 0.5 – (VOUT/G) • (G – 1)/2 Substituting yields: – 0.5 – (10/2) • (1/2) = – 3V below the positive supply or 12V for a 15V supply. To calculate how far above the negative supply the input can swing for a gain of 10 with a maximum expected output swing of –10V, the equation for the negative case is: – VS + VIN = 1.5 – (VOUT/G) • (G – 1)/2 Substituting yields: 1.5 – (–10/10) • 9/2 = 6V above the negative supply or – 9V for a negative supply voltage of –15V. Figures 2 and 3 are for the positive common mode and negative common mode cases respectively. LT1168 U THEORY OF OPERATIO INPUT VOLTAGE WITH RESPECT TO POSITIVE SUPPLY (+VS – VIN)(V) G=1 AREA OF OPERATION –1 G=2 AREA OF OPERATION –2 –3 G = 100 AREA OF OPERATION –4 G = 10 AREA OF OPERATION –5 –6 T = 25°C A INPUT COMMON –7 MODE RANGE IS BELOW THE CURVE –8 2 4 8 6 0 VOUT (V) 10 12 14 1168 F02 Figure 2. Positive Input Range vs Output Voltage for Different Gains G = 10 AREA OF OPERATION 8 7 TA = 25°C INPUT COMMON MODE RANGE IS ABOVE THE CURVE Output Offset Trimming The LT1168 is laser trimmed for low offset voltage so that no external offset trimming is required for most applications. In the event that the offset needs to be adjusted, the circuit in Figure 4 is an example of an optional offset adjust circuit. The op amp buffer provides a low impedance to the REF pin where resistance must be kept to minimum for best CMRR and lowest gain error. RG G = 100 AREA OF OPERATION 4 –VS –14 +IN G=1 AREA OF OPERATION –12 –10 –8 –6 VOUT (V) 6 LT1168 3 OUTPUT –4 –2 +VS REF 8 G=2 3 AREA OF OPERATION 2 1 – 1 6 5 2 –IN + 5 10mV 1/2 LT1112 ±10mV ADJUSTMENT RANGE 100Ω + INPUT VOLTAGE RANGE WITH RESPECT TO NEGATIVE SUPPLY (–VS + VIN)(V) 9 potential, the voltage on the REF pin can be further level shifted. The application in the front of this data sheet, Single Supply Pressure Monitor, is an example. An op amp is used to buffer the voltage on the REF pin since a parasitic series resistance will degrade the CMRR. – +VS 10k 100Ω 0 –10mV 1168 F03 Figure 3. Negative Input Voltage Range vs Output Voltage for Various Gains –VS 1168 F04 Figure 4. Optional Trimming of Output Offset Voltage Single Supply Operation For best results under single supply operation, the REF pin should be raised above the negative supply (Pin 4) and one of the inputs should be at least 2.5V above ground. The barometer application later in this data sheet is an example that satisfies these conditions. The resistance RSET from the bridge transducer to ground sets the operating current for the bridge, and with R6, also has the effect of raising the input common mode voltage. The output of the LT1168 is always inside the specified range since the barometric pressure rarely goes low enough to cause the output to clip (30.00 inches of Hg corresponds to 3.000V). For applications that require the output to swing at or below the REF Input Bias Current Return Path The low input bias current of the LT1168 (250pA) and the high input impedance (200GΩ) allow the use of high impedance sources without introducing additional offset voltage errors, even when the full common mode range is required. However, a path must be provided for the input bias currents of both inputs when a purely differential signal is being amplified. Without this path the inputs will float to either rail and exceed the input common mode range of the LT1168, resulting in a saturated input stage. Figure 5 shows three examples of an input bias current 13 LT1168 U THEORY OF OPERATIO path. The first example is of a purely differential signal source with a 10kΩ input current path to ground. Since the impedance of the signal source is low, only one resistor is needed. Two matching resistors are needed for higher impedance signal sources as shown in the second example. Balancing the input impedance improves both common mode rejection and DC offset. – – MICROPHONE, HYDROPHONE, ETC LT1168 THERMOCOUPLE – LT1168 + LT1168 + 200k 10k + 200k CENTER-TAP PROVIDES BIAS CURRENT RETURN 1168 F05 Figure 5. Providing an Input Common Mode Current Path U W U U APPLICATIO S I FOR ATIO The LT1168 is a low power precision instrumentation amplifier that requires only one external resistor to accurately set the gain anywhere from 1 to 1000. The LT1168 is trimmed for critical DC parameters such as gain error (0.04%, G = 10), input offset voltage (40µV, RTI), CMRR (90dB min, G = 1) and PSRR (103dB min, G = 1). These trims allow the amplifier to achieve very high DC accuracy. The LT1168 achieves low input bias current of just 250pA (max) through the use of superbeta processing. The output can handle capacitive loads up to 1000pF in any gain configuration and the inputs are protected against ESD strikes up to ±13kV (human body). Input Protection The LT1168 can safely handle up to ±20mA of input current in an overload condition. Adding an external 5k input resistor in series with each input allows DC input fault voltage up to ±100V and improves the ESD immunity to ±8kV (contact) and ±15kV (air discharge), which is the IEC 1000-4-2 level 4 specification. If lower value input resistors must be used, a clamp diode from the positive supply to each input will maintain the IEC 1000-4-2 14 specification to level 4 for both air and contact discharge. A 2N4393 drain/source to gate is a good low leakage diode for use with resistors between 1k and 20k, see Figure 6. The input resistors should be carbon and not metal film or carbon film in order to withstand the fault conditions. J1 2N4393 J2 2N4393 RIN OPTIONAL FOR RIN < 20k + RG RIN +VS LT1168 OUT REF – –VS 1168 F06 Figure 6. Input Protection RFI Reduction In many industrial and data acquisition applications, instrumentation amplifiers are used to accurately amplify small signals in the presence of large common mode LT1168 U W U U APPLICATIO S I FOR ATIO voltages or high levels of noise. Typically, the sources of these very small signals (on the order of microvolts or millivolts) are sensors that can be a significant distance from the signal conditioning circuit. Although these sensors may be connected to signal conditioning circuitry, using shielded or unshielded twisted-pair cabling, the cabling may act as antennae, conveying very high frequency interference directly into the input stage of the LT1168. The amplitude and frequency of the interference can have an adverse effect on an instrumentation amplifier’s input stage by causing an unwanted DC shift in the amplifier’s input offset voltage. This well known effect is called RFI rectification and is produced when out-of-band interference is coupled (inductively, capacitively or via radiation) and rectified by the instrumentation amplifier’s input transistors. These transistors act as high frequency signal detectors, in the same way diodes were used as RF envelope detectors in early radio designs. Regardless of the type of interference or the method by which it is coupled into the circuit, an out-of-band error signal appears in series with the instrumentation amplifier’s inputs. To significantly reduce the effect of these out-of-band signals on the input offset voltage of instrumentation amplifiers, simple lowpass filters can be used at the inputs. This filter should be located very close to the input pins of the circuit. An effective filter configuration is illustrated in Figure 7, where three capacitors have been added to the inputs of the LT1168. Capacitors CXCM1 and CXCM2 form lowpass filters with the external series resistors RS1, 2 to any out-of-band signal appearing on each of the input traces. Capacitor CXD forms a filter to reduce any unwanted signal that would appear across the input traces. An added benefit to using CXD is that the circuit’s AC common mode rejection is not degraded due to common mode capacitive imbalance. The differential mode and common mode time constants associated with the capacitors are: tDM(LPF) = (RS1 + RS2)(CXD + CXCM1 + CXCM2) tCM(LPF) = (RS1|| RS2)(CXCM1+ CXCM2) Setting the time constants requires a knowledge of the frequency, or frequencies of the interference. Once this frequency is known, the common mode time constants can be set followed by the differential mode time constant. To avoid any possibility of inadvertently affecting the signal to be processed, set the common mode time constant an order of magnitude (or more) smaller than the differential mode time constant. Set the common mode time constants such that they do not degrade the LT1168 inherent AC CMR. Then the differential mode time constant can be set for the bandwidth required for the application. Setting the differential mode time constant close to the sensor’s BW also minimizes any noise pickup along the leads. To avoid any possibility of common mode to differential mode signal conversion, match the common mode time constants to 1% or better. If the sensor is an RTD or a resistive strain gauge and is in proximity to the instrumentation amplifier, then the series resistors RS1, 2 can be omitted. IN + CXD 0.1µF IN – +VS RS1 CXCM1 1.6k 0.001µF RS2 1.6k + RG LT1168 VOUT – CXCM2 0.001µF –VS f– 3dB ≈ 500Hz 1168 F07 EXTERNAL RFI FILTER Figure 7. Adding a Simple RC Filter at the Inputs to an Instrumentation Amplifier is Effective in Reducing Rectification of High Frequency Out-of-Band Signals Nerve Impulse Amplifier The LT1168’s low current noise makes it ideal for EMG monitors that have high source impedances. Demonstrating the LT1168’s ability to amplify low level signals, the circuit in Figure 8 takes advantage of the amplifier’s high gain and low noise operation. This circuit amplifies the low level nerve impulse signals received from a patient at Pins␣ 2 and 3. RG and the parallel combination of R3 and R4 set a gain of ten. The potential on LT1112’s Pin 1 creates 15 LT1168 U W U U APPLICATIO S I FOR ATIO a ground for the common mode signal. C1 was chosen to maintain the stability of the patient ground. The LT1168’s high CMRR ensures that the desired differential signal is amplified and unwanted common mode signals are attenuated. Since the DC portion of the signal is not important, R6 and C2 make up a 0.3Hz highpass filter. The AC signal at LT1112’s Pin 5 is amplified by a gain of 101 set by R7/R8 +1. The parallel combination of C3 and R7 form a lowpass filter that decreases this gain at frequencies above 1kHz. The ability to operate at ±3V on 350µA of supply current makes the LT1168 ideal for battery-powered applications. Total supply current for this application is 1.05mA. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm. 3 8 +IN R3 30k R1 12k R2 1M R4 30k – 1 PATIENT GND 2 0.3Hz HIGHPASS 7 + 3V C2 0.47µF RG 6k 6 LT1168 G = 10 1 2 1/2 LT1112 The LT1168’s low supply current, low supply voltage operation and low input bias currents allow it to fit nicely into battery-powered applications. Low overall power dissipation necessitates using higher impedance bridges. The single supply pressure monitor application on the front of this data sheet, shows the LT1168 connected to the differential output of a 3.5k bridge. The picoampere input bias currents keep the error caused by offset current to a negligible level. The LT1112 level shifts the LT1168’s reference pin and the ADC’s analog ground pins above ground. The LT1168’s and LT1112’s combined power dissipation is still less than the bridge’s. This circuit’s total supply current is just 2.2mA. 3V PATIENT/CIRCUIT PROTECTION/ISOLATION C1 0.01µF Low IB Favors High Impedance Bridges, Lowers Dissipation 5 R6 1M 5 – 6 4 8 + 1/2 LT1112 – 4 –3V –3V OUTPUT 1V/mV R7 10k R8 100Ω 3 + AV = 101 POLE AT 1kHz –IN 7 C3 15nF 1168 F08 Figure 8. Nerve Impulse Amplifier 14 15V 3 + 12 7 THERMOMETRICS DC95F103W THERMO METRICS DC95G104Z PRECISION R THERMISTOR T LT1168 6 REF 1 2 – 49.4kΩ VOUT = 1.25 • RT 5 4 OUTPUT VOLTAGE (V) 8 10 8 6 4 YSI #44006 –15V YSI #44011 1168 F09 LT1634-1.25 22k –15V 2 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 1168 F10 Figure 9. Precision Temperature Without Precision Resistors 16 Figure 10. Response of Figure 9 for Various Thermistors LT1168 U TYPICAL APPLICATIO S Single Supply Barometer VS 3 + 2 – – 4 5k 4 R6 1k 5 6 R8 100k 2 1 – 7 R1 825Ω 5k 2 + R2 12Ω 5k + RSET R3 50k 1 5k 6 R4 50k VS 3 6 LT1168 G = 60 8 3 5 TO 4-DIGIT DVM + 4 5 1/2 LT1490 – 7 R7 50k 0.6% ACCURACY AT 25°C 1.7% ACCURACY AT 0°C TO 60°C VS = 8V TO 30V VOLTS 2.800 3.000 3.200 INCHES Hg 28.00 30.00 32.00 1168 TA03 AC Coupled Instrumentation Amplifier 2 –IN 1 – RG +IN 6 LT1168 8 REF 3 5 + 6 OUTPUT R1 1M C1 0.1µF 2 + 1 1 1/2 LT1490 2 LT1634CCZ-1.25 LUCAS NOVA SENOR NPC-1220-015-A-3L 8 – R5 200k 3 LT1677 f –3dB = 1 (2π)(R1)(C1) = 1.59Hz 1168 TA02 17 LT1168 U TYPICAL APPLICATIO S 4-Digit Pressure Sensor 9V R8 392k 3 + 2 1 1 1/4 LT1114 2 LT1634CCZ-1.25 LUCAS NOVA SENOR NPC-1220-015A-3L 4 – 11 – 4 5k R9 1k 2 9V R1 825Ω + RSET 7 6 LT1168 G = 60 R2 12Ω 5k 6 – 1 5k 5k 2 1 8 5 3 3 + 4 10 + 9 0.6% ACCURACY AT ROOM TEMP 1.7% ACCURACY AT 0°C TO 60°C VOLTS 2.800 3.000 3.200 18 INCHES Hg 28.00 30.00 32.00 13 R3 51k + – 14 1/4 LT1114 – 8 1/4 LT1114 5 12 TO 4-DIGIT DVM R4 100k R5 100k R6 50k R7 180k C1 1µF 1168 TA04 LT1168 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.065 (1.651) TYP 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) ) 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) 0.100 (2.54) BSC N8 1098 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 1298 19 LT1168 U TYPICAL APPLICATIO Low Power Programmable Audio HPF/LPF with “Pop-Less” Switching R3 8k R2 4k R1 4k P1 3 14 P2 1 16 8 9 6 11 2 – 1/2 LT1462 VIN 3 + 4 –15V 2 15 12 13 4 5 7 10 +15V 7 6 LT1168 – HPF 5 4 –15V + 7 1/2 LT1462 6 NC +15V –15V 1 + C1 100µF 5 LTC®201 +15V 8 GAIN SET 3 8 1 2 LPF – 1168 TA05 P1 P2 — 0 POLE 100 0 1 1 1 0 < 0.8V 1 > 2.4V 200 400 TOTAL SUPPLY CURRENT < 400µA Hz RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1043 Dual Precision Instrumentation Building Block Switched Capacitor, Rail-to-Rail Input, 120dB CMRR LTC1100 Precision Chopper-Stabilized Instrumentation Amplifier G = 10 or 100, VOS = 10µV, IB = 50pA LT1101 Precision, Micropower, Single Supply Instrumentation Amplifier G = 10 or 100, IS = 105µA LT1102 High Speed, JFET Instrumentation Amplifier G = 10 or 100, Slew Rate = 30V/µs LT1167 Single Resistor Programmable Precision Instrumentation Amplifier Lower Noise than LT1168, eN = 7.5nV/√Hz 20 Linear Technology Corporation 1168f LT/TP 0800 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2000