ETC OP491GRU

a
Micropower Single-Supply
Rail-to-Rail Input/Output Op Amps
OP191/OP291/OP491
FEATURES
Single-Supply Operation: 2.7 V to 12 V
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Supply Current: 300 ␮A/Amp
Wide Bandwidth: 3 MHz
Slew Rate: 0.5 V/␮s
Low Offset Voltage: 700 ␮V
No Phase Reversal
PIN CONFIGURATIONS
8-Lead Narrow-Body SO
1
2
3
OP191
4
APPLICATIONS
Industrial Process Control
Battery-Powered Instrumentation
Power Supply Control and Protection
Telecom
Remote Sensors
Low-Voltage Strain Gage Amplifiers
DAC Output Amplifier
GENERAL DESCRIPTION
The OP191, OP291, and OP491 are single, dual and quad
micropower, single-supply, 3 MHz bandwidth amplifiers featuring rail-to-rail inputs and outputs. All are guaranteed to
operate from a 3 V single supply as well as ± 5 V dual supplies.
8
1
7
2
6
3
5
4
8-Lead Plastic DIP
8
OP291
7
6
5
14-Lead Plastic DIP
OUTA 1
OUTA
1
8
+V
–INA
2
7
OUTB
–INA
2
13 –IND
+INA
3
6
–INB
+INA 3
12 +IND
+INB
4
–V
OP291
4
5
+V
14 OUTD
OP491
+INB 5
14-Lead SO
OUTA 1
14 OUTD
2
13 –IND
+INA 3
12 +IND
–INA
+V
4
OP491
11 –V
+INB 5
10 +INC
6
9 –INC
–INB
OUTB 7
11 –V
10 +INC
6
9
–INC
OUTB 7
8
OUTC
–INB
Fabricated on Analog Devices’ CBCMOS process, the OP191
family has a unique input stage that allows the input voltage to
safely extend 10 V beyond either supply without any phase inversion or latch-up. The output voltage swings to within millivolts
of the supplies and continues to sink or source current all the
way to the supplies.
Applications for these amplifiers include portable telecom
equipment, power supply control and protection, and interface
for transducers with wide output ranges. Sensors requiring a
rail-to-rail input amplifier include Hall effect, piezo electric, and
resistive transducers.
8-Lead Narrow-Body SO
14-Lead TSSOP
1
2
14
13
12
3
4
5
6
7
OP491
11
10
9
8
8 OUTC
The ability to swing rail-to-rail at both the input and output
enables designers to build multistage filters in single-supply
systems and maintain high signal-to-noise ratios.
The OP191/OP291/OP491 are specified over the extended
industrial (–40°C to +125°C) temperature range. The OP191
single and OP291 dual amplifiers are available in 8-lead plastic
SO surface mount packages*. The OP491 quad is available in
14-lead DIPs and narrow 14-lead SO packages. Consult factory
for OP491 TSSOP availability.
*The OP291 dual is also available in 8-lead Plastic Dip.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
OP191/OP291/OP491–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = +3.0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
OP191G
VOS
OP291/OP491G
Input Bias Current
Input Offset Current
VOS
IB
IOS
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
Short Circuit Limit
ISC
Open-Loop Impedance
ZOUT
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
CM
= 0.1 V, VO = 1.4 V, TA = 25ⴗC unless otherwise noted.)
Conditions
Min
Typ
Max
Unit
80
500
1
700
1.25
65
95
11
22
3
µV
mV
µV
mV
nA
nA
nA
nA
V
dB
dB
V/mV
V/mV
µV/°C
pA/°C
pA/°C
–40°C ≤ TA ≤ +125°C
80
–40°C ≤ TA ≤ +125°C
30
–40°C ≤ TA ≤ +125°C
0.1
–40°C ≤ TA ≤ +125°C
VCM = 0 V to 2.9 V
–40°C ≤ TA ≤ +125°C
RL = 10 kΩ , VO = 0.3 V to 2.7 V
–40°C ≤ TA ≤ +125°C
0
70
65
25
90
87
70
50
1.1
100
20
RL = 100 kΩ to GND
–40°C to +125°C
RL = 2 kΩ to GND
–40°C to +125°C
RL = 100 kΩ to V+
–40°C to +125°C
RL = 2 kΩ to V+
–40°C to +125°C
Sink/Source
–40°C to +125°C
f = 1 MHz, AV = 1
2.95
2.90
2.8
2.70
± 8.75
± 6.0
± 13.5
± 10.5
200
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
VS = 2.7 V to 12 V
–40°C ≤ TA ≤ +125°C
VO = 0 V
–40°C ≤ TA ≤ +125°C
80
75
110
110
200
330
dB
dB
µA
µA
DYNAMIC PERFORMANCE
Slew Rate
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
+SR
–SR
BWP
tS
GBP
θO
CS
RL = 10 kΩ
RL = 10 kΩ
1% Distortion
To 0.01%
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz, RL = 10 kΩ
2.99
2.98
2.9
2.8
4.5
40
10
35
75
130
350
480
0.4
0.4
1.2
22
3
45
145
V/µs
V/µs
kHz
µs
MHz
Degrees
dB
2
35
0.8
µV p-p
nV/√Hz
pA/√Hz
Specifications subject to change without notice.
–2–
REV. A
OP191/OP291/OP491
ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V
S
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
OP191
VOS
OP291/OP491
Input Bias Current
Input Offset Current
VOS
IB
IOS
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
Short Circuit Limit
ISC
Open-Loop Impedance
ZOUT
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
CM
= 0.1 V, VO = 1.4 V, TA = 25ⴗC unless otherwise noted.)
Conditions
Typ
Max
Unit
80
500
1.0
700
1.25
65
95
11
22
5
µV
mV
µV
mV
nA
nA
nA
nA
V
dB
dB
V/mV
V/mV
µV/°C
pA/°C
pA/°C
–40°C ≤ TA ≤ +125°C
80
–40°C ≤ TA ≤ +125°C
30
–40°C ≤ TA ≤ +125°C
0.1
–40°C ≤ TA ≤ +125°C
VCM = 0 V to 4.9 V
–40°C ≤ TA ≤ +125°C
RL = 10 kΩ , VO = 0.3 V to 4.7 V
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
0
70
65
25
93
90
70
50
1.1
100
20
RL = 100 kΩ to GND
–40°C to +125°C
RL = 2 kΩ to GND
–40°C to +125°C
RL = 100 kΩ to V+
–40°C to +125°C
RL = 2 kΩ to V+
–40°C to +125°C
Sink/Source
–40°C to +125°C
f = 1 MHz, AV = 1
4.95
4.90
4.8
4.65
± 8.75
± 6.0
± 13.5
± 10.5
200
V
V
V
V
mV
mV
mV
mV
mA
mA
Ω
VS = 2.7 V to 12 V
–40°C ≤ TA ≤ +125°C
VO = 0 V
–40°C ≤ TA ≤ +125°C
80
75
110
110
220
350
dB
dB
µA
µA
DYNAMIC PERFORMANCE
Slew Rate
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
+SR
–SR
BWP
tS
GBP
θO
CS
RL = 10 kΩ
RL = 10 kΩ
1% Distortion
To 0.01%
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz, RL = 10 kΩ
NOTE
+5 V specifications are guaranteed by +3 V and ± 5 V testing.
Specifications subject to change without notice.
REV. A
Min
–3–
4.99
4.98
4.85
4.75
4.5
40
10
35
75
155
400
500
0.4
0.4
1.2
22
3
45
145
V/µs
V/µs
kHz
µs
MHz
Degrees
dB
2
35
0.8
µV p-p
nV/√Hz
pA/√Hz
OP191/OP291/OP491
ELECTRICAL SPECIFICATIONS (@ V = ⴞ5.0 V, –4.9 V ≤ V
O
Parameter
Symbol
INPUT CHARACTERISTICS
Offset Voltage
OP191
VOS
OP291/OP491
IB
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection
CMR
Large Signal Voltage Gain
AVO
Open-Loop Impedance
POWER SUPPLY
Power Supply Rejection Ratio
ZOUT
PSRR
Supply Current/Amplifier
ISY
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
Unit
80
500
1
700
1.25
65
95
11
22
+5
µV
mV
µV
mV
nA
nA
nA
nA
V
dB
dB
0.1
–40°C ≤ TA ≤ +125°C
ISC
Max
30
–40°C ≤ TA ≤ +125°C
VCM = ± 5 V
–40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = ± 4.7 V,
–40°C ≤ TA ≤ +125°C
Typ
80
–40°C ≤ TA ≤ +125°C
VO
Short Circuit Limit
Min
–40°C ≤ TA ≤ +125°C
∆VOS/∆T
∆IB/∆T
∆IOS/∆T
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
OUTPUT CHARACTERISTICS
Output Voltage Swing
≤ +4.9 V, TA = 25ⴗC unless otherwise noted.)
Conditions
VOS
Input Bias Current
CM
–5
75
67
25
100
97
70
50
1.1
100
20
V/mV
µV/°C
pA/°C
pA/°C
RL = 100 kΩ to GND
–40°C to +125°C
RL = 2 kΩ to GND
–40°C ≤ TA ≤ +125°C
Sink/Source
–40°C to +125°C
f = 1 MHz, AV = 1
± 4.93
± 4.90
± 4.80
± 4.65
± 8.75
±6
± 4.99
± 4.98
± 4.95
± 4.75
± 16
± 13
200
V
V
V
V
mA
mA
Ω
VS = ± 5 V
–40°C ≤ TA ≤ +125°C
VO = 0 V
–40 ≤ TA ≤ +125°C
80
70
110
100
260
390
dB
dB
µA
µA
± SR
BWP
tS
GBP
θO
CS
RL =10 kΩ
1% Distortion
To 0.01%
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
420
550
0.5
1.2
22
3
45
145
V/µs
kHz
µs
MHz
Degrees
dB
2
35
0.8
µV p-p
nV/√Hz
pA/√Hz
Specifications subject to change without notice.
5V
100
90
INPUT
VS = ⴞ5V
RL = 2k⍀
AV = +1
VIN = 20V p-p
OUTPUT
10
0%
5V
200␮s
Figure 1. Input and Output with Inputs Overdriven by 5 V
–4–
REV. A
OP191/OP291/OP491
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS 10 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage Temperature Range
P, S, RU Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP191/OP291/OP491G . . . . . . . . . . . . . . . –40°C to +125°C
Junction Temperature Range
P, S, RU Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Package Type
␪JA2
␪JC
Units
8-Lead Plastic DIP (P)
8-Lead SOIC (S)
14-Lead Plastic DIP (P)
14-Lead SOIC (S)
14-Lead TSSOP (RU)
103
158
76
120
180
43
43
33
36
35
°C/W
°C/W
°C/W
°C/W
°C/W
Model
Temperature
Range
Package
Description
Package
Option
OP191GS
OP291GP*
OP291GS
OP491GP
OP491GS
OP491GRU
-40ⴗC to +125ⴗC
-40ⴗC to +125ⴗC
-40ⴗC to +125ⴗC
-40ⴗC to +125ⴗC
-40ⴗC to +125ⴗC
-40ⴗC to +125ⴗC
8-Lead SOIC
8-Lead Plastic DIP
8-Lead SOIC
14-Lead Plastic DIP
14-Lead SOIC
14-Lead TSSOP
SO-8
N-8
SO-8
N-14
SO-14
RU-14
*Not
for new design; obsolete April 2002.
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket
for P-DIP packages; θJA is specified for device soldered in circuit board for TSSOP
and SOIC packages.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP191/OP291/OP491 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–5–
WARNING!
ESD SENSITIVE DEVICE
OP191/OP291/OP491–Typical Performance Characteristics
100
120
VS = +3V
VS = +3V
–40ⴗC < TA < +125ⴗC
BASED ON 600 OP AMPS
INPUT OFFSET VOLTAGE – mV
VS = +3V
160 T = 25ⴗC
A
140 BASED ON
1200 OP AMPS
80
100
UNITS
80
60
60
40
40
20
20
0
0.22
TPC 1. OP291 Input Offset Voltage
Distribution, VS = +3 V
40
INPUT OFFSET CURRENT – nA
INPUT BIAS CURRENT – nA
30
VCM = 2.9V
10
0
–10
VS = +3V
VCM = 0.1V
–20
–30
–40
VCM = 0V
–50
–60
–40
25
85
TEMPERATURE – ⴗC
OPEN-LOOP GAIN – dB
OUTPUT SWING – V
+VO @ RL = 2k⍀
2.85
2.80
VS = +3V
2.75
–40
VCM = 2.9V
–0.6
VCM = 3V
–0.8
–1.0
VCM = 0V
–1.2
–1.4
–1.6
25
85
TEMPERATURE – ⴗC
125
TPC 7. Output Voltage Swing vs.
Temperature, VS = +3 V
125
VS = +3V
18
12
6
0
–6
–12
–18
–24
–30
–36
25
85
TEMPERATURE – ⴗC
125
0 0.30 0.60 0.90 1.2 1.5 1.8 2.1 2.4 2.7 3.0
INPUT COMMON-MODE VOLTAGE – V
TPC 6. Input Bias Current vs. Common-Mode Voltage, VS = +3 V
1200
VS = +3V
TA = 25ⴗC
1000
100
80
0
60
45
40
90
20
135
0
180
–20
225
–40
100
85
25
TEMPERATURE – ⴗC
24
VCM = 0.1V
120
2.90
VCM = 2.9V
–0.12
–0.2
140
2.95
–0.10
TPC 3. Input Offset Voltage vs.
Temperature, VS = +3 V
160
+VO @ RL = 100k⍀
–0.08
–0.14
–40
7
TPC 5. Input Offset Current vs. Temperature, VS = +3 V
3.00
VCM = 3V
36
–0.4
VCM = 0V
–0.06
30
VS = +3V
VCM = 0.1V
–0.04
0
–1.8
–40
125
TPC 4. Input Bias Current vs.
Temperature, VS = +3 V
1
2
3
4
5
6
INPUT OFFSET VOLTAGE – ␮V/ ⴗC
TPC 2. OP291 Input Offset Voltage Drift Distribution, VS = +3 V
VCM = 3V
20
0
–0.02
INPUT BIAS CURRENT – nA
0.14
–0.10
–0.02
0.06
INPUT OFFSET VOLTAGE – mV
1k
10k
100k
1M
FREQUENCY – Hz
270
10M
TPC 8. Open-Loop Gain and Phase
vs. Frequency, VS = +3 V
–6–
PHASE SHIFT – ⴗC
0
–0.18
OPEN-LOOP GAIN –V/mV
UNITS
0
120
180
800
RL = 100k⍀,
VCM = 2.9V
RL = 100k⍀,
VCM = 0.1V
600
400
200
VS = 3V, VO = 0.3V/2.7V
0
–40
25
85
TEMPERATURE – ⴗC
125
TPC 9. Open-Loop Gain vs.
Temperature, VS = +3 V
REV. A
OP191/OP291/OP491
160
50
VS = +3V
TA = 25ⴗC
30
120
20
–20
88
CMRR – dB
0
–10
80
60
40
–30
0
–40
–20
100
1k
10k 100k 1M
FREQUENCY – Hz
–40
100
10M
85
1k
10k
100k
1M
FREQUENCY – Hz
1.6
VS = +3V
PSRR – dB
ⴙPSRR
60
40
–PSRR
20
0
110
109
108
10k
100k
1M
ⴙSR
107
–40
10M
1.0
0.8
0.6
0.4
25
85
125
0
–40
TEMPERATURE – ⴗC
FREQUENCY – Hz
TPC 13. PSRR vs. Frequency,
VS = +3 V
–SR
0.2
–20
1k
VS = +3V
1.2
111
80
1.4
112
100
125
TPC 12. CMRR vs. Temperature,
VS = +3 V
SLEW RATE – V/␮s
120
85
25
TEMPERATURE – ⴗC
113
ⴞPSRR
VS = +3V
TA = 25ⴗC
140
–40
100
84
–40
10M
TPC 11. CMRR vs. Frequency,
VS = +3 V
160
87
86
20
TPC 10. Closed-Loop Gain vs.
Frequency, VS = +3 V
PSRR – dB
VS = +3V
89
100
10
–50
10
90
CMRR
VS = +3V
TA = 25ⴗC
140
CMRR – dB
CLOSED-LOOP GAIN – dB
40
TPC 14. PSRR vs. Temperature,
VS = +3 V
85
25
TEMPERATURE – ⴗC
125
TPC 15. Slew Rate vs. Temperature, VS = +3 V
MKR: 36.2 nV/冪Hz
2.8
VS = +3V
MAXIMUM OUTPUT SWING – V
SUPPLY CURRENT/AMPLIFIER – mA
0.35
0.30
0.25
0.20
0.15
0.10
VIN = +2.8V p-p
VS = +3V
AV = +1
RL = 100k⍀
2.6
2.4
2.2
100
90
2.0
1.8
1.6
10
0%
1.4
1.2
0.05
–40
25
85
125
TEMPERATURE – ⴗC
TPC 16. Supply Current vs.
Temperature, VS = +3 V, +5 V, ± 5 V
REV. A
1.0
0.1 0.5 1.0 10 30 50 70 100 150 200 250 300
FREQUENCY – kHz
TPC 17. Maximum Output Swing vs.
Frequency, VS = +3 V
–7–
MKR: 0 Hz
1000 Hz
BW: 2.5kHz
15.0 Hz
TPC 18. Voltage Noise Density,
VS = +3 V to ± 5 V, AVO = 1000
OP191/OP291/OP491
70
60
50
0.15
120
VS = +5V
TA = 25ⴗC
BASED ON 600
OP AMPS
VS = +5V
VS = +5V
–40°C < TA < +125ⴗC
BASED ON 600 OP AMPS
100
0.10
VCM = 0V
30
0
0
–0.30 –0.10 0.10
0.30
0.50
INPUT OFFSET VOLTAGE – mV
TPC 19. OP291 Input Offset Voltage
Distribution, VS = +5 V
–10
–20
VCM = 0V
–IB
–30
+IB
25
85
TEMPERATURE – ⴗC
VCM = 0V
0.8
0.6
0.4
0.2
0
VCM = 5V
–0.2
–40
125
TPC 22. Input Bias Current vs.
Temperature, VS = +5 V
25
85
TEMPERATURE – ⴗC
80
0
60
45
40
90
20
135
0
180
–20
25
85
125
TEMPERATURE – ⴗC
TPC 25. Output Voltage Swing vs.
Temperature, VS = +5 V
–40
100
–24
1
2
3
4
5
COMMON MODE INPUT VOLTAGE – Volts
VS = +5V
100
4.75
VS = +5V
–18
120
225
1k
10k
100k
1M
FREQUENCY – Hz
270
10M
TPC 26. Open-Loop Gain and Phase
vs. Frequency, VS = +5 V
–8–
OPEN-LOOP GAIN – V/mV
RL = 2k⍀
4.80
–6
–12
TPC 24. Input Bias Current vs.
Common-Mode Voltage, VS = +5 V
PHASE SHIFT – ⴗC
OPEN-LOOP GAIN – dB
4.85
6
0
140
120
4.90
12
0
VS = +5V
TA = 25ⴗC
140
4.95
18
–36
125
160
RL = 100k⍀
VS = +5V
24
–30
TPC 23. Input Offset Current vs.
Temperature, VS = +5 V
5.00
4.70
–40
30
INPUT BIAS CURRENT – nA
0
INPUT OFFSET CURRENT – nA
IB – nA
10
125
36
1.2
1.0
25
85
TEMPERATURE – ⴗC
TPC 21. Input Offset Voltage vs.
Temperature, VS = +5 V
VS = +5V
1.4
–IB
VCM = 5V
VCM = +5V
–0.1
–40
7.0
1.6
+IB
VS = +5V
20
OUTPUT SWING – V
1.0
2.0 3.0
4.0
5.0 6.0
INPUT OFFSET VOLTAGE – ␮V/ⴗC
TPC 20. OP291 Input Offset
Voltage Drift Distribution, VS = +5 V
40
–40
–40
0
–0.05
20
10
30
60
0.05
40
20
0
–0.50
VOS – mV
UNITS
UNITS
80
40
RL = 100k⍀, VCM = 5V
100
80
60
40
RL = 100k⍀, VCM = 0V
RL = 2k⍀, VCM = 5V
20
0
–40
RL = 2k⍀, VCM = 0V
85
25
TEMPERATURE – ⴗC
125
TPC 27. Open-Loop Gain vs.
Temperature, VS = +5 V
REV. A
OP191/OP291/OP491
50
160
VS = +5V
TA = 25ⴗC
30
96
CMRR
VS = +5V
TA = 25ⴗC
140
120
20
95
0
–10
CMRR – dB
10
80
60
40
–20
93
92
91
90
20
89
–30
0
88
–40
–20
87
–50
–40
100
10
100
1k
10k 100k
FREQUENCY – Hz
1M
10M
10k
100k
1M
FREQUENCY – Hz
160
120
0.50
0.45
0.5
0.40
+PSRR
40
–PSRR
SR – V/␮s
+SR
SR – V/␮s
80
–SR
0.3
0.2
0
0
–40
10M
60
–ISC, VS = ⴞ5V
14
+ISC, VS = +3V
–ISC, VS = +3V
8
50
40
30
10k⍀
20
A
6
4
–40
VO
10k⍀
10
25
85
TEMPERATURE – ⴗC
125
0
0
500
1000
1500
2000
FREQUENCY – Hz
2500
TPC 35. Channel Separation,
VS = ± 5 V
–9–
4.5
4.0
3.5
VIN = +4.8V p-p
VS = +5V
AV = +1
RL = 100k⍀
4 PARTS
3.0
2.5
2.0
1.5
1.0
0.5
VIN = 10V p-p @ 1kHz
TPC 34. Short Circuit Current vs.
Temperature, VS = +3 V, +5 V, ± 5 V
REV. A
1k⍀
B
125
5.0
VS = ⴞ5V
70
85
25
TEMPERATURE – ⴗC
TPC 33. OP491 Slew Rate vs.
Temperature, VS = +5 V
MAXIMUM OUTPUT SWING – V
+ISC, VS = ⴞ5V
10
0
–40
125
80
VOLTAGE – ␮V
SHORT CIRCUIT CURRENT – mA
85
25
TPC 32. OP291 Slew Rate vs.
Temperature, VS = +5 V
20
16
0.20
TEMPERATURE – ⴗC
TPC 31. PSRR vs. Frequency,
VS = +5 V
18
0.25
0.05
VS = +5V
10k
100k
1M
FREQUENCY – Hz
–SR
0.10
–20
1k
0.30
0.15
0.1
–40
100
VS = +5V
0.35
0.4
20
125
+SR
100
60
25
85
TEMPERATURE – ⴗC
TPC 30. CMRR vs. Temperature,
VS = +5 V
0.6
ⴞPSRR
VS = +5V
TA = 25ⴗC
140
12
86
–40
10M
TPC 29. CMRR vs. Frequency,
VS = +5 V
TPC 28. Closed-Loop Gain vs.
Frequency, VS = +5 V
PSRR – dB
1k
VS = +5V
94
100
CMRR – dB
CLOSED-LOOP GAIN – dB
40
0
0.1 0.5 1.0 10 30 50 70 100 150 200 250 300
FREQUENCY – kHz
TPC 36. Maximum Output Swing
vs. Frequency, VS = +5 V
OP191/OP291/OP491
0.15
10
7
6
5
4
3
2
1
VCM = –5V
0
0.8
0.6
0.4
0.2
VCM = +5V
0
25
85
TEMPERATURE – ⴗC
TPC 38. Input Offset Voltage vs.
Temperature, VS = ± 5 V
125
12
0
–12
–24
45
20
90
10
135
0
180
–10
225
–20
270
100k
1M
10M
FREQUENCY – Hz
TPC 43. Open-Loop Gain and Phase
vs. Frequency, VS = ± 5 V
OPEN-LOOP GAIN – V/mV
0
30
10k
RL = 100k⍀
4.90
4.85
4.80
4.75
RL = 2k⍀
VS = ⴞ5V
0
–4.75
–4.80
–4.85
RL = 2k⍀
–4.90
RL = 100k⍀
120
100
80
65
40
25
0
–40
85
25
TEMPERATURE – ⴗC
125
TPC 42. Output Voltage Swing vs.
Temperature, VS = ± 5 V
50
160
140
RL = 100k⍀
–5.00
–40
VS = ⴞ5V
180
PHASE SHIFT – ⴗC
OPEN-LOOP GAIN – dB
24
200
40
–30
1k
5.00
TPC 41. Input Bias Current vs. Common-Mode Voltage, VS = ± 5 V
VS = ⴞ5V
TA = 25ⴗC
125
TPC 39. Input Bias Current vs.
Temperature, VS = ± 5 V
–4.95
70
50
25
85
TEMPERATURE – ⴗC
4.95
–36
2 3 4 5
–5 –4 –3 –2 –1 0 1
COMMON-MODE INPUT VOLTAGE – V
TPC 40. Input Offset Current vs.
Temperature, VS = ± 5 V
60
–IB
+IB
–50
–40
125
OUTPUT VOLTAGE SWING – V
1.0
–0.2
–40
25
85
TEMPERATURE – ⴗC
VS = ⴞ5V
VCM = –5V
VCM = –5V
–40
–0.1
–40
36
1.2
0
–10
–30
RL = 2k⍀
25
85
TEMPERATURE – ⴗC
TPC 44. Open-Loop Gain vs.
Temperature, VS = ± 5 V
–10–
VS = ⴞ5V
TA = 25ⴗC
40
CLOSED-LOOP GAIN – dB
INPUT OFFSET CURRENT – nA
1.4
–IB
10
–20
VCM = +5V
–0.05
VS = ⴞ5V
+IB
VCM = +5V
20
0.05
INPUT BIAS CURRENT – nA
1.6
VS = ⴞ5V
30
0.10
0
0.1 0.5 1.0 10 30 50 70 100 150 200 250 300
FREQUENCY – kHz
TPC 37. Maximum Output Swing vs.
Frequency, VS = ± 5 V
40
IB – nA
8
INPUT OFFSET VOLTAGE – mV
MAXIMUM OUTPUT SWING – V
9
50
VS = ⴞ5V
VIN = +9.8V p-p
VS = ⴞ5V
AV = +1
RL = 100k⍀
4 PARTS
30
20
10
0
–10
–20
–30
–40
125
–50
10
100
1k
10k 100k
FREQUENCY – Hz
1M
10M
TPC 45. Closed-Loop Gain vs.
Frequency, VS = ± 5 V
REV. A
OP191/OP291/OP491
102
CMRR
VS = ⴞ5V
TA = 25ⴗC
120
101
80
60
40
120
99
100
98
80
97
96
60
95
0
94
0
–20
93
–20
1k
10k
100k
1M
FREQUENCY – Hz
25
85
TEMPERATURE – ⴗC
–40
100
125
TPC 47. CMRR vs. Temperature,
VS = ± 5 V
TPC 46. CMRR vs. Frequency,
VS = ± 5 V
OP491
800
110
SR – V/␮s
PSRR – dB
100
0.4
+SR
700
–SR
ZOUT – ⍀
0.5
105
0.3
600
500
400
300
0.2
95
AVCL = 100
200
0.1
90
–40
25
85
TEMPERATURE – ⴗC
0
–40
125
TPC 49. OP291/OP491 PSRR vs.
Temperature, VS = ± 5 V
AVCL = 10
100
0
25
85
TEMPERATURE – ⴗC
125
TPC 50. Slew Rate vs. Temperature,
VS = ± 5 V
100
1k
100
100
90
90
INPUT
INPUT
VS = +3V
RL = 200k⍀
10
0%
500mV
2.00␮s
100mV
OUTPUT
TPC 52. Large Signal Transient
Response, VS = +3 V
REV. A
VS = ⴞ5V
RL = 200k⍀
AV = +1V/V
10
0%
1.00V
2.00␮s
100mV
TPC 53. Large Signal Transient
Response, VS = ± 5 V
–11–
AVCL = +1
10k
100k
1M
FREQUENCY – Hz
10M
TPC 51. Output Impedance vs.
Frequency
2.00V
1.00V
OUTPUT
10M
VS = +3V
TA = 25ⴗC
900
0.6
OP291
10k
100k
1M
FREQUENCY – Hz
1k
VS = ⴞ5V
VS = ⴞ5V
1k
TPC 48. PSRR vs. Frequency,
VS = ± 5 V
0.7
115
–PSRR
20
92
–40
10M
+PSRR
40
20
–40
100
ⴞPSRR
VS = ⴞ5V
TA = 25ⴗC
140
100
CMRR – dB
CMRR – dB
100
160
VS = ⴞ5V
PSRR – dB
160
140
OP191/OP291/OP491
exceeds approximately 0.6 V. In this condition, current will flow
between the input pins, limited only by the two 5 kΩ resistors.
Being aware of this characteristic is important in circuits where
the amplifier may be operated open-loop, such as a comparator.
Evaluate each circuit carefully to make sure that the increase in
current does not affect the performance.
FUNCTIONAL DESCRIPTION
The OP191/OP291/OP491 are single-supply, micropower
amplifiers featuring rail-to-rail inputs and outputs. In order to
achieve wide input and output ranges, these amplifiers employ
unique input and output stages. As the simplified schematic
shows (Figure 2), the input stage is actually comprised of two
differential pairs, a PNP pair and an NPN pair. These two stages
do not actually work in parallel. Instead, only one or the other
stage is on for any given input signal level. The PNP stage (transistors Q1 and Q2) is required to ensure that the amplifier remains
in the linear region when the input voltage approaches and
reaches the negative rail. On the other hand, the NPN stage
(transistors Q5 and Q6) is needed for input voltages up to and
including the positive rail.
The output stage of the OP191 family uses a PNP and an NPN
transistor as do most output stages; however, the output transistors, Q32 and Q33, are actually connected with their collectors to the output pin to achieve the rail-to-rail output swing. As
the output voltage approaches either the positive or negative
rail, these transistors begin to saturate. Thus, the final limit on
output voltage is the saturation voltage of these transistors,
which is about 50 mV. The output stage does have inherent gain
arising from the collectors and any external load impedance.
Because of this, the open-loop gain of the amplifier is dependent
on the load resistance.
For the majority of the input common-mode range, the PNP
stage is active, as is evidenced by examining the graph of Input
Bias Current vs. Common-Mode Voltage. Notice that the bias
current switches direction at approximately 1.2 V to 1.3 V below
the positive rail. At voltages below this, the bias current flows
out of the OP291, indicating a PNP input stage. Above this
voltage, however, the bias current enters the device, revealing the
NPN stage. The actual mechanism within the amplifier for
switching between the input stages is comprised of the transistors
Q3, Q4, and Q7. As the input common-mode voltage increases,
the emitters of Q1 and Q2 follow that voltage plus a diode drop.
Eventually the emitters of Q1 and Q2 are high enough to turn
Q3 on. This diverts the 8 µA of tail current away from the PNP
input stage, turning it off. Instead, the current is mirrored through
Q4 and Q7 to activate the NPN input stage.
Input Overvoltage Protection
As with any semiconductor device, whenever the condition
exists for the input to exceed either supply voltage, attention
needs to be paid to the input overvoltage characteristic. When
an overvoltage occurs, the amplifier could be damaged depending on the voltage level and the magnitude of the fault current.
Figure 3 shows the characteristic for the OP191 family. This
graph was generated with the power supplies at ground and a
curve tracer connected to the input. As can be seen, when the
input voltage exceeds either supply by more than 0.6 V, internal
pn-junctions energize, allowing current to flow from the input to
the supplies. As described above, the OP291/OP491 does have
5 kΩ resistors in series with each input, which helps limit the
current. Calculating the slope of the current versus voltage in
the graph confirms the 5 kΩ resistor.
Notice that the input stage includes 5 kΩ series resistors and
differential diodes, a common practice in bipolar amplifiers to
protect the input transistors from large differential voltages.
These diodes will turn on whenever the differential voltage
Q22
8␮A
Q26
–IN
Q32
Q23
Q3
5k⍀
+IN
5k⍀
Q20
Q16
Q5 Q6
Q1 Q2
Q27
Q8
Q10
Q12
Q30
10pF
Q17
Q14
Q21
Q9
Q11
Q13
Q15
Q24
Q18
Q4
Q19
VOUT
Q31
Q25
Q28
Q29
Q33
Q7
Figure 2. Simplified Schematic
–12–
REV. A
OP191/OP291/OP491
IIN
ground and the cathode to the inputs, prevent input signal excursions from exceeding the device’s negative supply (i.e., GND),
preventing a condition which could cause the output voltage to
change phase. JFET-input amplifiers may also exhibit phase
reversal, and, if so, a series input resistor is usually required to
prevent it.
2mA
1mA
–10V
–5V
5V
The OP191 family is free from reasonable input voltage range
restrictions due to its novel input structure. In fact, the input
signal can exceed the supply voltage by a significant amount
without causing damage to the device. As illustrated in Figure 4,
the OP191 family can safely handle a 20 V p-p input signal on
± 5 V supplies without exhibiting any sign of output voltage
phase reversal or other anomalous behavior. Thus no external
clamping diodes are required.
10V
VIN
–1mA
–2mA
Overdrive Recovery
Figure 3. Input Overvoltage Characteristics
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. In the case shown, for an
input of 10 V over the supply, the current is limited to 1.8 mA.
If the voltage is large enough to cause more than 5 mA of current
to flow, then an external series resistor should be added. The size
of this resistor is calculated by dividing the maximum overvoltage
by 5mA and subtracting the internal 5 kΩ resister. For example,
if the input voltage could reach 100 V, the external resistor
should be (100 V/5 mA) –5 k = 15 kΩ. This resistance should
be placed in series with either or both inputs if they are subjected
to the overvoltages. For more information on general overvoltage
characteristics of amplifiers refer to the 1993 System Applications
Guide, available from the Analog Devices Literature Center.
The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to its linear region
from a saturated condition. This recovery time is important in
applications where the amplifier must recover quickly after a
large transient event, such as a comparator. The circuit shown
in Figure 5 was used to evaluate the OP191 family’s overload
recovery time. The OP191 family takes approximately 8 µs to
recover from positive saturation and approximately 6.5 µs to
recover from negative saturation.
Output Voltage Phase Reversal
R1
9k⍀
3
VIN
10V STEP
1/2
OP291
2
R2
10k⍀
1
VS = ⴞ5V
Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs
are driven beyond their useful common-mode range. Typically
for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range. With these
devices, external clamping diodes, with the anode connected to
Figure 5. Overdrive Recovery Time Test Circuit
5␮s
+5V
8
1/2
OP291
2
4
–5V
1
VOUT
5␮s
100
90
VOUT – 2V/DIV
3
100
90
VIN – 2.5V/DIV
VIN
20V p-p
10
10
0%
0%
20mV
TIME – 200␮s/DIV
Figure 4. Output Voltage Phase Reversal Behavior
REV. A
VOUT
R3
10k⍀
–13–
20mV
TIME – 200␮s/DIV
OP191/OP291/OP491
APPLICATIONS
Single +3 V Supply, Instrumentation Amplifier
Single-Supply RTD Amplifier
The OP291’s low supply current and low voltage operation make
it ideal for battery-powered applications such as the instrumentation amplifier shown in Figure 6. The circuit utilizes the classic
two op amp instrumentation amplifier topology, with four resistors
to set the gain. The equation is simply that of a noninverting
amplifier as shown in the figure. The two resistors labeled R1
should be closely matched to each other as well as both resistors
labeled R2 to ensure good common-mode rejection performance.
Resistor networks ensure the closest matching as well as matched
drifts for good temperature stability. Capacitor C1 is included
to limit the bandwidth and, therefore, the noise in sensitive
applications. The value of this capacitor should be adjusted
depending on the desired closed-loop bandwidth of the instrumentation amplifier. The RC combination creates a pole at a
frequency equal to 1/(2 π × R1C1). If AC-CMRR is critical,
than a matched capacitor to C1 should be included across the
second resistor labeled R1.
The circuit in Figure 7 uses three op amps of the OP491 to
develop a bridge configuration for an RTD amplifier that operates from a single +5 V supply. The circuit takes advantage of
the OP491’s wide output swing range to generate a high bridge
excitation voltage of 3.9 V. In fact, because of the rail-to-rail
output swing, this circuit will work with supplies as low as 4.0 V.
Amplifier A1 servos the bridge to create a constant excitation
current in conjunction with the AD589, a 1.235 V precision
reference. The op amp maintains the reference voltage across
the parallel combination of the 6.19 kΩ and 2.55 MΩ resistor,
which generates a 200 µA current source. This current splits
evenly and flows through both halves of the bridge. Thus, 100 µA
flows through the RTD to generate an output voltage based on
its resistance. A 3-wire RTD is used to balance the line resistance in both 100 Ω legs of the bridge to improve accuracy.
26.7k⍀
+3V
5
VIN
6
3
2
R1
1/2
OP291
+5V
26.7k⍀
A3
100⍀
RTD
8
1/2
OP291
GAIN = 274
200⍀
10-TURNS
7
VOUT
A2
100⍀
2.55M⍀
365⍀
6.19k⍀
R2
1/4
OP491
AD589
100pF
365⍀
100k⍀
A1
R1
C1
R1
VOUT = (1 + ––– ) VIN
R2
VOUT
1/4
OP491
4
1
R2
1/4
OP491
100k⍀
0.01pF
ALL RESISTORS 1% OR BETTER
37.4k⍀
+5V
Figure 6. Single +3 V Supply Instrumentation Amplifier
Figure 7. Single-Supply RTD Amplifier
Because the OP291 accepts rail-to-rail inputs, the input commonmode range includes both ground and the positive supply of 3
V. Furthermore, the rail-to-rail output range ensures the widest
signal range possible and maximizes the dynamic range of the
system. Also, with its low supply current of 300 µA/device, this
circuit consumes a quiescent current of only 600 µA, yet still
exhibits a gain bandwidth of 3 MHz.
A question may arise about other instrumentation amplifier
topologies for single-supply applications. For example, a variation
on this topology adds a fifth resistor between the two inverting
inputs of the op amps for gain setting. While that topology works
well in dual-supply applications, it is inherently not appropriate
for single-supply circuits. The same could be said for the traditional three op amp instrumentation amplifier. In both cases, the
circuits simply will not work in single-supply situations unless a
false ground between the supplies is created.
Amplifiers A2 and A3 are configured in the two op amp IA
discussed above. Their resistors are chosen to produce a gain of
274, such that each 1°C increase in temperature results in a
10 mV change in the output voltage, for ease of measurement.
A 0.01 µF capacitor is included in parallel with the 100 kΩ
resistor on amplifier A3 to filter out any unwanted noise from
this high gain circuit. This particular RC combination creates a
pole at 1.6 kHz.
–14–
REV. A
OP191/OP291/OP491
A +2.5 V Reference from a +3 V Supply
In many single-supply applications, the need for a 2.5 V reference
often arises. Many commercially available monolithic 2.5 V
references require at least a minimum operating supply voltage
of 4 V. The problem is exacerbated when the minimum operating
system supply voltage is +3 V. The circuit illustrated in Figure 8
is an example of a +2.5 V that operates from a single +3 V supply.
The circuit takes advantage of the OP291’s rail-to-rail input and
output voltage ranges to amplify an AD589’s 1.235 V output to
+2.5 V. The OP291’s low TCVOS of 1 µV/°C helps maintain an
output voltage temperature coefficient of less than 200 ppm/°C.
The circuit’s overall temperature coefficient is dominated by R2
and R3’s temperature coefficient. Lower tempco resistors are
recommended. The entire circuit draws less than 420 µA from a
+3 V supply at 25°C.
+3V
R1
17.4k⍀
+3V
3
8
1/2
OP291
AD589
2
+2.5VREF
1
4
RESISTORS = 1%, 100ppm/ⴗC
POTENTIOMETER = 10 TURN, 100ppm/ⴗC
R3
100k⍀
R2
100k⍀
R1
5k⍀
The OP291 serves two functions. First, it is required to buffer
the high output impedance of the DAC’s VREF pin, which is on
the order of 10 kΩ. The op amp provides a low impedance output
to drive any following circuitry. Secondly, the op amp amplifies
the output signal to provide a rail-to-rail output swing. In this
particular case, the gain is set to 4.1 to generate a 5.0 V output
when the DAC is at full scale. If other output voltage ranges are
needed, such as 0 to 4.095, the gain can easily be adjusted by
altering the value of the resistors.
A High-Side Current Monitor
In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a
result, monitoring and limiting device power dissipation is of prime
importance in these designs. The circuit illustrated in Figure 10
is an example of a +5 V, single-supply high-side current monitor
that can be incorporated into the design of a voltage regulator
with fold-back current limiting or a high current power supply
with crowbar protection. This design uses an OP291’s rail-to-rail
input voltage range to sense the voltage drop across a 0.1 Ω
current shunt. A p-channel MOSFET used as the feedback
element in the circuit converts the op amp’s differential input
voltage into a current. This current is then applied to R2 to
generate a voltage that is a linear representation of the load
current. The transfer equation for the current monitor is given by:
Figure 8. A +2.5 V Reference that Operates on a Single
+3 V Supply
R

Monitor Output = R2 ×  SENSE  × I L
 R1 
+5 V Only, 12-Bit DAC Swings Rail-to-Rail
The OP191 family is ideal for use with a CMOS DAC to generate
a digitally controlled voltage with a wide output range. Figure 9
shows the DAC8043 used in conjunction with the AD589 to
generate a voltage output from 0 V to 1.23 V. The DAC is actually operated in “voltage switching” mode where the reference is
connected to the current output, IOUT, and the output voltage is
taken from the VREF pin. This topology is inherently noninverting
as opposed to the classic current output mode, which is inverting
and, therefore, unsuitable for single supply.
For the element values shown, the Monitor Output’s transfer
characteristic is 2.5 V/A.
RSENSE
0.1⍀
R1
17.8k⍀
R1
100⍀
1.23V
IOUT
RFB
DAC8043
VREF
3
8
1/2
OP291
2
S
M1
3N163
MONITOR
OUTPUT
VDD
3
+5V
+5V
+5V
8
IL
+5V
1
4
G
D
R2
2.49k⍀
2
1
+5V
AD589
GND CLK SR1 LD
4
7
6
5
DIGITAL
CONTROL
R3
232⍀
1%
R2
32.4k⍀
1%
Figure 10. A High-Side Load Current Monitor
3
8
1/2
OP291
2
1
D
VOUT = –––– (5V)
4096
4
R4
100k⍀
1%
Figure 9. +5 V Only, 12-Bit DAC Swings Rail-to-Rail
REV. A
–15–
OP191/OP291/OP491
390pF
A +3 V, Cold Junction Compensated Thermocouple Amplifier
The OP291’s low supply operation makes it ideal for +3 V batterypowered applications such as the thermocouple amplifier shown
in Figure 11. The K-type thermocouple terminates in an isothermal block where the junctions’ ambient temperature is
continuously monitored using a simple 1N914 diode. The diode
corrects the thermal EMF generated in the junctions by feeding
a small voltage, scaled by the 1.5 MΩ and 475 Ω resistors, to
the op amp.
37.4k⍀
RXA
14
A2
1/4
OP491 8
ALUMEL
9
37.4k⍀, 1%
0.1␮F
TXA
20k⍀, 1%
K-TYPE
THERMOCOUPLE
40.7␮V/ⴗC
0.033␮F
20k⍀ 1%
1:1
24.9k⍀
1%
4.99k⍀
1%
COLD
JUNCTIONS
500⍀
10-TURN
11.2mV
ZERO
ADJUST
5
+3V OR +5V
8
4
VOUT
OP291
3
5.1V TO 6.2V
ZENER 5
A3
1/4
7
OP491
SCALE
ADJUST
1.33M⍀ 20k⍀
24.3k⍀
1%
2
475⍀
1%
T1
750pF
3.0V
AL
CR
CHROMEL
475⍀, 1%
20k⍀ 1%
10k⍀
7.15k⍀
1%
1.5M⍀
1%
20k⍀, 1%
10
6
1N914
12
3.3k⍀
1.235V
ISOTHERMAL
BLOCK
13
1/4
OP491
0.0047␮F
To calibrate this circuit, immerse the thermocouple measuring
junction in a 0°C ice bath, and adjust the 500 Ω pot to zero volts
out. Next, immerse the thermocouple in a 250°C temperature
bath or oven and adjust the Scale Adjust pot for an output
voltage of 2.50 V. Within this temperature range, the K-type
thermocouple is accurate to within ± 3°C without linearization.
AD589
20k⍀, 1%
A1
0.1␮F
4
1
1
A4
0V = 0ⴗC
3V = 300ⴗC
2
100k⍀
1/4
OP491
11
3
100k⍀
10␮F
0.1␮F
2.1k⍀
1%
Figure 11. A 3 V, Cold Junction Compensated Thermocouple Amplifier
Figure 12. Single-Supply Direct Access Arrangement for
Modems
Single-Supply, Direct Access Arrangement for Modems
The OP491’s bandwidth of 3 MHz and rail-to-rail output swings
ensures that it can provide the largest possible drive to the transformer at the frequency of transmission.
An important building block in modems is the telephone line
interface. In the circuit shown in Figure 12, a direct access
arrangement is utilized for transmitting and receiving data from
the telephone line. Amplifier A1 is the receiving amplifier, and
amplifiers A2 and A3 are the transmitters. The forth amplifier,
A4, generates a pseudo ground half-way between the supply
voltage and ground. This pseudo ground is needed for the ac
coupled bipolar input signals.
A +3 V, 50 Hz/60 Hz Active Notch Filter with False Ground
The transmit signal, TXA, is inverted by A2 and then reinverted
by A3 to provide a differential drive to the transformer, where
each amplifier supplies half the drive signal. This is needed
because of the smaller swings associated with a single supply as
opposed to a dual supply. Amplifier A1 provides some gain for
the received signal, and it also removes the transmit signal present
at the transformer from the receive signal. To do this, the drive
signal from A2 is also fed to the noninverting input of A1 to
cancel the transmit signal from the transformer.
To process ac signals in a single-supply system, it is often best
to use a false-ground biasing scheme. A circuit that uses this
approach is illustrated in Figure 13. In this circuit, a false-ground
circuit biases an active notch filter used to reject 50 Hz/60 Hz
power line interference in portable patient monitoring equipment.
Notch filters are quite commonly used to reject power line
frequency interference which often obscures low frequency
physiological signals, such as heart rates, blood pressure readings,
EEGs, and EKGs. This notch filter effectively squelches 60 Hz
pickup at a filter Q of 0.75. Substituting 3.16 kΩ resistors for
the 2.67 kΩ resistors in the twin-T section (R1 through R5)
configures the active filter to reject 50 Hz interference.
–16–
REV. A
OP191/OP291/OP491
Single-Supply Half-Wave and Full-Wave Rectifiers
R2
2.67k⍀
C1
1␮F
11
2
1/4
OP491
VIN
3
An OP191 family configured as a voltage follower operating on
a single supply can be used as a simple half-wave rectifier in
low-frequency (<2 kHz) applications. A full-wave rectifier can
be configured with a pair of OP291s as illustrated in Figure 14.
The circuit works in the following way: When the input signal is
above 0 V, the output of amplifier A1 follows the input signal.
Since the noninverting input of amplifier A2 is connected to
A1’s output, op amp loop control forces the A2’s inverting input
to the same potential. The result is that both terminals of R1 are
equipotential; i.e., no current flows. Since there is no current
flow in R1, the same condition exists upon R2; thus, the output
of the circuit tracks the input signal. When the input signal is
below 0 V, the output voltage of A1 is forced to 0 V. This condition now forces A2 to operate as an inverting voltage follower
because the noninverting terminal of A2 is at 0 V as well. The
output voltage at VOUTA is then a full-wave rectified version of
the input signal. If needed, a buffered, half-wave rectified version
of the input signal is available at VOUTB.
R1
2.67k⍀
+3V
1
5
R3
2.67k⍀
A1
4
C2
1␮F
R4
2.67k⍀
1/4
OP491
6
R5
1.33k⍀
(2.67k⍀÷2)
C3
2␮F
(1␮Fⴛ2)
R6
100k⍀
R8
1k⍀
VOUT
7
A2
R7
1k⍀
R11
100k⍀
C5
+3V
R9
1M⍀
C4
1␮F
0.01␮F
R12
499⍀
9
1/4
OP491
10
A3
8
C6
1.5V
1␮F
R10
1M⍀
R1
100k⍀
Figure 13. A +3 V Single-Supply, 50 Hz/60 Hz Active Notch
Filter with False Ground
Amplifier A3 is the heart of the false-ground bias circuit. It
simply buffers the voltage developed by R9 and R10 and is the
reference for the active notch filter. Since the OP491 exhibits a
rail-to-rail input common-mode range, R9 and R10 are chosen
to split the +3 V supply symmetrically. An in-the-loop compensation scheme is used around the OP491 that allows the op amp
to drive C6, a 1 µF capacitor, without oscillation. C6 maintains
a low impedance ac ground over the operating frequency range
of the filter.
The filter section uses a pair of OP491s in a twin-T configuration whose frequency selectivity is very sensitive to the relative
matching of the capacitors and resistors in the twin-T section.
Mylar is the material of choice for the capacitors, and the relative matching of the capacitors and resistors determines the
filter’s passband symmetry. Using 1% resistors and 5% capacitors produces satisfactory results.
+5V
VIN
2V p-p
<2kHz
3
R2
100k⍀
6
1/2
OP291
8
1/2
OP291
4
2
1
5
A2
VOUT A
7
FULL-WAVE
RECTIFIED
OUTPUT
A1
VOUT B
HALF-WAVE
RECTIFIED
OUTPUT
VIN
(1V/DIV)
500mV
1V
100
90
VOUT B
(0.5V/DIV)
10
VOUT A
(0.5V/DIV)
0%
500mV
200␮s
TIME – 200␮s/DIV
Figure 14. Single-Supply Half-Wave and Full-Wave
Rectifiers Using an OP291
REV. A
–17–
OP191/OP291/OP491
* OP491 SPICE Macro-model
Rev. A, 5/94
*
ARG/ADI
*
* Copyright 1994 by Analog Devices, Inc.
*
* Refer to “README.DOC” file for License Statement. Use of
* this model indicates your acceptance of the terms and pro* visions in the License Statement.
*
* Node assignments
*
noninverting input
*
inverting input
*
positive supply
*
negative supply
*
output
*
.SUBCKT OP491 1 2
99
50 45
*
* INPUT STAGE
*
I1
99
7
8.06E-6
Q1 6
4
7 QP
Q2 5
3
7 QP
D1 3
99
DX
D2 4
99
DX
D3 3
4
DX
D4 4
3
DX
R1 3
8
5E3
R2 4
2
5E3
R3 5
50
6.4654E3
R4 6
50
6.4654E3
EOS 8
1
POLY(1) (16,39) –0.08E-3 1
IOS 3
4
50E-12
GB1 3
98
(21,98) 50E-9
GB2 4
98
(21,98) 50E-9
CIN 1
2
1E-12
*
* 1ST GAIN STAGE
*
EREF 98
0
(39,0)
1
G1 98
9
(6,5)
31.667E-6
R7 9
98
1E6
EC1 99
10
POLY(1) (99,39) –0.52 1
EC2 11
50
POLY(1) (39,50) –0.52 1
D5 9
10
DX
D6 11
9
DX
*
* 2ND GAIN STAGE AND DOMINANT POLE AT 1.25 Hz
*
G2 98
12
(9,39)
8E-6
R8 12
98
276.311E6
C2 12
98
16E-12
D7 12
13
DX
D8 14
12
DX
V1 99
13
0.58
V2 14
50
0.58
*
* COMMON-MODE STAGE
*
ECM 15
98
POLY(2) (1,39) (2,39) 0 0.5 0.5
R9 15
16
1E6
R10 16
98
10
*
* POLE AT 2.5 MHz
*
G3 98
18
(12,39) 1E-6
R11 18
98
1E6
C4 18
98
63.662E-15
*
* BIAS CURRENT-VS-COMMON-MODE VOLTAGE
*
EP 97
0
(99,0) 1
VB 99
17
1.3
RB 17
50
1E9
E3
19
0
(15,17) 16
D13 19
20
DX
R12 20
0
1E6
G4 98
21
(20,0) 1E-3
R13 21
98
5E3
D14 21
22
DY
E4
97
22
(POLY(1) (99,98) -0.765 1
*
* POLE AT 100 MHz
*
G6 98
40
(18,39) 1E-6
R20 40
98
1E6
C10 40
98
1.592E-15
*
* OUTPUT STAGE
*
RS1 99
39
109.375E3
RS2 39
50
109.375E3
RO1 99
45
41.667
RO2 45
50
41.667
G7 45
99
(99,40) 24E-3
G8 50
45
(40,50) 24E-3
G9 98
60
(45,40) 24E-3
D9 60
61
DX
D10 62
60
DX
V7 61
98
DC 0
V8 98
62
DC 0
FSY 99
50
POLY(2) V7 V8 0.207E-3 1 1
D11 41
45
DZ
D12 45
42
DZ
V5 40
41
0.131
V6 42
40
0.131
.MODEL DX D()
.MODEL DY D(IS=1E-9)
.MODEL DZ D(IS=1E-6)
.MODEL QP PNP(BF=66.667)
.ENDS
–18–
REV. A
OP191/OP291/OP491
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8-Lead Narrow-Body SO
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.430 (10.92)
0.348 (8.84)
8
5
0.280 (7.11)
0.240 (6.10)
1
4
PIN 1
0.210 (5.33)
MAX
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
0.022 (0.558) 0.100 0.070 (1.77)
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
SEATING
PLANE
8
5
1
4
PIN 1
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
8
1
7
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
14
8
1
7
PIN 1
0.130
(3.30)
MIN
0.100 0.070 (1.77)
(2.54) 0.045 (1.15)
BSC
0.1574 (4.00)
0.1497 (3.80)
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.0500
(1.27)
BSC
14-Lead TSSOP
(RU-14)
0.201 (5.10)
0.193 (4.90)
14
8
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
7
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. A
8°
0°
0.0500 (1.27)
0.0160 (0.41)
0.3444 (8.75)
0.3367 (8.55)
14
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.0098 (0.25)
0.0075 (0.19)
14-Lead Narrow-Body SO
(R-14)
0.795 (20.19)
0.725 (18.42)
PIN 1
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35)
BSC
14-Lead Plastic DIP
(N-14)
0.210 (5.33)
MAX
0.2440 (6.20)
0.2284 (5.80)
0.0433
(1.10)
MAX
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–19–
8°
0°
0.028 (0.70)
0.020 (0.50)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
0.0196 (0.50)
x 45°
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
OP191/OP291/OP491
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Edits to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ODERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PRINTED IN U.S.A.
Edits to DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
C00294-0-2/02(A)
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
–20–
REV. A