AD AMP04EP

Precision Single Supply
Instrumentation Amplifier
AMP04*
a
FEATURES
Single Supply Operation
Low Supply Current: 700 mA max
Wide Gain Range: 1 to 1000
Low Offset Voltage: 150 mV max
Zero-In/Zero-Out
Single-Resistor Gain Set
8-Pin Mini-DIP and SO packages
FUNCTIONAL BLOCK DIAGRAM
100k
R GAIN
1
IN(–) 2
The AMP04 is a single-supply instrumentation amplifier
designed to work over a +5 volt to ± 15 volt supply range. It
offers an excellent combination of accuracy, low power consumption, wide input voltage range, and excellent gain
performance.
Gain is set by a single external resistor and can be from 1 to
1000. Input common-mode voltage range allows the AMP04 to
handle signals with full accuracy from ground to within 1 volt of
the positive supply. And the output can swing to within 1 volt of
the positive supply. Gain bandwidth is over 700 kHz. In addition to being easy to use, the AMP04 draws only 700 µA of supply current.
6
IN(+) 3
11k
APPLICATIONS
Strain Gages
Thermocouples
RTDs
Battery Powered Equipment
Medical Instrumentation
Data Acquisition Systems
PC Based Instruments
Portable Instrumentation
GENERAL DESCRIPTION
VOUT
8
INPUT BUFFERS
11k
100k
5 REF
The AMP04 is specified over the extended industrial (–40°C to
+85°C) temperature range. AMP04s are available in plastic and
ceramic DIP plus SO-8 surface mount packages.
Contact your local sales office for MIL-STD-883 data sheet
and availability.
PIN CONNECTIONS
8-Lead Epoxy DIP
(P Suffix)
RGAIN 1
–IN 2
8 RGAIN
8-Lead Narrow-Body SO
(S Suffix)
RGAIN
RGAIN
7 V+
–IN
+IN 3
6 VOUT
+IN
VOUT
V– 4
5 REF
V–
REF
AMP-04
AMP-04
V+
For high resolution data acquisition systems, laser trimming of
low drift thin-film resistors limits the input offset voltage to
under 150 µV, and allows the AMP04 to offer gain nonlinearity
of 0.005% and a gain tempco of 30 ppm/°C.
A proprietary input structure limits input offset currents to less
than 5 nA with drift of only 8 pA/°C, allowing direct connection
of the AMP04 to high impedance transducers and other signal
sources.
*Protected by U.S. Patent No. 5,075,633.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AMP04–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
OFFSET VOLTAGE
Input Offset Voltage
VIOS
Input Offset Voltage Drift
Output Offset Voltage
TCVIOS
VOOS
Output Offset Voltage Drift
TCVoos
INPUT CURRENT
Input Bias Current
IB
Input Bias Current Drift
Input Offset Current
TCIB
IOS
Input Offset Current Drift
TCIOS
INPUT
Common-Mode Input Resistance
Differential Input Resistance
Input Voltage Range
VIN
Common-Mode Rejection
CMR
Common-Mode Rejection
Power Supply Rejection
CMR
PSRR
GAIN (G = 100 K/RGAIN)
Gain Equation Accuracy
Conditions
Min
0.5
–40°C ≤ TA ≤ +85°C
22
–40°C ≤ TA ≤ +85°C
65
1
–40°C ≤ TA ≤ +85°C
0 V ≤ VCM ≤ 3.0 V
G=1
G = 10
G = 100
G = 1000
0 V ≤ VCM ≤ 2.5 V
–40°C ≤ TA ≤ +85°C
G=1
G = 10
G = 100
G = 1000
4.0 V ≤ VS ≤ 12 V
–40°C ≤ TA ≤ +85°C
G=1
G = 10
G = 100
G = 1000
G
Gain Temperature Coefficient
∆G/∆T
OUTPUT
Output Voltage Swing High
VOH
Output Voltage Swing Low
VOL
AMP04E
Typ Max
30
–40°C ≤ TA ≤ +85°C
60
80
90
90
Units
150
300
3
1.5
3
30
300
600
6
3
6
50
µV
µV
µV/°C
mV
mV
µV/°C
30
50
40
60
nA
nA
pA/°C
nA
nA
pA/°C
65
5
10
10
15
8
4
4
4
4
3.0
80
100
105
105
0
3.0
GΩ
GΩ
V
dB
dB
dB
dB
55
75
85
85
50
70
75
75
dB
dB
dB
dB
95
105
105
105
85
95
95
95
dB
dB
dB
dB
0.2
0.5
0.8
0.4
1
–2–
AMP04F
Typ
Max
55
75
80
80
G = 1, RL = 5 kΩ
G = 10, RL = 5 kΩ
G = 100, RL = 5 kΩ
RL = 2 kΩ
RL = 2 kΩ
–40°C ≤ TA ≤ +85°C
RL = 2 kΩ
–40°C ≤ TA ≤ +85°C
Sink
Source
Min
8
0
G = 1 to 100
G = 1 to 100
–40°C ≤ TA ≤ +85°C
G = 1000
Gain Range
Nonlinearity
Output Current Limit
(VS = +5 V, VCM = +2.5 V, TA = +258C unless otherwise noted)
1000
1.0
%
%
V/V
%
%
%
ppm/°C
1
1000
50
4.2
3.8
4.0
V
3.8
V
2.0
30
15
%
0.75
0.005
0.015
0.025
30
4.0
0.75
2.5
30
15
mV
mA
mA
REV. A
AMP04
Conditions
NOISE
Noise Voltage Density, RTI
eN
f = 1 kHz, G = 1
f = 1 kHz, G = 10
f = 100 Hz, G = 100
f = 100 Hz, G = 1000
f = 100 Hz, G = 100
0.1 to 10 Hz, G = 1
0.1 to 10 Hz, G = 10
0.1 to 10 Hz, G = 100
270
45
30
25
4
7
1.5
0.7
270
45
30
25
4
7
1.5
0.7
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
µV p-p
µV p-p
µV p-p
G = 1, –3 dB
300
300
kHz
iN
eN p-p
DYNAMIC RESPONSE
Small Signal Bandwidth
BW
POWER SUPPLY
Supply Current
ISY
550
–40°C ≤ TA ≤ +85°C
Min
AMP04F
Typ
Symbol
Noise Current Density, RTI
Input Noise Voltage
Min
AMP04E
Typ Max
Parameter
700
850
Max
700
850
Units
µA
µA
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (V = 65 V, V
S
Parameter
Symbol
OFFSET VOLTAGE
Input Offset Voltage
VIOS
Input Offset Voltage Drift
Output Offset Voltage
TCVIOS
VOOS
Output Offset Voltage Drift
TCVoos
INPUT CURRENT
Input Bias Current
IB
Input Bias Current Drift
Input Offset Current
TCIB
IOS
Input Offset Current Drift
TCIOS
INPUT
Common-Mode Input Resistance
Differential Input Resistance
Input Voltage Range
Common-Mode Rejection
Common-Mode Rejection
Power Supply Rejection
REV. A
VIN
CMR
CMR
PSRR
CM
= 0 V, TA = +258C unless otherwise noted)
Conditions
Min
80
–40°C ≤ TA ≤ +85°C
1
–40°C ≤ TA ≤ +85°C
17
–40°C ≤ TA ≤ +85°C
65
2
–40°C ≤ TA ≤ +85°C
–12 V ≤ VCM ≤ +12 V
G=1
G = 10
G = 100
G = 1000
–11 V ≤ VCM ≤ +11 V
–40°C ≤ TA ≤ +85°C
G=1
G = 10
G = 100
G = 1000
± 2.5 V ≤ VS ≤ ± 18 V
–40°C ≤ TA ≤ +85°C
G=1
G = 10
G = 100
G = 1000
–3–
AMP04E
Typ Max
AMP04F
Typ
Max
600
900
6
6
9
50
µV
µV
µV/°C
mV
mV
µV/°C
30
50
40
60
nA
nA
pA/°C
nA
nA
pA/°C
65
5
15
10
20
28
4
4
4
4
+12
80
100
105
105
Units
400
600
3
3
6
30
28
–12
60
80
90
90
Min
–12
+12
GΩ
GΩ
V
55
75
80
80
dB
dB
dB
dB
55
75
85
85
50
70
75
75
dB
dB
dB
dB
75
90
95
95
70
80
85
85
dB
dB
dB
dB
AMP04
Parameter
Symbol
GAIN (G = 100 K/RGAIN)
Gain Equation Accuracy
G
Gain Temperature Coefficient
∆G/∆T
OUTPUT
Output Voltage Swing High
VOH
Output Voltage Swing Low
VOL
Output Current Limit
Noise Current Density, RTI
Input Noise Voltage
Min
AMP04E
Typ Max
G = 1 to 100
G = 1000
G = 1 to 100
–40°C ≤ TA ≤ +85°C
Gain Range
Nonlinearity
NOISE
Noise Voltage Density, RTI
Conditions
eN
iN
eN p-p
DYNAMIC RESPONSE
Small Signal Bandwidth
BW
POWER SUPPLY
Supply Current
ISY
0.2
0.4
G = 1, RL = 5 kΩ
G = 10, RL = 5 kΩ
G = 100, RL = 5 kΩ
RL = 2 kΩ
RL = 2 kΩ
–40°C ≤ TA ≤ +85°C
RL = 2 kΩ
–40°C ≤ TA ≤ +85°C
Sink
Source
AMP04F
Typ
Max
0.5
1
0.005
0.015
0.025
30
+13
Units
0.75
%
%
1.0
1000
%
V/V
%
%
%
ppm/°C
0.75
0.8
1000
1
Min
0.005
0.015
0.025
50
+13.4
+12.5
+13
V
+12.5
V
–14.5
–14.5 V
mA
mA
30
15
30
15
f = 1 kHz, G = 1
f = 1 kHz, G = 10
f = 100 Hz, G = 100
f = 100 Hz, G = 1000
f = 100 Hz, G = 100
0.1 to 10 Hz, G = 1
0.1 to 10 Hz, G = 10
0.1 to 10 Hz, G = 100
270
45
30
25
4
5
1
0.5
270
45
30
25
4
5
1
0.5
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
µV p-p
µV p-p
µV p-p
G = 1, –3 dB
700
700
kHz
–40°C ≤ TA ≤ +85°C
750
900
1100
900
1100
µA
µA
Specifications subject to change without notice.
WAFER TEST LIMITS
(VS = +5 V, VCM = +2.5 V, TA = +258C unless otherwise noted)
Parameter
Symbol
OFFSET VOLTAGE
Input Offset Voltage
Output Offset Voltage
Limit
Units
VIOS
VOOS
300
3
µV max
mV max
INPUT CURRENT
Input Bias Current
Input Offset Current
IB
IOS
40
10
nA max
nA max
INPUT
Common-Mode Rejection
CMR
55
75
80
80
dB min
dB min
dB min
dB min
55
75
80
dB min
dB min
dB min
Common-Mode Rejection
CMR
Conditions
0 V ≤ VCM ≤ 3.0 V
G=1
G = 10
G = 100
G = 1000
VS = ± 15 V, –12 V ≤ VCM ≤ +12 V
G=1
G = 10
G = 100
–4–
REV. A
AMP04
Parameter
Symbol
Power Supply Rejection
PSRR
GAIN (G = 100 K/RGAIN)
Gain Equation Accuracy
Conditions
Limit
Units
G = 1000
4.0 V ≤ VS ≤ 12 V
G=1
G = 10
G = 100
G = 1000
80
dB min
85
95
95
95
dB min
dB min
dB min
dB min
G = 1 to 100
0.75
% max
OUTPUT
Output Voltage Swing High
Output Voltage Swing Low
VOH
VOL
RL = 2 kΩ
RL = 2 kΩ
4.0
2.5
V min
mV max
POWER SUPPLY
Supply Current
ISY
VS = ± 15
900
700
µA max
µA max
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS 1
DICE CHARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 18 V
Common-Mode Input Voltage2 . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AMP04A . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
AMP04E, F . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
Package Type
θJA3
θJC
Units
8-Pin Cerdip (Z)
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
148
103
158
16
43
43
°C/W
°C/W
°C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
3
θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for cerdip, P-DIP, and LCC packages; θJA is specified for device
soldered in circuit board for SOIC package.
AMP04 Die Size 0.075 × 0.99 inch, 7,425 sq. mils.
Substrate (Die Backside) Is Connected to V+.
Transistor Count, 81.
ORDERING GUIDE
REV. A
Model
Temperature
Range
VOS @ +5 V
TA = +258C
Package
Description
Package
Option
AMP04EP
AMP04ES
AMP04FP
AMP04FS
AMP04FS-REEL
AMP04FS-REEL7
AMP04GBC
XIND
XIND
XIND
XIND
XIND
XIND
+25°C
150 µV
150 µV
300 µV
300 µV
150 µV
150 µV
300 µV
Plastic DIP
SOIC
Plastic DIP
SOIC
SOIC
SOIC
N-8
SO-8
N-8
SO-8
SO-8
SO-8
–5–
AMP04
Input Common-Mode Voltage Below Ground
APPLICATIONS
Common-Mode Rejection
The purpose of the instrumentation amplifier is to amplify the
difference between the two input signals while ignoring offset
and noise voltages common to both inputs. One way of judging
the device’s ability to reject this offset is the common-mode
gain, which is the ratio between a change in the common-mode
voltage and the resulting output voltage change. Instrumentation amplifiers are often judged by the common-mode rejection
ratio, which is equal to 20 × log10 of the ratio of the user-selected
differential signal gain to the common-mode gain, commonly
called the CMRR. The AMP04 offers excellent CMRR, guaranteed to be greater than 90 dB at gains of 100 or greater. Input
offsets attain very low temperature drift by proprietary lasertrimmed thin-film resistors and high gain amplifiers.
Input Common-Mode Range Includes Ground
The AMP04 employs a patented topology (Figure 1) that
uniquely allows the common-mode input voltage to truly extend
to zero volts where other instrumentation amplifiers fail. To illustrate, take for example the single supply, gain of 100 instrumentation amplifier as in Figure 2. As the inputs approach zero
volts, in order for the output to go positive, amplifier A’s output
(VOA) must be allowed to go below ground, to –0.094 volts.
Clearly this is not possible in a single supply environment. Consequently this instrumentation amplifier configuration’s input
common-mode voltage cannot go below about 0.4 volts. In
comparison, the AMP04 has no such restriction. Its inputs will
function with a zero-volt common-mode voltage.
Although not tested and guaranteed, the AMP04 inputs are biased in a way that they can amplify signals linearly with commonmode voltage as low as –0.25 volts below ground. This holds
true over the industrial temperature range from –40°C to +85°C.
Extended Positive Common-Mode Range
On the high side, other instrumentation amplifier configurations, such as the three op amp instrumentation amplifier, can
have severe positive common-mode range limitations. Figure 3
shows an example of a gain of 1001 amplifier, with an input
common-mode voltage of 10 volts. For this circuit to function,
VOB must swing to 15.01 volts in order for the output to go to
10.01 volts. Clearly no op amp can handle this swing range
(given a +15 V supply) as the output will saturate long before it
reaches the supply rails. Again the AMP04’s topology does not
have this limitation. Figure 4 illustrates the AMP04 operating at
the same common-mode conditions as in Figure 3. None of the
internal nodes has a signal high enough to cause amplifier saturation. As a result, the AMP04 can accommodate much wider
common-mode range than most instrumentation amplifiers.
+10.00V
A
R
100k
200Ω
R
+5V
10.01
VOA
50µA
VOB
100k
R
+15.01V
R
+10.01V
100k
B
R GAIN
IN(–)
1
2
VOUT
8
INPUT BUFFERS
IN(+)
Figure 3. Gain = 1001, Three Op Amp Instrumentation
Amplifier
6
3
11k
100k
0.1µA
11k
+10.00V
–
100k
5
100Ω
+15V
+10.01V
VOUT
+10V
100µA
+10.01V
+
+15V
REF
–15V
11k
100.1µA
Figure 1. Functional Block Diagram
–15V
0.01V
+
VOB
+11.111V
11k
VOUT
100k
B
VIN
0V
–
A
100k
VOA
Figure 4. Gain = 1000, AMP04
20k
20k
0V
4.7µA
4.7µA
–.094V
5.2µA
100k
0.01V
2127Ω
Figure 2. Gain = 100 Instrumentation Amplifier
–6–
REV. A
AMP04
signal routing practice to minimize stray coupling and ground
loops is recommended. Leakage currents can be minimized by
using high quality socket and circuit board materials, and by
carefully cleaning and coating complete board assemblies.
Programming the Gain
The gain of the AMP04 is programmed by the user by selecting
a single external resistor—RGAIN:
Gain = 100 kΩ/RGAIN
As mentioned above, the high speed transition noise found in
logic circuitry is the sworn enemy of the analog circuit designer.
Great care must be taken to maintain separation between them
to minimize coupling. A major path for these error voltages will
be found in the power supply lines. Low impedance, load related variations and noise levels that are completely acceptable
in the high thresholds of the digital domain make the digital
supply unusable in nearly all high performance analog applications. The user is encouraged to maintain separate power and
ground between the analog and digital systems wherever possible, joining only at the supply itself if necessary, and to observe careful grounding layout and bypass capacitor scheduling
in sensitive areas.
The output voltage is then defined as the differential input voltage times the gain.
VOUT = (VIN+ – VIN–) × Gain
In single supply systems, offsetting the ground is often desired
for several reasons. Ground may be offset from zero to provide
a quieter signal reference point, or to offset “zero” to allow a
unipolar signal range to represent both positive and negative
values.
In noisy environments such as those having digital switching,
switching power supplies or externally generated noise, ground
may not be the ideal place to reference a signal in a high accuracy system.
Input Shield Drivers
Often, real world signals such as temperature or pressure may
generate voltages that are represented by changes in polarity. In
a single supply system the signal input cannot be allowed to go
below ground, and therefore the signal must be offset to accommodate this change in polarity. On the AMP04, a reference input pin is provided to allow offsetting of the input range.
High impedance sources and long cable runs from remote transducers in noisy industrial environments commonly experience
significant amounts of noise coupled to the inputs. Both stray
capacitance errors and noise coupling from external sources can
be minimized by running the input signal through shielded
cable. The cable shield is often grounded at the analog input
common, however improved dynamic noise rejection and a reduction in effective cable capacitance is achieved by driving the
shield with a buffer amplifier at a potential equal to the voltage
seen at the input. Driven shields are easily realized with the
AMP04. Examination of the simplified schematic shows that the
potentials at the gain set resistor pins of the AMP04 follow the
inputs precisely. As shown in Figure 5, shield drivers are easily
realized by buffering the potential at these pins by a dual, single
supply op amp such as the OP213. Alternatively, applications
with single-ended sources or that use twisted-pair cable could
drive a single shield. To minimize error contributions due to
this additional circuitry, all components and wiring should remain in proximity to the AMP04 and careful grounding and bypassing techniques should be observed.
The gain equation is more accurately represented by including
this reference input.
VOUT = (VIN+ – VIN–) × Gain + VREF
Grounding
The most common problems encountered in high performance
analog instrumentation and data acquisition system designs are
found in the management of offset errors and ground noise.
Primarily, the designer must consider temperature differentials
and thermocouple effects due to dissimilar metals, IR voltage
drops, and the effects of stray capacitance. The problem is
greatly compounded when high speed digital circuitry, such as
that accompanying data conversion components, is brought
into the proximity of the analog section. Considerable noise and
error contributions such as fast-moving logic signals that easily
propagate into sensitive analog lines, and the unavoidable noise
common to digital supply lines must all be dealt with if the accuracy of the carefully designed analog section is to be preserved.
1/2 OP-213
Besides the temperature drift errors encountered in the amplifier, thermal errors due to the supporting discrete components
should be evaluated. The use of high quality, low-TC components where appropriate is encouraged. What is more important,
large thermal gradients can create not only unexpected changes
in component values, but also generate significant thermoelectric voltages due to the interface between dissimilar metals such
as lead solder, copper wire, gold socket contacts, Kovar lead
frames, etc. Thermocouple voltages developed at these junctions commonly exceed the TCVOS contribution of the
AMP04. Component layout that takes into account the power
dissipation at critical locations in the circuit and minimizes gradient effects and differential common-mode voltages by taking
advantage of input symmetry will minimize many of these errors.
2
8
VOUT
6
3
1/2 OP-213
Figure 5. Cable Shield Drivers
High accuracy circuitry can experience considerable error contributions due to the coupling of stray voltages into sensitive
areas, including high impedance amplifier inputs which benefit
from such techniques as ground planes, guard rings, and
shields. Careful circuit layout, including good grounding and
REV. A
1
–7–
AMP04
Compensating for Input and Output Errors
To achieve optimal performance, the user needs to take into
account a number of error sources found in instrumentation
amplifiers. These consist primarily of input and output offset
voltages and leakage currents.
CEXT
100k
The input and output offset voltages are independent from one
another, and must be considered separately. The input offset
component will of course be directly multiplied by the gain of
the amplifier, in contrast to the output offset voltage that is independent of gain. Therefore, the output error is the dominant
factor at low gains, and the input error grows to become the
greater problem as gain is increased. The overall equation for
offset voltage error referred to the output (RTO) is:
R GAIN
IN(–) 2
1
8
6
INPUT BUFFERS
IN(+)
VOUT
3
11k
11k
VOS (RTO) = (VIOS × G) + VOOS
ƒLP =
where VIOS is the input offset voltage and VOOS the output offset
voltage, and G is the programmed amplifier gain.
The change in these error voltages with temperature must also
be taken into account. The specification TCVOS, referred to the
output, is a combination of the input and output drift specifications. Again, the gain influences the input error but not the output, and the equation is:
TCVOS (RTO) = (TCVIOS × G) + TCVOOS
In some applications the user may wish to define the error contribution as referred to the input, and treat it as an input error.
The relationship is:
TCVOS (RTI) = TCVIOS + (TCVOOS / G)
The bias and offset currents of the input transistors also have an
impact on the overall accuracy of the input signal. The input
leakage, or bias currents of both inputs will generate an additional offset voltage when flowing through the signal source resistance. Changes in this error component due to variations with
signal voltage and temperature can be minimized if both input
source resistances are equal, reducing the error to a commonmode voltage which can be rejected. The difference in bias current between the inputs, the offset current, generates a differential error voltage across the source resistance that should be
taken into account in the user’s design.
1
2π (100k) C EXT
100k
5
REF
Figure 6. Noise Band Limiting
a single-pole low-pass filter is produced. The cutoff frequency
(fLP) follows the relationship:
f LP =
1
2π (100 kΩ) CEXT
Filtering can be applied to reduce wide band noise. Figure 7a
shows a 10 Hz low-pass filter, gain of 1000 for the AMP04. Figures 7b and 7c illustrate the effect of filtering on noise. The
photo in Figure 7b shows the output noise before filtering. By
adding a 0.15 µF capacitor, the noise is reduced by about a
factor of 4 as shown in Figure 7c.
+15V
100
0.15µF
7
1
2
8 6
3
5
In applications utilizing floating sources such as thermocouples,
transformers, and some photo detectors, the user must take care
to provide some current path between the high impedance inputs and analog ground. The input bias currents of the AMP04,
although extremely low, will charge the stray capacitance found
in nearby circuit traces, cables, etc., and cause the input to drift
erratically or to saturate unless given a bleed path to the analog
common. Again, the use of equal resistance values will create a
common input error voltage that is rejected by the amplifier.
4
–15V
Figure 7a. 10 Hz Low-Pass Filter
5mV
10ms
100
90
Reference Input
The VREF input is used to set the system ground. For dual supply operation it can be connected to ground to give zero volts
out with zero volts differential input. In single supply systems it
could be connected either to the negative supply or to a pseudoground between the supplies. In any case, the REF input must
be driven with low impedance.
10
0%
Noise Filtering
Unlike most previous instrumentation amplifiers, the output
stage’s inverting input (Pin 8) is accessible. By placing a capacitor across the AMP04’s feedback path (Figure 6, Pins 6 and 8)
Figure 7b. Unfiltered AMP04 Output
–8–
REV. A
AMP04
1mV
First, the potentiometer should be adjusted to cause the
output to swing in the positive direction; then adjust it in
the reverse direction, causing the output to swing toward
ground, until the output just stops changing. At that point
the output is at the saturation limit.
2s
100
90
RG
10
0%
AMP-04
1
8
2
7
3
6
4
5
+5V
INPUT
Figure 7c. 10 Hz Low-Pass Filtered Output
Power Supply Considerations
OUTPUT
OP-113
In dual supply applications (for example ± 15 V) if the input is
connected to a low resistance source less than 100 Ω, a large
current may flow in the input leads if the positive supply is applied before the negative supply during power-up. A similar
condition may also result upon a loss of the negative supply. If
these conditions could be present in you system, it is recommended that a series resistor up to 1 kΩ be added to the input
leads to limit the input current.
+5V
100Ω
50k
Figure 9. Offset Adjust for Single Supply Applications
Alternative Nulling Method
An alternative null correction technique is to inject an offset current into the summing node of the output amplifier
as in Figure 10. This method does not require an external
op amp. However the drawback is that the amplifier will
move off its null as the input common-mode voltage
changes. It is a less desirable nulling circuit than the previous method.
This condition can not occur in a single supply environment as
losing the negative supply effectively removes any current return
path.
Offset Nulling in Dual Supply
Offset may be nulled by feeding a correcting voltage at the VREF
pin (Pin 5). However, it is important that the pin be driven with
a low impedance source. Any measurable resistance will degrade
the amplifier’s common-mode rejection performance as well as
its gain accuracy. An op amp may be used to buffer the offset
null circuit as in Figure 8.
V+
V–
100k
R GAIN
RG
1
IN(–) 2
VOUT
8
6
INPUT BUFFERS
IN(+)
AMP-04
1
–
INPUT
+
2
V+
3
3
8
7
11k
+5V
OUTPUT
6
+5V
4
V–
REF
5
+5V
11k
50k
100k
*
–5V
* OP-90 FOR LOW POWER
OP-113 FOR LOW DRIFT
–5V
100Ω
±5mV
ADJ
RANGE
5
50k
Figure 10. Current Injection Offsetting Is Not
Recommended
–5V
Figure 8. Offset Adjust for Dual Supply Applications
Offset Nulling in Single Supply
Nulling the offset in single supply systems is difficult because
the adjustment is made to try to attain zero volts. At zero volts
out, the output is in saturation (to the negative rail) and the output voltage is indistinguishable from the normal offset error.
Consequently the offset nulling circuit in Figure 9 must be used
with caution.
REV. A
REF
–9–
AMP04
APPLICATION CIRCUITS
Low Power Precision Single Supply RTD Amplifier
To calibrate, either immerse the RTD into a zero-degree ice
bath or substitute an exact 100 Ω resistor in place of the RTD.
Then adjust bridge BALANCE potentiometer R3 for a 0 volt
output. Note that a 0 volt output is also the negative output
swing limit of the AMP04 powered with a single supply. Therefore, be sure to adjust R3 to first cause the output to swing
positive and then back off until the output just stop swinging
negatively.
Figure 11 shows a linearized RTD amplifier that is powered off
a single +5 volt supply. However, the circuit will work up to 36
volts without modification. The RTD is excited by a 100 µA
constant current that is regulated by amplifier A (OP295). The
0.202 volts reference voltage used to generate the constant current is divided down from the 2.500 volt reference. The AMP04
amplifies the bridge output to a 10 mV/°C output coefficient.
R3
BALANCE
C3
0.1µF
R9
50Ω
+5V
500Ω
R1
26.7k
Next, set the LINEARITY ADJ. potentiometer to the midrange. Substitute an exact 247.04 Ω resistor (equivalent to
400°C temperature) in place of the RTD. Adjust the
FULL-SCALE potentiometer for a 4.000 volts output.
R8
383Ω
100Ω
R10
R2
26.7k
7
FULL-SCALE
ADJ
1
3
C1
0.47µF
8 6
AMP-04
VOUT
2
0→4.00V
(0°C TO 400°C)
5
4
RTD
100Ω
1
R4
100Ω
1/2
OP-295
2
1k
Precision 4-20 mA Loop Transmitter With Noninteractive
Trim
+5V
R7
121k
3
R5
1.02k
6
8
7
1/2
OP-295
4
R6
11.5k
2.5V
When properly calibrated, the circuit achieves better than
± 0.5°C accuracy within a temperature measurement range from
0°C to 400°C.
A
0.202V
R SENSE
Finally substitute a 175.84 Ω resistor (equivalent to 200°C
temperature), and adjust the LINEARITY ADJ potentiometer
for a 2.000 volts at the output. Repeat the full-scale and the
half-scale adjustments as needed.
Figure 12 shows a full bridge strain gage transducer amplifier
circuit that is powered off the 4-20 mA current loop. The
AMP04 amplifies the bridge signal differentially and is converted to a current by the output amplifier. The total quiescent
current drawn by the circuit, which includes the bridge, the amplifiers, and the resistor biasing, is only a fraction of the 4 mA
null current that flows through the current-sense resistor
RSENSE. The voltage across RSENSE feeds back to the OP90’s input, whose common-mode is fixed at the current summing
reference voltage, thus regulating the output current.
B
5
50k
LINEARITY
ADJ.
(@1/2 FS)
6
OUT
REF-43
GND
4
IN
2
+5V
C2
0.1µF
NOTES: ALL RESISTORS ±0.5%, ±25 PPM/°C
ALL POTENTIOMETERS ±25 PPM/°C
Figure 11. Precision Single Supply RTD Thermometer
Amplifier
The RTD is linearized by feeding a portion of the signal back to
the reference circuit, increasing the reference voltage as the temperature increases. When calibrated properly, the RTD’s nonlinearity error will be canceled.
With no bridge signal, the 4 mA null is simply set up by the
50 kΩ NULL potentiometer plus the 976 kΩ resistors that inject an offset that forces an 80 mV drop across RSENSE. At a
50 mV full-scale bridge voltage, the AMP04 amplifies the
voltage-to-current converter for a full-scale of 20 mA at the output. Since the OP90’s input operates at a constant 0 volt
common-mode voltage, the null and the span adjustments do
Figure 12. Precision 4-20 mA Loop Transmitter Features Noninteractive Trims
–10–
REV. A
AMP04
not interact with one another. Calibration is simple and easy
with the NULL adjusted first, followed by SPAN adjust. The
entire circuit can be remotely placed, and powered from the
4-20 mA 2-wire loop.
Single Supply Programmable Gain Instrumentation Amplifier
4-20 mA Loop Receiver
At the receiving end of a 4-20 mA loop, the AMP04 makes a
convenient differential receiver to convert the current back to a
usable voltage (Figure 13). The 4-20 mA signal current passes
through a 100 Ω sense resistor. The voltage drop is differentially
amplified by the AMP04. The 4 mA offset is removed by the
offset correction circuit.
Combining with the single supply ADG221 quad analog switch,
the AMP04 makes a useful programmable gain amplifier that
can handle input and output signals at zero volts. Figure 15
shows the implementation. A logic low input to any of the gain
control ports will cause the gain to change by shorting a gainset resistor across AMP04’s Pins 1 and 8. Trimming is required
at higher gains to improve accuracy because the switch ONresistance becomes a more significant part of the gain-set
resistance. The gain of 500 setting has two switches connected
in parallel to reduce the switch resistance.
+5V TO +30V
+15V
IN4002
4–20mA
4–20mA
TRANSMITTER
1k
8 6
AMP-04
VOUT
0–1.6V FS
2
7
GAIN OF 500
GAIN CONTROL
–0.400V
4
2
+ –
POWER
SUPPLY
–15V
OP-177
6
3
10k
27k
–
–15V
GAIN OF 100
GAIN OF 10
–
INPUT
+
OUT
10V
REF-01
GND
50k
0.22µF
1
VOUT
2
5
4
Figure 14. Pulsed Load Cell Bridge Amplifier
REV. A
RG
RG
2
V+
3
0.22µF
8
7
+5V
TO +30V
VOUT
6
V–
REF
5
0.1µF
The switch ON resistance is lower if the supply voltage is
12 volts or higher. Additionally the overall amplifier’s temperature coefficient also improves with higher supply voltage.
1N4148
6
100k
Figure 15. Single Supply Programmable Gain Instrumentation Amplifier
MEASURE
8
10.9k
12
AMP-04
2N3904
AMP-04
3
1
4
IN
10k
7
715Ω
2
1
+12V
+12V
16
WR
+
Figure 14 shows a 350 Ω load cell that is pulsed with a low duty
cycle to conserve power. The OP295’s rail-to-rail output capability allows a maximum voltage of 10 volts to be applied to the
bridge. The bridge voltage is selectively pulsed on when a measurement is made. A negative-going pulse lasting 200 ms should
be applied to the MEASURE input. The long pulse width is
necessary to allow ample settling time for the long time constant
of the low-pass filter around the AMP04. A much faster settling
time can be achieved by omitting the filter capacitor.
1/2
OP-295
200Ω
14
AD589
Low Power, Pulsed Load-Cell Amplifier
1k
6
8
15
Figure 13. 4-to-20 mA Line Receiver
350Ω
200Ω
9
WIRE RESISTANCE
3
4
11
0.1µF
10
5
330Ω
5
ADG221
+
1
3
100Ω 1%
1k
4–20mA
10µF
0.15µF
7
–
+
13
100k
–11–
AMP04
120
120
100
VS = +5V
VCM = 2.5V
TA = +25°C
VS = ±15V
VCM = 0V
NUMBER OF UNITS
NUMBER OF UNITS
BASED ON 300 UNITS
3 RUNS
TA = +25°C
BASED ON 300 UNITS
3 RUNS
100
80
60
40
80
60
40
20
20
0
–200 –160 –120
–80 –40
0
40
80
120
INPUT OFFSET VOLTAGE – µV
160
0
–0.5
200
–0.4
–0.3
–0.2 –0.1
0
0.1
0.2
0.3
INPUT OFFSET VOLTAGE – mV
120
120
300 UNITS
VS = +5V
100
300 UNITS
VS = ±15V
100
VCM = 2.5V
VCM = 0V
NUMBER OF UNITS
NUMBER OF UNITS
0.5
Figure 17. Input Offset (VIOS) Distribution @ ± 15 V
Figure 16. Input Offset (VIOS) Distribution @ +5 V
80
60
40
80
60
40
20
20
0
0
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
0
2.50
0.25
0.50
0.75
Figure 18. Input Offset Drift (TCVIOS) Distribution @ +5 V
1.25
1.50
1.75
2.25
2.50
120
BASED ON 300 UNITS
3 RUNS
TA = +25°C
VS = +5V
BASED ON 300 UNITS
3 RUNS
100
NUMBER OF UNITS
80
60
40
TA = +25 °C
VS = ±15V
VCM = 0V
VCM = 2.5V
80
60
40
20
20
0
–2.0
2.00
Figure 19. Input Offset Drift (TCVIOS) Distribution @ ± 15 V
120
100
1.00
TCV IOS – µV/ °C
TCV IOS – µV/ °C
NUMBER OF UNITS
0.4
0
–1.6
–1.2
–0.8 –0.4
0
0.4
0.8
OUTPUT OFFSET – mV
1.2
1.6
–5
2.0
–4
–3
–2
–1
0
1
2
OUTPUT OFFSET – mV
3
4
5
Figure 21. Output Offset (VOOS) Distribution @ ± 15 V
Figure 20. Output Offset (VOOS) Distribution @ +5 V
–12–
REV. A
AMP04
120
120
300 UNITS
VS = +5V
100
300 UNITS
VS = ±15V
100
VCM = 0V
NUMBER OF UNITS
NUMBER OF UNITS
VCM = 0V
80
60
40
20
80
60
40
20
0
0
0
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
TCV OOS – µV/ ° C
Figure 22. Output Offset Drift (TCVOOS) Distribution
@ +5 V
4.6
RL = 100k
+OUTPUT SWING – Volts
4.8
15.0
–OUTPUT SWING – Volts
OUTPUT VOLTAGE SWING – Volts
VS = +5V
–14.6
4.4
4.2
RL = 2k
RL = 10k
3.8
–50
–25
0
25
50
TEMPERATURE – °C
75
100
R
RLL =
= 100k
100k
14.5
16
18
20
22
24
VS = +5V
14.0
RL = 10k
13.5
13.0
RL = 2k
12.5
RL = 2k
–14.7
–14.8
RL = 10k
–14.9
–15.0
RL = 100k
–15.1
–50
–25
0
25
50
75
100
TEMPERATURE – °C
Figure 24. Output Voltage Swing vs. Temperature
@ +5 V
Figure 25. Output Voltage Swing vs. Temperature
@ +15 V
40
8
VS = +5V, VCM = 2.5V
35
VS = +5V, VCM = 2.5V
VS = ±15V, VCM = 0V
INPUT OFFSET CURRENT – nA
INPUT BIAS CURRENT – nA
14
Figure 23. Output Offset Drift (TCVOOS) Distribution
@ ± 15 V
5.0
4.0
12
TCV OOS – µV/ °C
30
VS = +5V
25
20
15
VS = ±15V
10
VS = ±15V , VCM = 0V
6
4
VS = ±15V
VS = +5V
2
5
0
–50
–25
0
25
50
75
0
–50
100
TEMPERATURE – °C
0
25
50
75
100
TEMPERATURE – °C
Figure 26. Input Bias Current vs. Temperature
REV. A
–25
Figure 27. Input Offset Current vs. Temperature
–13–
AMP04
50
120
TA = +25° C
VS = ±15V
G = 100
TA = +25 °C
100
OUTPUT IMPEDANCE – Ω
VOLTAGE GAIN – dB
40
30
G = 10
20
10
G=1
0
–10
G=1
80
VS = ±15V
60
40
VS = +5V
20
0
–20
100
1k
10k
FREQUENCY – Hz
100k
1M
Figure 28. Closed-Loop Voltage Gain vs. Frequency
10
10k
100k
120
TA = +25°C
TA = +25°C
VS = ±15V
VCM = 2V P-P
100
G = 100
COMMON-MODE REJECTION – dB
COMMON-MODE REJECTION – dB
1k
FREQUENCY – Hz
Figure 29. Closed-Loop Output Impedance vs. Frequency
120
80
60
G = 10
40
20
G=1
0
VS = ±15V
VCM = 2V P-P
110
100
90
80
70
60
–20
1
10
100
1k
FREQUENCY – Hz
10k
50
100k
1
Figure 30. Common-Mode Rejection vs. Frequency
10
100
VOLTAGE GAIN – G
1k
Figure 31. Common-Mode Rejection vs. Voltage Gain
140
140
TA = +25°C
VS = ±15V
120
∆V S = ±1V
G = 100
POWER SUPPLY REJECTION – dB
POWER SUPPLY REJECTION – dB
100
100
80
G = 10
60
40
G=1
20
0
TA = +25°C
VS = ±15V
120
∆V S = ±1V
G = 100
100
80
G = 10
60
40
G=1
20
0
10
100
1k
10k
FREQUENCY – Hz
100k
1M
Figure 32. Positive Power Supply Rejection vs. Frequency
10
100
1k
10k
FREQUENCY – Hz
100k
1M
Figure 33. Negative Power Supply Rejection vs. Frequency
–14–
REV. A
AMP04
1k
1k
TA = +25 °C
VS = ±15V
ƒ = 1kHz
VS = ±15V
ƒ = 100Hz
VOLTAGE NOISE – nV/ Hz
VOLTAGE NOISE – nV/ Hz
TA = +25 °C
100
10
1
100
10
1
1
10
100
VOLTAGE GAIN – G
1k
1
Figure 34. Voltage Noise Density vs. Gain
10
100
VOLTAGE GAIN – G
1k
Figure 35. Voltage Noise Density vs. Gain, f = 1 kHz
VOLTAGE NOISE DENSITY – nV/ Hz
140
TA = +25 °C
120
20mV
VS = ±15V
G = 100
1s
100
90
100
80
60
40
10
0%
20
0
1
10
100
FREQUENCY – Hz
1k
10k
VS = ±15V, GAIN = 1000, 0.1 TO 10 Hz BANDPASS
Figure 36. Voltage Noise Density vs. Frequency
Figure 37. Input Noise Voltage
1200
16
VS = ±15V
OUTPUT VOLTAGE – V
SUPPLY CURRENT – µA
TA = +25 °C
14
1000
800
600
VS = +5V
400
VS = ±15V
12
10
8
6
4
200
2
0
–50
–25
0
25
50
75
0
100
10
TEMPERATURE – °C
Figure 38. Supply Current vs. Temperature
REV. A
100
1k
LOAD RESISTANCE – Ω
10k
100k
Figure 39. Maximum Output Voltage vs. Load Resistance
–15–
AMP04
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8
C1720–24–10/92
8-Lead Plastic DIP (N-8)
5
0.280 (7.11)
0.240 (6.10)
1
4
0.070 (1.77)
0.045 (1.15)
0.430 (10.92)
0.348 (8.84)
0.325 (8.25)
0.300 (7.62)
0.015
(0.381) TYP
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
SEATING
PLANE
0.015 (0.381)
0.008 (0.204)
0°- 15°
8-Lead Cerdip (Q-8)
0.005 (0.13) MIN
0.055 (1.4) MAX
8
5
0.310 (7.87)
0.220 (5.59)
4
1
0.070 (1.78)
0.030 (0.76)
0.405 (10.29) MAX
0.200
(5.08)
MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.015 (0.38)
0.008 (0.20)
0°-15°
0.100 (2.54)
BSC
SEATING PLANE
PRINTED IN U.S.A.
8-Lead Narrow-Body SO (S0-8)
–16–
REV. A