データシート

[AK4686]
AK4686
Multi-channel CODEC with Capless Stereo Selector
AK4686 2ch ADC
ADC/DAC
4ch DAC
1
24bitCODEC
24bit
AK4686
I/O
AC
ADC 96dB DAC 100dB
† PORT1(ADC, DAC1)-PORT2(DAC2)
† ADC
6:1
† 2ch 24bit ADC
- 64
:
48kHz
- S/(N+D): 88dB
, S/N: 96dB
HPF
† 4ch 24bit DAC
- 128
:
192kHz
- 24
8
- S/(N+D): 88dB
, S/N: 100dB
†
† TTL
I/F
†
:
256fs, 384fs, 512fs 768fs (fs=32kHz ∼ 48kHz)
128fs, 192fs, 256fs 384fs (fs=64kHz ∼ 96kHz)
128fs, 192fs (fs=128kHz ~ 192kHz)
†2
I/F (PORT1, PORT2)
/
(PORT1)
- I/F
:
PORT2:
,
(16bit, 24bit), I2S
PORT1:
,
(16bit, 24bit), I2S
2
† I C-bus
µP I/F
†
:
- Digital I/O: 3.0V ∼ 3.6V
- Charge Pump: 3.0V ∼ 3.6V
- Analog: 3.0V ∼ 3.6V
†
: 48pinLQFP
MS1243-J-01
2010/10
-1-
[AK4686]
2Vrms
PWAD bit
LIN1
LIN2
LIN3
LIN4
LIN5
LIN6
PORT1
2ch
ADC
MCLK1
BICK1
LRCK1
SDTO1
SDTI1
MS1
HPF
RIN1
RIN2
RIN3
RIN4
RIN5
RIN6
Serial
I/F
PWDA1 bit
2Vrms
2ch
DAC
LOUT1
ROUT1
PWAD bit or PWDA1 bit
CVEE
CP
CN
Control
Charge
Pump
I/F
PDN pin
Analog Soft Mute
SDA
SCL
MT1N
MT2N
PDN
Analog Soft Mute
PWDA2 bit
PORT2
LOUT2
2ch
DAC
Serial
I/F
ROUT2
AVDD1
VSS1
CVDD
VSS2
AVDD2
VSS3
DVDD
VSS4
CAD1
MCLK2
BICK2
LRCK2
SDTI2
CAD0
AK4686 Block Diagram
MS1243-J-01
2010/10
-2-
[AK4686]
■
AK4686EQ
AKD4686
-20 ∼ +85°C
48pin LQFP (0.5mm pitch)
MT2N
MS1
SDTI1
MCLK1
MT1N
DVD D
VSS4
SDTO
LRCK1
BICK1
SD A
SCL
■
36 3 5 34 33 32 31 30 29 2 8 27 2 6 2 5
LIN1
37
24
NC
RIN1
38
23
BICK2
NC
39
22
MCL K2
LIN2
40
21
LRC K2
RIN2
41
20
SDTI2
NC
42
19
PDN
LIN3
43
18
CVDD
RIN3
44
17
CP
NC
45
16
VSS3
LIN4
46
15
CN
RIN4
47
14
CVEE
NC
48
13
VSS2
AK4686EQ
RIN5
NC
LIN6
RIN6
AVDD1
7
8
9
1 0 11 12
MS1243-J-01
AVDD2
6
ROUT2
5
LOUT2
4
ROUT1
3
LOUT1
2
VSS1
1
LIN5
Top Vie w
2010/10
-3-
[AK4686]
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Name
LIN5
RIN5
NC
LIN6
RIN6
AVDD1
VSS1
LOUT1
ROUT1
LOUT2
ROUT2
AVDD2
VSS2
CVEE
CN
VSS3
CP
CVDD
I/O
I
I
I
I
O
O
O
O
O
I
I
-
19
PDN
I
20
21
22
23
24
SDTI2
LRCK2
MCLK2
BICK2
NC
I
I
I
I
-
25
MT2N
I
26
MS1
I
27
28
SDTI1
MCLK1
I
I
29
MT1N
I
30
31
32
33
34
35
36
37
38
39
40
41
42
DVDD
VSS4
SDTO
LRCK1
BICK1
SDA
SCL
LIN1
RIN1
NC
LIN2
RIN2
NC
O
I/O
I/O
I/O
I
I
I
I
I
-
Function
Lch Input 5 Pin
Rch Input 5 Pin
This pin must be connected to the ground.
Lch Input 6 Pin
Rch Input 6 Pin
ADC&DAC1 Analog Power Supply Pin, 3.0V∼3.6V
ADC&DAC1 Analog Ground Pin, 0V
Lch Analog Output Pin1
Rch Analog Output Pin1
Lch Analog Output Pin2
Rch Analog Output Pin2
DAC2 Analog Power Supply Pin, 3.3V∼3.6V
DAC2 Analog Ground Pin, 0V
Charge Pump Circuit Negative Voltage Output Pin (for Analog Input/Output)
Negative Charge Pump Capacitor Terminal Pin (for Analog Input/Output)
Charge Pump Circuit Analog Ground Pin, 0V (for Analog Input/Output)
Positive Charge Pump Capacitor Terminal Pin (for Analog Input/Output)
Charge Pump Circuit Positive Power Supply Pin 3.0V∼3.6V (for Analog Input/Output)
Power-Down Mode & Reset Pin
When “L”, the AK4686 is powered-down, all registers are reset. And then all digital
output pins go “L”. The AK4686 must be reset once upon power-up.
Audio Serial Data Input Pin (for PORT2)
Input Channel Clock Pin (for PORT2)
DAC2 Master Clock Input Pin (for PORT2)
Audio Serial Data Clock Pin (for PORT2)
This pin must be connected to the ground.
DAC2 Mute Pin
“H”: Normal Operation
“L”: Mute
PORT1 Master Mode Select Pin.
“L”(connected to the ground): Slave mode.
“H”(connected to DVDD) : Master mode.
Audio Serial Data Input Pin (for PORT1)
ADC&DAC1 Master Clock Input Pin (for PORT1)
DAC1 Mute Pin
“H”: Normal Operation
“L”: Mute
Digital Power Supply Pin, 3.0V∼3.6V
Digital Ground Pin, 0V
Audio Serial Data Output 1 Pin (for PORT1)
Channel Clock 1 Pin (for PORT1)
Audio Serial Data Clock 1 Pin (for PORT1)
Control Data Pin
Control Data Clock Pin
Lch Input 1 Pin
Rch Input 1 Pin
This pin must be connected to the ground.
Lch Input 2 Pin
Rch Input 2 Pin
This pin must be connected to the ground.
MS1243-J-01
2010/10
-4-
[AK4686]
(
No.
43
44
45
46
47
48
Note:
Pin Name
LIN3
RIN3
NC
LIN4
RIN4
NC
I/O
I
I
I
I
-
)
Function
Lch Input 3 Pin
Rch Input 3 Pin
This pin must be connected to the ground.
Lch Input 4 Pin
Rch Input 4 Pin
This pin must be connected to the ground.
■
Analog
Digital
-
LOUT1-2, ROUT1-2, LIN1-6, RIN1-6
SDTO1, LRCK1(Master), BICK1(Master)
MCLK1-2, LRCK1(Slave), LRCK2, BICK1(Slave),
BICK2, SDTI1-2, MS1, CAD0
These pins must be open.
These pins must be open.
These pins must be connected to VSS4.
SDA, SCL, MT1N, MT2N
These pins must be pulled-up to DVDD.
NC
These pins should be connected to the ground.
MS1243-J-01
2010/10
-5-
[AK4686]
(VSS1=VSS2=VSS3=VSS4 =0V; Note 1)
Parameter
Power Supply
Input Current (any pins except for supplies)
Digital Input Voltage
(MCLK1-2, PDN, LRCK1-2, BICK1-2,
SDTI1-2, SDA, SCL, MS1, CAD0, MT1N and
MT2N pins)
Analog Input Voltage
(LIN1-6, RIN1-6 pins)
Ambient Operating Temperature
Storage Temperature
Note 1. VSS1, VSS2, VSS3, VSS4
Symbol
DVDD
AVDD1
AVDD2
CVDD
IIN
VIND
min
-0.3
-0.3
-0.3
-0.3
-0.3
max
4.0
4.0
4.0
4.0
±10
DVDD+0.3
Units
V
V
V
V
mA
V
VINA
-0.3
AVDD1+0.3
V
Ta
Tstg
-20
-65
85
150
°C
°C
typ
3.3
3.3
3.3
3.3
max
3.6
3.6
3.6
3.6
Units
V
V
V
V
:
(VSS1=VSS2=VSS3=VSS4= 0V; Note 1)
Parameter
Power Supply (Note 2)
Symbol
DVDD
AVDD1
AVDD2
CVDD
Note 2. AVDD1, AVDD2, CVDD
DVDD
(AVDD1, AVDD2, CVDD)
min
3.0
3.0
3.0
3.0
0.3V
:
MS1243-J-01
2010/10
-6-
[AK4686]
(Ta=25°C; AVDD1=AVDD2= CVDD = DVDD= 3.3V; VSS1=VSS2= VSS3=VSS4=0V; fs=48kHz; BICK=64fs; Signal
Frequency=1kHz; 24bit Data; Measurement Frequency = 20Hz∼ 20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz;
20Hz~40kHz at fs=192kHz, all blocks are synchronized, unless otherwise specified)
Parameter
min
typ
max
Units
Input Impedance
12
16.4
kΩ
Analog Input (LIN1-6, RIN1-6pin) to ADC Analog Input Characteristics
Resolution
24
Bits
S/(N+D)
(-1dBFS)
fs=48kHz
75
88
dB
DR
(-60dBFS)
fs=48kHz, A-weighted
88
96
dB
S/N
(input off)
fs=48kHz, A-weighted
88
96
dB
Interchannel Isolation
(Note 3)
90
100
dB
Interchannel Gain Mismatch
0
0.6
dB
Gain Drift
50
ppm/°C
Input Voltage
AIN= 2.2 x AVDD1/3.3
2
2.2
2.4
Vrms
Power Supply Rejection
(Note 4)
50
dB
DAC to Analog Output (LOUT1-2, ROUT1-2 pin) Characteristics
Resolution
24
Bits
S/(N+D)
(0dBFS)
fs=48kHz
76
88
dB
fs=96kHz
84
dB
fs=192kHz
84
dB
DR
(-60dBFS)
fs=48kHz, A-weighted
94
100
dB
fs=96kHz
96
dB
fs=96kHz, A-weighted
100
dB
fs=192kHz
96
dB
fs=192kHz, A-weighted
100
dB
S/N
(“0” data)
fs=48kHz, A-weighted
94
100
dB
fs=96kHz
96
dB
fs=96kHz, A-weighted
100
dB
fs=192kHz
96
dB
fs=192kHz, A-weighted
100
dB
Interchannel Isolation
90
100
dB
Interchannel Gain Mismatch
0
0.5
dB
Gain Drift
50
ppm/°C
Output Voltage
AOUT= 2 x AVDD1(AVDD2)/3.3
1.90
2
2.15
Vrms
Load Resistance
(AC Load)
5
kΩ
Load Capacitance
(C1)
30
pF
Load Resistance
(R1)
446.5
470
Ω
Load Capacitance
(C2)
1
1.5
nF
Power Supply Rejection
(Note 4)
50
dB
Note 3. 1
Full Scale
Note 4. AVDD1, AVDD2, DVDD,CVDD 1kHz, 50mVpp
LOUT/ROUT1,2 pin
R1
C1
Analog
Out
C2
Figure 1. Lineout Circuit Example
MS1243-J-01
2010/10
-7-
[AK4686]
Power Supplies
Parameter
Power Supply Current
Normal Operation (PDN pin = “H”)
DVDD+AVDD1+AVDD2
CVDD
Power-Down Mode (PDN pin = “L”; Note 5)
DVDD+AVDD1+AVDD2+CVDD
Note 5.
min
max
Units
26
8
34
13
mA
mA
10
100
μA
(MCLK1-2, BICK1-2, LRCK1-2, SDTI1-2) DVDD, VSS4
(Ta=-20°C ~+85°C; AVDD1=AVDD2= CVDD = DVDD= 3.3V; fs=48kHz)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
Passband
(Note 6)
PB
0
±0.1dB
-0.2dB
-3.0dB
Stopband
SB
27.9
Stopband Attenuation
SA
61
Group Delay
(Note 7)
GD
Group Delay Distortion
ΔGD
ADC Digital Filter (HPF):
Frequency Response (Note 6)
-3dB
FR
-0.1dB
DAC Digital Filter:
Passband
(Note 6)
-0.1dB
PB
0
-6.0dB
Stopband
SB
26.2
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay
(Note 7)
GD
DAC Digital Filter + Analog Filter:
FR
Frequency Response: 0 ∼ 20.0kHz
FR
40.0kHz (Note 8)
FR
80.0kHz (Note 8)
Note 6.
typ
fs
-0.1dB
Note 7.
DAC
typ
max
Units
19.9
22.9
18.5
-
15.7
0
kHz
kHz
kHz
kHz
dB
1/fs
µs
1.0
6.5
Hz
Hz
24.0
21.8
±0.02
19
±0.2
±0.3
±1.0
21.8kHz 0.454 x fs(DAC)
24
20/24
kHz
kHz
kHz
dB
dB
1/fs
dB
dB
dB
1kHz
PORT1
PORT1
PORT2
Note 8. 40.0kHz@fs=96kHz, 80.0kHz@fs=192kHz.
MS1243-J-01
2010/10
-8-
[AK4686]
DC
(Ta=-20°C ~+85°C; AVDD1=AVDD2=CVDD = DVDD= 3.3V)
Parameter
Symbol
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
High-Level Output Voltage ( Iout=-400μA)
VOH
Low-Level Output Voltage
VOL
(Iout= -400μA(except SDA pin), 3mA(SDA pin))
Iin
Input Leakage Current
min
70%DVDD
DVDD-0.4
-
typ
-
max
30%DVDD
0.4
Units
V
V
V
V
-
-
±10
μA
(Ta=-20°C ~+85°C; AVDD1=AVDD2=CVDD = DVDD= 3.3V; CL= 20pF (except for SDA pin), Cb=400pF(SDA pin))
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fECLK
8.192
36.864
MHz
Duty
dECLK
40
50
60
%
Master Clock
256fsn, 128fsd:
fCLK
8.192
12.288
MHz
Pulse Width Low
tCLKL
27
ns
Pulse Width High
tCLKH
27
ns
384fsn, 192fsd:
fCLK
12.288
18.432
MHz
Pulse Width Low
tCLKL
20
ns
Pulse Width High
tCLKH
20
ns
512fsn, 256fsd, 128fsq:
fCLK
16.384
24.576
MHz
Pulse Width Low
tCLKL
15
ns
Pulse Width High
tCLKH
15
ns
768fsn, 384fsd, 192fsq:
fCLK
24.576
36.864
MHz
Pulse Width Low
tCLKL
10
ns
Pulse Width High
tCLKH
10
ns
LRCK1/2Timing (Slave Mode)
Normal mode
Normal Speed Mode
fsn
32
48
kHz
Double Speed Mode
fsd
64
96
kHz
Quad Speed Mode
fsq
128
192
kHz
Duty Cycle
Duty
45
55
%
LRCK1 Timing (Master Mode)
Normal mode
Normal Speed Mode
fsn
32
48
kHz
Double Speed Mode
fsd
64
96
kHz
Quad Speed Mode
fsq
128
192
kHz
Duty Cycle
Duty
50
%
Power-down & Reset Timing
PDN Pulse Width
(Note 9)
tPD
150
ns
PDN “↑” to SDTO1 valid (Note 10)
tPDV
296
1/fs
Note 9. AK4686 PDN pin = “L”
Note 10. PDN pin
MCLK
LRCK
256/fs
CVEE
ADC
40/fs
SDTIO1
MS1243-J-01
2010/10
-9-
[AK4686]
Parameter
Audio Interface Timing (Slave Mode)
PORT1(DAC1), PORT2(DAC2)
BICK1, 2 Period
BICK1, 2 Pulse Width Low
Pulse Width High
LRCK1, 2 Edge to BICK1, 2 “↑” (Note 11)
BICK1, 2 “↑” to LRCK1, 2 Edge (Note 11)
SDTI1, 2 Hold Time
SDTI1, 2 Setup Time
PORT1 (ADC)
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑” (Note 11)
BICK1 “↑” to LRCK1 Edge (Note 11)
LRCK1 to SDTO1 (MSB)
BICK1 “↓” to SDTO1
Audio Interface Timing (Master Mode)
BICK1 Frequency
BICK1 Duty
BICK1 “↓” to LRCK1 Edge
BICK1 “↓” to SDTO1
SDTI1 Hold Time
SDTI1 Setup Time
Control Interface Timing (I2C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 12)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Note 11.
LRCK
BICK
Note 12.
300ns (SCL
)
Note 13. I2C-bus NXP B.V.
MS1243-J-01
Symbol
min
typ
max
Units
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
81
32
32
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
324
128
128
80
80
ns
ns
ns
ns
ns
ns
ns
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
80
80
64fs
50
-20
20
20
Hz
%
ns
ns
ns
ns
25
10
fSCL
tBUF
tHD:STA
1.3
0.6
400
-
kHz
μs
μs
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
1.3
0.6
0.6
0
0.1
0.6
0
0.3
0.3
50
400
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
2010/10
- 10 -
[AK4686]
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing (Normal mode)
VIH
LRCK
VIL
tBLR
tLRB
tLRS
VIH
BICK
VIL
tBSD
SDTO
50% TVDD
tSDS
tSDH
VIH
SDTI
VIL
Audio Interface Timing
LRCK= LRCK1, LRCK2
BICK= BICK1, BICK2
SDTI= SDTI1/2
SDTO= SDTO1.
MS1243-J-01
2010/10
- 11 -
[AK4686]
LRCK
50% TVDD
tMBLR
50% TVDD
BICK
tBSD
50% TVDD
SDTO
Audio Interface timing (Master Mode)
tPD
VIH
PDN
VIL
tPDV
50% TVDD
SDTO
Power Down & Reset Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
I2C Bus mode Timing
MS1243-J-01
2010/10
- 12 -
[AK4686]
■
AK4686
ADC, DAC1
2 (PORT1, PORT2)
PORT1
PORT2 DAC2
PORT
MCLK 1(MCLK2), LRCK1 (LRCK2), BICK1 (BICK2)
MCLK1 (MCLK2)
LRCK1 (LRCK2)
PORT
(PDN pin = “H”) MCLK1(MCLK2) 2µs
BICK1 or LRCK1 (BICK2 or LRCK2)
1024*MCLK
ADC
“0”
DAC
Pull
Down(VSS)
MCLK1, BICK1, LRCK1 (MCLK2, BICK2, LRCK2)
ON
(PDN pin = “L” → “H”) MCLK1 (MCLK2)
AK4686 LRCK
■
/
MS1 pin PORT1
/
LRCK1 pin BICK1 pin
(BICK2) pin
(Table 1)
PDN pin
MS1 pin
L
L
H
PORT2
LRCK1 (LRCK2) pin
PORT1 (ADC, DAC1)
BICK1, LRCK1
Input (slave mode)
Output “L”(master mode)
BICK1
PORT2 (DAC2)
BICK2, LRCK2
Input (slave mode)
Input (slave mode)
Table 1. Master/Salve Mode
MS1243-J-01
2010/10
- 13 -
[AK4686]
■ PORT1(ADC,DAC1)
(MS1 pin = “H”) CKS12-10 bit
(PDN pin = “L” or PWAD bit , PWDA1 bit = “0”)
ADC, DAC1 MCLK1
CKS12
CKS11
CKS10
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
(Table 2) ADC, DAC1
(MCLK1)
Sampling Speed (fs)
Normal or Double
Normal or Double
Normal
Normal
Double or Quad
Double or Quad
32kHz~48kHz, 64kHz~96kHz
32kHz~48kHz, 64kHz~96kHz
32kHz~48kHz
32kHz~48kHz
64kHz~96kHz, 128kHz~192kHz
64kHz~96kHz, 128kHz~192kHz
X
Master Clock
Speed
256fs
384fs
512fs
768fs
128fs
192fs
N/A
(default)
Table 2. PORT1(ADC, DAC1) Master Clock Control (Master Mode)
(MS1 pin = “L”) ADC, DAC1
(MCLK1, BICK1, LRCK1)
“0”)
(PDN pin = “L” or PWAD bit = PWDA1 bit = “0”)
(PDN pin = “↑”) MCLK1, LRCK1
ADC,DAC1
Setting Mode (ACKS1 bit = “0”)
ADC Normal Speed Mode
(PDN pin = “L” or PWAD bit = PWDA1 bit =
MCLK1 LRCK1
ADC, DAC1
(RSTN bit = “0”)
ON
DFS1-0 bit
Auto Setting Mode (ACKS1 bit = “1”).
Double Speed Mode, Quad Speed Mode
1. Manual Setting Mode (ACKS1 bit = “0”)
ACKS1 bit = “0” ADC, DAC1 Manual Setting Mode
DFS11-10 bit= “00” (Normal Speed Mode)
DFS11
DFS10
0
0
0
1
Power down
1
0
Power down
1
1
Manual
ADC Normal Speed Mode
ADC Sampling Speed (fs)
Normal Speed
32kHz~48kHz
Mode
DAC1 Sampling Speed (fs)
Normal Speed
32kHz~48kHz
Mode
Double Speed
64kHz~96kHz
Mode
Quad Speed
128kHz~192kHz
Mode
Not Available
(default)
Table 3. PORT1(ADC, DAC1) Sampling Speed (ACKS1bit = “0”, Manual Setting Mode)
LRCK1
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK1 (MHz)
384fs
512fs
12.2880
16.3840
16.9344
22.5792
18.4320
24.5760
768fs
24.5760
33.8688
36.8640
BICK1 (MHz)
64fs
2.0480
2.8224
3.0720
Table 4. ADC, DAC1 system clock example (ADC, DAC1 Normal Speed Mode @Manual Setting Mode)
MS1243-J-01
2010/10
- 14 -
[AK4686]
LRCK1
fs
88.2kHz
96.0kHz
128fs
11.2896
12.2880
MCLK1 (MHz)
192fs
256fs
16.9344
22.5792
18.4320
24.5760
384fs
33.8688
36.8640
BICK1 (MHz)
64fs
5.6448
6.1440
Table 5. DAC1 system clock example (DAC1 Double Speed Mode @Manual Setting Mode)
LRCK1
fs
176.4kHz
192.0kHz
128fs
22.5792
24.5760
MCLK1 (MHz)
192fs
256fs
33.8688
36.8640
-
384fs
-
BICK1 (MHz)
64fs
11.2896
12.2880
Table 6. DAC1 system clock example (DAC1 Quad Speed Mode @Manual Setting Mode)
2. Auto Setting Mode (ACKS1 bit = “1”)
ACKS1 bit = “1” ADC,DAC1 Auto Setting Mode
ADC Normal Speed Mode
(Table 13, Table 14)
MCLK1
512fs, 768fs
256fs, 384fs
128fs, 192fs
LRCK1
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
MCLK1/LRCK1
Double Speed Mode, Quad Speed Mode
DFS11-10 bit
ADC Sampling Speed
Normal Speed Mode
Power down
Power down
DAC Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Table 7. PORT1 (ADC, DAC1) Sampling Speed (ACKS1 bit = “1”, Auto Setting Mode)
LRCK1
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
192fs
MCLK1 (MHz)
256fs
384fs
22.5792 33.8688
24.5760 36.8640
22.5792 33.8688
24.5760 36.8640
-
512fs
768fs
ADC
Sampling
Speed
DAC1
Sampling
Speed
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Normal
Normal
-
-
Power down
Double
Power down
Quad
Table 8. PORT1 (ADC, DAC1) System clock example (Auto Setting Mode)
MS1243-J-01
2010/10
- 15 -
[AK4686]
■ PORT2(DAC2)
DAC
(RSTN bit = “0”)
(PDN pin = “L” or PWDA2 bit) = “0”)
(MCLK2, BICK2, LRCK2)
MCLK2 LRCK2
DAC
(PDN pin = “L” or PWDA2 bit = “0”)
ON
(PDN pin = “↑”) MCLK2, LRCK2
DAC2
Mode (ACKS2 bit = “0”)
DFS21-20 bit
1. Manual Setting Mode (ACKS2 bit = “0”)
ACKS2 bit = “0” DAC2 Manual Setting Mode
9)
DFS21
0
0
1
1
Manual Setting
Auto Setting Mode (ACKS2 bit = “1”).
DFS20
0
1
0
1
DFS21-20 bit
DAC2 Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
128kHz~192kHz
Not Available
-
(Table
(default)
Table 9. PORT2(DAC2) sampling speed (ACKS2 bit = “0”, Manual Setting Mode)
LRCK2
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK2 (MHz)
384fs
512fs
12.2880
16.3840
16.9344
22.5792
18.4320
24.5760
768fs
24.5760
33.8688
36.8640
BICK2 (MHz)
64fs
2.0480
2.8224
3.0720
Table 10. DAC2 system clock example (DAC Normal Speed Mode @Manual Setting Mode)
LRCK2
fs
88.2kHz
96.0kHz
128fs
11.2896
12.2880
MCLK2 (MHz)
192fs
256fs
16.9344
22.5792
18.4320
24.5760
384fs
33.8688
36.8640
BICK2 (MHz)
64fs
5.6448
6.1440
Table 11. DAC2 system clock example(DAC Double Speed Mode @Manual Setting Mode)
LRCK2
Fs
176.4kHz
192.0kHz
128fs
22.5792
24.5760
MCLK2 (MHz)
192fs
256fs
33.8688
36.8640
-
384fs
-
BICK2 (MHz)
64fs
11.2896
12.2880
Table 12. DAC2 system clock example (DAC Quad Speed Mode @Manual Setting Mode)
MS1243-J-01
2010/10
- 16 -
[AK4686]
2. Auto Setting Mode (ACKS2 bit = “1”)
ACKS2 bit = “1” DAC2 Auto Setting Mode
(Table 13, Table 14)
MCLK2
512fs, 768fs
256fs, 384fs
128fs, 192fs
MCLK2/LRCK2
DFS21-20 bit
DAC Sampling Speed (fs) LRCK2
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
128kHz~192kHz
Table 13. PORT2(DAC2) Sampling Speed (ACKS2 bit = “1”, Auto Setting Mode)
LRCK2
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
192fs
33.8688
36.8640
MCLK2 (MHz)
256fs
384fs
22.5792
33.8688
24.5760
36.8640
-
512fs
16.3840
22.5792
24.5760
-
768fs
24.5760
33.8688
36.8640
-
Sampling
Speed
Normal
Double
Quad
Table 14. PORT2 (DAC2) System clock example (Auto Setting Mode)
■
DAC IIR
3
(32kHz, 44.1kHz, 48kHz)
Double Speed Mode Quad Speed Mode
DAC1 (DEM11-10 bits), DAC2 (DEM21-20 bits)
Mode
0
1
2
3
DEM11
(DEM21)
0
0
1
1
DEM10
(DEM20)
0
1
0
1
(50/15μs
OFF
)
DEM
44.1kHz
OFF
48kHz
32kHz
(default)
Table 15. De-emphasis control
■
HPF
ADC DC
HPF
HPF
fc
fs=48kHz
1.0Hz
fs
MS1243-J-01
2010/10
- 17 -
[AK4686]
■
PORT
bit (DIF21-20 bit)
SDTO1 BICK1
SDTI1(SDTI2)
MSB
SDTI1(SDTI2)
LSB
PORT1 (PORT2)
2’s compliment
BICK1(BICK2)
“0”
DIF11-10
1. PORT1(ADC,DAC1)
MS1 pin, DIF11-10 bit
Mode
0
1
2
3
4
5
6
7
MS1
pin
DIF11
bit
4
DIF10
bit
(Table 16)
SDTO
SDTI1
LRCK1
L/R
I/O
BICK1
speed
I/O
≥ 48fs or
0
0
0
24/16bit, L J
16bit, R J
H/L
I
I
32fs
0
0
1
24bit, L J
24bit, R J
H/L
I
I
≥ 48fs
0
1
0
24bit, L J
24bit, L J
H/L
I
I
≥ 48fs
0
1
1
24bit, I2S
24bit, I2S
L/H
I
I
(default)
≥ 48fs
1
0
0
24bit, L J
16bit, R J
H/L
O
64fs
O
1
0
1
24bit, L J
24bit, R J
H/L
O
64fs
O
1
1
0
24bit, L J
24bit, L J
H/L
O
64fs
O
1
1
1
24bit, I2S
24bit, I2S
L/H
O
64fs
O
(default)
Table 16. Audio Interface Format (Normal mode, x: Don’t care. L J: Left justified. R J: Right justified.)
2. PORT2(DAC2)
DIF21-20 bit
(Table 17)
4
Mode
DIF21
bit
DIF20
bit
SDTI2
0
0
0
16bit, Right justified
1
2
3
0
1
1
1
0
1
24bit, Right justified
H/L
I
24bit, Left justified
H/L
I
24bit, I2S
L/H
I
Table 17. Audio Interface Format
LRCK2
L/R
I/O
MS1243-J-01
H/L
I
BICK2
speed
I/O
≥ 48fs
I
or 32fs
I
≥ 48fs
I
≥ 48fs
I
≥ 48fs
(default)
2010/10
- 18 -
[AK4686]
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
12 11 10
Don’t Care
0
15 14
23 22
8
7
1
12
11 10
Don’t Care
0
0
15 14
SDTO-23:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 2. Mode 0/4 Timing
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK (64fs)
SDTO(o)
23 22
16 15 14
Don’t Care
SDTI(i)
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 3. Mode 1/5 Timing
LRCK
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK (64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
Don’t Care
23
Rch Data
Figure 4. Mode 2/6 Timing
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK (64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 5. Mode 3/7 Timing
MS1243-J-01
2010/10
- 19 -
[AK4686]
■
MT1N/2N pin
“H”
“L”
DAC
(VSS1/VSS3)
LOUT1, ROUT1/LOUT2, ROUT2
AMTS1-0 bit
MT1N/2N pin “L”
“H”
DAC
DAC
MT1N/2N bit=”0”
LOUT1, ROUT1/LOUT2, ROUT2
MT1N/2N pin = “L”
DAC
Power(PDN pin)
MT1N/2N pin
(1)
MT1N/2N bit
Normal Operation
DAC Internal State
Init Cycle
512/fs
Normal Operation
GD
(2)
(3)
LOUT1,ROUT1/
LOUT2,ROUT2
(1)
(DVDD, AVDD1/2, CVDD)
AMTS1-0 bit
(DVDD, AVDD1/2, CVDD)
AMTS1-0 bit
(2)
AMTS1-0 bit
(3)
(2)
(3)
Figure 6.
AMTS2 AMTS1 AMTS0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
Table 18.
AMTS2-0 bits = “101” or “11X”
(fs=48kHz
)
(2)
MT1N/2N pin
MT1N/2N bit
16ms
16ms
32ms
32ms
64ms
64ms
128ms
128ms
256ms
256ms
8ms
16ms
2ms
16ms
(3)
MT1N/2N
16ms
32ms
64ms
128ms
256ms
16ms
16ms
(X: Don’t care)
(@48kHz)
(default)
MT1N/2N pin MT1N/2N bit
MS1243-J-01
2010/10
- 20 -
[AK4686]
■
AK4686 6:1
AIN3-0 bit
AIN3 bit
0
0
0
0
0
0
0
0
1
AIN2 bit
AIN1 bit
AIN0 bit
Input Selector
0
0
0
LIN1 / RIN1
0
0
1
LIN2 / RIN2
0
1
0
LIN3 / RIN3
0
1
1
LIN4 / RIN4
1
0
0
LIN5 / RIN5
1
0
1
LIN6 / RIN6
1
1
0
(reserved)
1
1
1
(reserved)
x
x
x
Mute
Table 19. Input Selector (for ADC, x: Don’t care)
MS1243-J-01
(Table 19)
(default)
2010/10
- 21 -
[AK4686]
■
CVDD pin
(CVEE)
5.3ms@48kHz
= “1”
ADC DAC1/2 (PWAD = PWDA1/2 bits
)
■
(LIN1-6/RIN1-6,LOUT1-2/ROUT1-2 pins)
AVDD2
CVDD
VSS3 (0V)
5kΩ (min)
DAC 0dBFS
DC
2Vrms (typ)
■
PDN pin = “L”
PDN pin
(DVDD, AVDD1, AVDD2, CVDD)
(PDN pin = “L” Æ “H”)
“H”
PDN pin
MS1243-J-01
2010/10
- 22 -
[AK4686]
■
AK4686
(PDN pin) “L”
PDN pin = “L”
0V SDTO1 pin “L”
ADC/DAC1/DAC2
LRCK1/2
“↑”
MLCK1/2
MCLK1/2 LRCK1/2
ADC
ADC
514/fs
DAC
0V
Figure 7
DAC PWAD bit PWDA1 bit, PWDA2 bit
PWAD bit = “0”
ADC
0V
“L”
PWDA bit = “0”
Power
(1)
PDN
(2)
0V
CVEE pin
0V
CVEE
40/fs (3)
ADC Internal
State
(12)
Init Cycle
(4)
Normal Operation
Power-down
Normal Operation
Power-down
5/fs
DAC Internal
State
GD
(5)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
“0”data
(6)
(7)
“0”data
“0”data
(5)
GD
(8)
GD
(8)
DAC Out
(Internal Status)
(9)
Clock In
Don’t care
Don’t care
MCLK,LRCK,BICK
MT1N/2N pin or
MT1N/2N bit
LOUT1,ROUT1/LOUT2
Mute ON
Mute ON
(11)
(11)
Mute
0V
Normal
(10)
(10) Mute
0V
,ROUT2 pins
Figure 7. Power-up/down sequence example
(1)
PDN pin “L”Æ“H”
AK4686
PDN pin = “L”
PDN pin “H”
150ns
“L”
(DVDD, AVDD1/2, CVDD1)
MS1243-J-01
2010/10
- 23 -
[AK4686]
(2)
:
PDN pin = “L” Æ “H” & MCLK1 or MCLK2
CVEE pin
5.3ms(fs=48KHz)
CVEE
:Charge-Pump
PWAD, PWDA1/2 bit
Charge-Pump
(3) ADC
(4) DAC
(5)
(6)
(7)
ADC
(8) PDN
) 512/fs
(9) CVEE pin
CVEE pin
17.5kΩ (typ)
(10)
20mV(
)
(11)
MUTE
+2msec)
(12)
PDN pin = “H” Æ “L”
CVEE pin
CVEE pin
“1”
ADC, DAC1/2
(GD)
“0”
ADC
PDN
(
0V
AMTS1-0 bit
Mute Normal
5mV DC
5.3ms(fs=48KHz)+2msec
DC
PDN
(CVEE
:
CAP
0V
CAP 2.2µF
MS1243-J-01
50k
(typ)
110ms(typ)
2010/10
- 24 -
[AK4686]
■
RSTN bit = “0”
ADC DAC
0V SDTO1 pin “L”
Figure 8 RSTN bit
RSTN bit
1~2/fs
4~5/fs (7)
Internal
RSTN bit
516/fs
ADC Internal
State
Normal Operation
Digital Block Power-down
DAC Internal
State
Normal Operation
Digital Block Power-down
GD
(1)
Normal Operation
Init Cycle
Normal Operation
(2)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
(4)
(3)
“0”data
(2)
GD
GD
(6)
DAC Out
(Analog)
(5)
(6)
(1) ADC
(2)
(GD)
(3)
(4)
ADC
(5) RSTN bit = “0”
(6) RSTN1 bit “0”
(7) RSTN bit
“0”
“0”
ADC
0V
4∼5/fs
LSI
RSTN bit
“1”
RSTN
1∼2/fs
4~5/fs
Figure 8. Reset sequence example
MS1243-J-01
2010/10
- 25 -
[AK4686]
■
AK4686 I2C
(max:400kHz)
1.
IC
·
1
·
IC
IC
READ
IC
WRITE
·
1-1.
“H”
SDA
“H”
·
·
“L”
SCL
“L”
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 9. Data transfer
1-2.
SCL
“H”
SDA
“H”
·
“L”
·
SCL
·
“H”
SDA
“L”
“H”
·
SCL
SDA
START CONDITION
STOP CONDITION
Figure 10. START and STOP conditions
MS1243-J-01
2010/10
- 26 -
[AK4686]
1-3.
IC
1
SDA
IC
SDA
(HIGH
)
“L”
AK4686
WRITE
AK4686
READ
SDA
·
·
SDA
AK4686
·
AK4686
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 11. Acknowledge on the I2C-bus
1-4. FIRST BYTE
1
IC
“00100”
·
IC
2
7
IC
“10”
bit= “1”
·
·
1
R/W bit= “0”
READ
0
0
1
8
WRITE
0
0
(
CAD1
CAD0
5
CAD1, CAD0 bit
IC
) R/W bit
R/W
R/W
Figure 12. The First Byte
MS1243-J-01
2010/10
- 27 -
[AK4686]
2. WRITE
R/W bit
“0”
AK4686 WRITE
2
MSB first
3
*
WRITE
2
Don’t care
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 13. The Second Byte
2
3
MSB first
8
D7
D6
D5
3
D4
D3
D2
D1
D0
Figure 14. Byte structure after the second byte
AK4686
3
·
05H
·
00H
S
T
A
R
T
SDA
Slave
Address
Register
Address(n)
S
T
Data(n+x) O
P
Data(n+1)
Data(n)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 15. WRITE Operation
MS1243-J-01
2010/10
- 28 -
[AK4686]
3. READ
R/W bit
“1”
AK4686
READ
·
0DH
AK4686
·
00H
·
·
READ
3-1.
AK4686
·
·
·
·
AK4686 READ
·
·
(READ
WRITE
“n+1”
(R/W bit = “1”)
·
)
“n”
·
·
1
1
READ
·
S
T
A
R
T
SDA
·
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 16. CURRENT ADDRESS READ
3-2.
·
·
·
(R/W bit = “1”)
·
·
WRITE
WRITE
·
READ
(R/W bit = “0”)
AK4686
·
READ
·
(R/W bit = “1”)
AK4686
·
1
·
READ
S
T
A
R
T
SDA
S
T
A
R
T
Word
Address(n)
Slave
Address
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 17. RANDOM READ
MS1243-J-01
2010/10
- 29 -
[AK4686]
■
Addr
Register Name
D7
D6
D5
D4
00H
Powerdown 1
0
0
0
0
01H
Powerdown 2
0
PWDA2 PWDA1 PWAD
02H
Audio Data Format
0
0
0
0
03H De-emphasis/ ATT speed DEM21 DEM20 DEM11 DEM10
04H
Clock Control
0
ACKS1 DFS11 DFS10
Input Selector Control &
05H
0
AMTS2 AMTS1 AMTS0
Analog mute control
D3
0
0
DIF21
0
0
D2
MT2N
ACKS2
DIF20
0
CKS12
D1
MT1N
DFS21
DIF11
0
CKS11
D0
RSTN
DFS20
DIF10
0
CKS10
AIN3
AIN2
AIN1
AIN0
:
06H∼1FH
PDN pin “L”
RSTN bit “0”
“0” bit
“0”
MS1243-J-01
2010/10
- 30 -
[AK4686]
■
Addr
00H
Register Name
Powerdown 1
R/W
Default
RSTN: Codec
0:
1:
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
MT2N
R/W
0
D1
MT1N
R/W
0
D0
RSTN
R/W
1
(default)
MT1N: DAC1
0: Mute (default)
1: Normal Output
MT2N: DAC2
0: Mute (default)
1: Normal Output
MT1N: DAC1
MT1N
Pin
L
L
H
H
MT1N
bit
0
1
0
1
DAC1Analog Mute Status
Mute
Mute
Mute
Unmute
(default)
(default)
Table 20. DAC1 Analog Mute Control
MT2N: DAC2
MT2N
Pin
L
L
H
H
MT2N
bit
0
1
0
1
DAC2 Analog Mute Status
Mute
Mute
Mute
Unmute
(default)
(default)
Table 21. DAC1 Analog Mute Control
MS1243-J-01
2010/10
- 31 -
[AK4686]
Addr
01H
Register Name
Powerdown 2
R/W
Default
D7
0
RD
0
D6
D5
PWDA2 PWDA1
R/W
R/W
1
1
DFS21-20: PORT2(DAC2)
PORT Auto Setting Mode
D4
PWAD
R/W
1
D3
0
RD
0
DFS21-20 bits
ACKS2: PORT2(DAC2)
0:
, Manual Setting Mode (default)
1:
, Auto Setting Mode
ACKS2 bit= “1”
MCLK
DFS21-20 bits
DFS21-20 bits
D2
ACKS2
R/W
0
D1
DFS21
R/W
0
D0
DFS20
R/W
0
Table 9
PORT
ACKS2 bit= “0”
MCLK
PWAD: ADC
0: Power-down
1: Normal operation (default)
PWDA1: DAC1
0: Power-down
1: Normal operation (default)
PWDA2: DAC2
0: Power-down
1: Normal operation (default)
MS1243-J-01
2010/10
- 32 -
[AK4686]
Addr
02H
Register Name
Audio Data Format
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
DIF21
R/W
1
D2
DIF20
R/W
1
D1
DIF11
R/W
1
D0
DIF10
R/W
1
D6
DEM20
R/W
1
D5
DEM11
R/W
0
D4
DEM10
R/W
1
D3
0
RD
0
D2
0
RD
0
D1
0
RD
0
D0
0
RD
0
D6
ACKS1
R/W
0
D5
DFS11
R/W
0
D4
DFS10
R/W
0
D3
0
RD
0
D2
CKS12
RW
0
D1
CKS11
R/W
0
D0
CKS10
R/W
0
DIF21-20: PORT2
Table 17
DIF11-10: PORT1
Table 16
Addr
03H
Register Name
D7
De-emphasis/ ATT speed DEM21
R/W
R/W
Default
0
DEM11-10: DAC1
DEM21-20: DAC2
Table 15
Addr
04H
Register Name
Clock Control
R/W
Default
CKS12-10: Master mode
Table 2
D7
0
RD
0
PORT1(ADC&DAC1)
DFS11-10: PORT1(ADC&DAC1)
PORT Auto Setting Mode
DFS11-10 bits
ACKS1: PORT1(ADC&DAC1)
0:
, Manual Setting Mode (default)
1:
, Auto Setting Mode
ACKS1 bit= “1”
MCLK
DFS11-10 bits
DFS11-10 bits
MS1243-J-01
Table 3
PORT
ACKS1 bit= “0”
MCLK
2010/10
- 33 -
[AK4686]
Addr
05H
Register Name
Input Selector Control &
Analog mute control
R/W
Default
D7
0
RD
0
D6
D5
D4
AMTS2 AMTS1 AMTS0
R/W
0
R/W
0
R/W
1
D3
D2
D1
D0
AIN3
AIN2
AIN1
AIN0
R/W
0
R/W
0
R/W
0
R/W
0
AIN3-0: ADC input selector control
0000: LIN1/RIN1 (default)
0001: LIN2/RIN2
0010: LIN3/RIN3
0011: LIN4/RIN4
0100: LIN5/RIN5
0101: LIN6/RIN6
1xxx: Mute (x: don’t care)
AMTS2-0: Analog Mute Clock Source Control
Default: “001”
Refer Table 18.
MS1243-J-01
2010/10
- 34 -
[AK4686]
Figure 18
(AKD4686)
Analog Ground
Digital Ground
Digital
Analog in
LIN1 37
NC 39
RIN1 38
LIN2 40
RIN2 41
NC 42
LIN3 43
RIN3 44
NC 45
LIN4 46
RIN4 47
NC 48
Micro
Controller
1 LIN5
SCL 36
2 RIN5
SDA 35
3 NC
BICK1 34
LRCK1 33
4 LIN6
SDTO 32
5 RIN6
VSS4 31
7 VSS1
DVDD 30
8 LOUT1
MT1N 29
9 ROUT1
MCLK1 28
10 LOUT2
SDTI1 27
10u
+
3.3V Digital
24 NC
23 BICK2
22 MCLK2
21 LRCK2
20 SDTI2
19 PDN
0.1u
Audio
DSP2
2.2u
18 CVDD
0.1u
17 CP
MT2N 25
16 VSS3
MS1 26
12 AVDD2
15 CN
11 ROUT2
14 CVEE
10u +
0.1u
13 VSS2
3.3V Analog
10u +
Audio
DSP1
3.3V Analog
AK4686
6 AVDD1
2.2u
0.1u
10u
+
3.3V Analog
Figure 18.
(Slave mode)
Notes:
- VSS1, VSS2, VSS3, VSS4
MS1243-J-01
2010/10
- 35 -
[AK4686]
1.
AVDD1, AVDD2, DVDD,CVDD
AVDD1, AVDD2, DVDD, CVDD
VSS1, VSS2, VSS3, VSS4
PC
DVDD
2.
AVDD1 pin
DAC1(DAC2)
ADC
AVDD1(AVDD2) pin
VSS1(VSS3) pin
0.1μF
3.
ADC
fs=48kHz)
(2
)
2.2 x AVDD1/3.3 Vrms (typ.
2’s complement
0V
DC
HPF
AK4686 64fs
64fs
AK4686 64fs
(RC
)
AK4686
Analog In
LIN1-6,
RIN1-6
2.0Vrms
Figure 19. External Circuit Example1
4.
DAC
Vrms(typ)
800000H(@24bit)
(CTF)
0V (typ)
2 x AVDD2 (AVDD3)/3.3
2’s compliment(2
)
7FFFFFH(@24bit)
000000H(@24bit)
0V
(
)
(SCF)
LSI
DC
0V(typ)
AK4686
Analog
Out
470
LOUT1/2,
ROUT1/2
2.0Vrms (typ)
Figure 20. External Circuit Example1
5.
LIN1-6, RIN1-6 pin
MS1243-J-01
2010/10
- 36 -
[AK4686]
48pin LQFP(Unit: mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
1
9.0 ± 0.2
25
12
0.09 ∼ 0.20
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
0.30 ~ 0.75
■
(
)
MS1243-J-01
2010/10
- 37 -
[AK4686]
AK4686EQ
XXXXXXX
1
1)
2)
3)
4)
Date (YY/MM/DD)
10/10/05
10/10/25
Revision
00
01
Reason
Pin #1 indication
Asahi Kasei Logo
Marking Code: AK4686EQ
Date Code: XXXXXXX (7 digits)
Page
Contents
7
DAC to Analog Output
Output Voltage: 1.85 → 1.90Vrms (min)
MS1243-J-01
2010/10
- 38 -
[AK4686]
z
z
z
z
z
z
MS1243-J-01
2010/10
- 39 -