CSD18563Q5A www.ti.com SLPS444 – JULY 2013 60-V N-Channel NexFET™ Power MOSFETs Check for Samples: CSD18563Q5A FEATURES 1 • • • • • • • • 2 PRODUCT SUMMARY Ultra Low Qg and Qgd Low Thermal Resistance Avalanche Rated Logic Level Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package TA = 25°C 60 V Qg Gate Charge Total (10V) 15.0 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage D 5.7 mΩ 2.0 V Package Media Qty Ship CSD18563Q5A SON 5-mm × 6-mm Plastic Package 13-Inch Reel 2500 Tape and Reel VALUE UNIT VDS Drain to Source Voltage 60 V VGS Gate to Source Voltage ±20 V Continuous Drain Current (Package limited), TC = 25°C 100 Continuous Drain Current (Silicon limited), TC = 25°C 91 Continuous Drain Current, TA = 25°C(1) 15 A IDM Pulsed Drain Current, TA = 25°C(2) 96 A PD Power Dissipation(1) 3.2 W S 2 7 D TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C S 3 6 D EAS Avalanche Energy, single pulse ID = 54A, L = 0.1mH, RG = 25Ω 146 mJ G 4 5 D (1) Typical RθJA = 40°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06inch thick FR4 PCB. (2) Pulse duration ≤300μs, duty cycle ≤2% D P0093-01 RDS(on) vs VGS 24 GATE CHARGE 10 TC = 25°C, I D = 18A TC = 125°C, I D = 18A 21 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) VGS = 10V Device ID Top View 18 15 12 9 6 3 0 mΩ ABSOLUTE MAXIMUM RATINGS The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications. 8 nC 8.6 TA = 25°C DESCRIPTION 1 2.9 VGS = 4.5V ORDERING INFORMATION DC-DC Conversion Secondary Side Synchronous Rectifier Motor Control S UNIT Drain to Source Voltage APPLICATIONS • • • TYPICAL VALUE VDS 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 18A VDS = 30V 9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 Qg - Gate Charge (nC) 14 16 G001 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated CSD18563Q5A SLPS444 – JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 48V IGSS Gate to Source Leakage Current VDS = 0V, VGS = 20V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250μA RDS(on) Drain to Source On Resistance gfs Transconductance 60 1.7 V 1 μA 100 nA 2.0 2.4 V VGS = 4.5V, ID = 18A 8.6 10.8 mΩ VGS = 10V, ID = 18A 5.7 6.8 mΩ VDS = 30V, ID = 18A 60 S Dynamic Characteristics Ciss Input Capacitance 1150 1500 pF Coss Output Capacitance Crss Reverse Transfer Capacitance 280 364 pF 3.9 5.1 RG pF Series Gate Resistance 1.5 3.0 Ω Qg Gate Charge Total (4.5V) 7.3 9.5 Qg Gate Charge Total (10V) 15 20 Qgd Gate Charge Gate to Drain Qgs Qg(th) Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 30V, f = 1MHz VDS = 30V, ID = 18A nC 2.9 nC Gate Charge Gate to Source 3.3 nC Gate Charge at Vth 2.3 nC 36 nC 3.2 ns VDS = 30V, VGS = 0V VDS = 30V, VGS = 10V, IDS = 18A, RG = 0Ω 6.3 ns 11.4 ns 1.7 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 18A, VGS = 0V 0.8 VDS= 30V, IF = 18A, di/dt = 300A/μs 1 V 63 nC 49 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER RθJC Thermal Resistance Junction to Case (1) RθJA Thermal Resistance Junction to Ambient (1) (2) (1) (2) 2 MIN 2 TYP MAX UNIT 1.3 °C/W 50 °C/W 2 RθJC is determined with the device mounted on a 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD18563Q5A CSD18563Q5A www.ti.com GATE SLPS444 – JULY 2013 GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick) Cu. Source Max RθJA = 125°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD18563Q5A 3 CSD18563Q5A SLPS444 – JULY 2013 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING 100 180 90 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) TEXT ADDED FOR SPACING 200 160 140 120 100 80 60 VGS =10V VGS =6V VGS =4.5V 40 20 0 0 1 2 3 4 VDS - Drain-to-Source Voltage (V) 80 70 60 50 40 30 TC = 125°C TC = 25°C TC = −55°C 20 10 0 5 VDS = 5V 0 1 Figure 2. Saturation Characteristics TEXT ADDED FOR SPACING C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) ID = 18A VDS = 30V G001 7 6 5 4 3 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 1000 100 10 2 1 0 2 4 6 8 10 12 Qg - Gate Charge (nC) 14 1 16 0 10 20 30 40 50 VDS - Drain-to-Source Voltage (V) G001 Figure 4. Gate Charge 60 G001 Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 2.6 24 RDS(on) - On-State Resistance (mΩ) ID = 250uA VGS(th) - Threshold Voltage (V) 6 TEXT ADDED FOR SPACING 20000 10000 8 0 2.4 2.2 2 1.8 1.6 1.4 1.2 1 −75 −25 25 75 125 TC - Case Temperature (ºC) Figure 6. Threshold Voltage vs. Temperature 4 5 Figure 3. Transfer Characteristics 10 9 2 3 4 VGS - Gate-to-Source Voltage (V) G001 175 TC = 25°C, I D = 18A TC = 125°C, I D = 18A 21 18 15 12 9 6 3 0 0 2 G001 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 Figure 7. On-State Resistance vs. Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD18563Q5A CSD18563Q5A www.ti.com SLPS444 – JULY 2013 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 VGS = 4.5V VGS = 10V 2.1 ISD − Source-to-Drain Current (A) Normalized On-State Resistance 2.4 1.8 1.5 1.2 0.9 0.6 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 ID =18A 0.3 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 Figure 8. Normalized On-State Resistance vs. Temperature TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1ms 10ms 1000 100ms 1s DC 100 10 1 Single Pulse Typical RthetaJA = 100ºC/W 0.01 0.01 TC = 25ºC TC = 125ºC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) G001 Figure 9. Typical Diode Forward Voltage 5000 0.1 1 0.1 1 10 VDS - Drain-to-Source Voltage (V) 100 10 0.01 0.1 TAV - Time in Avalanche (mS) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING IDS - Drain- to- Source Current (A) 120 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD18563Q5A 5 CSD18563Q5A SLPS444 – JULY 2013 www.ti.com MECHANICAL DATA 2 3 4 5 4 5 6 3 6 7 2 7 1 8 1 DIM 6 8 Q5A Package Dimensions MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 E3 3.03 3.13 3.23 e 1.17 1.27 1.37 e1 0.27 0.37 0.47 e2 0.15 0.25 0.35 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° Submit Documentation Feedback 12° Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD18563Q5A CSD18563Q5A www.ti.com SLPS444 – JULY 2013 Recommended PCB Pattern MILLIMETERS DIM MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 F1 F7 8 F3 1 F2 F11 F5 F9 5 4 F6 INCHES MIN F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Recommended Stencil Opening (0.020) 8x 0.500 (0.020) 0.500 5 4 0.500 (0.020) 8x 1.585 (0.062) 1.235 (0.049) (0.024) 0.620 (0.170) 4.310 0.385 (0.015) 1.270 (0.050) 1 8 1.570 (0.062) 4x 0.615 (0.024) 1.105 (0.044) 3.020 (0.119) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD18563Q5A 7 CSD18563Q5A SLPS444 – JULY 2013 www.ti.com K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket spacer 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD18563Q5A PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) CSD18563Q5A ACTIVE Package Type Package Pins Package Drawing Qty SON DQJ 8 2500 Eco Plan Lead/Ball Finish (2) Pb-Free (RoHS Exempt) MSL Peak Temp Op Temp (°C) Device Marking (3) CU SN Level-1-260C-UNLIM (4/5) -55 to 150 CSD18563 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. 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