TI CSD19502Q5B

CSD19502Q5B
www.ti.com
SLPS413 – DECEMBER 2013
80 V N-Channel NexFET™ Power MOSFET
Check for Samples: CSD19502Q5B
FEATURES
1
•
•
•
•
•
•
•
•
2
PRODUCT SUMMARY
Ultra-Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Logic Level
Pb-Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5-mm × 6-mm Plastic Package
TA = 25°C
UNIT
Drain-to-Source Voltage
80
V
Qg
Gate Charge Total (10 V)
48
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
8.6
nC
VGS = 6 V
3.8
mΩ
VGS = 10 V
3.4
mΩ
2.7
V
ORDERING INFORMATION
Device
Package
Media
Qty
Ship
CSD19502Q5B
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
2500
Tape and
Reel
APPLICATIONS
•
•
TYPICAL VALUE
VDS
Secondary Side Synchronous Rectifier
Motor Control
ABSOLUTE MAXIMUM RATINGS
DESCRIPTION
TA = 25°C
VALUE
UNIT
This 3.4 mΩ, 80 V, SON 5 mm × 6 mm NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
VDS
Drain-to-Source Voltage
80
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package limited)
100
Continuous Drain Current (Silicon limited),
TC = 25°C
138
ID
Top View
S
S
S
8
1
7
2
6
3
D
D
Continuous Drain Current(1)
20
IDM
Pulsed Drain Current(2)
200
A
PD
Power Dissipation(1)
3.2
W
TJ,
TSTG
Operating Junction and
Storage Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 79 A, L = 0.1 mH, RG = 25 Ω
312
mJ
D
D
G
5
4
D
(1) Typical RθJA = 40°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06inch thick FR4 PCB.
(2) Pulse duration ≤300 μs, duty cycle ≤2%
P0093-01
RDS(on) vs VGS
GATE CHARGE
10
TC = 25°C, I D = 19A
TC = 125°C, I D = 19A
18
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
20
16
14
12
10
8
6
4
2
0
0
2
4
A
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
ID = 19A
VDS = 40V
9
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
Qg - Gate Charge (nC)
40
45
50
G001
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD19502Q5B
SLPS413 – DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-Source Leakage Current
VGS = 0 V, VDS = 64 V
IGSS
Gate-to-Source Leakage Current
VDS = 0 V, VGS = 20 V
VGS(th)
Gate-to-Source Threshold Voltage
VDS = VGS, ID = 250 μA
RDS(on)
Drain-to-Source On Resistance
gfs
Transconductance
80
2.2
V
1
μA
100
nA
2.7
3.3
V
VGS = 6 V, ID = 19 A
3.8
4.8
mΩ
VGS = 10 V, ID = 19 A
3.4
4.1
mΩ
VDS = 8 V, ID = 19 A
88
S
Dynamic Characteristics
Ciss
Input Capacitance
3750
4870
pF
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
925
1202
pF
17
22
RG
Series Gate Resistance
pF
1.2
2.4
Ω
Qg
Qgd
Gate Charge Total (10 V)
48
62
nC
Gate Charge Gate to Drain
8.6
Qgs
Gate Charge Gate to Source
nC
14
nC
Qg(th)
Gate Charge at Vth
Qoss
Output Charge
td(on)
VGS = 0 V, VDS = 40 V, f = 1 MHz
VDS = 40 V, ID = 19 A
10
nC
130
nC
Turn On Delay Time
8
ns
tr
Rise Time
6
ns
td(off)
Turn Off Delay Time
22
ns
tf
Fall Time
7
ns
VDS = 40 V, VGS = 0 V
VDS = 40 V, VGS = 10 V,
IDS = 19 A, RG = 0 Ω
Diode Characteristics
VSD
Diode Forward Voltage
ISD = 19 A, VGS = 0 V
0.8
Qrr
Reverse Recovery Charge
275
nC
trr
Reverse Recovery Time
VDS= 40 V, IF = 19 A,
di/dt = 300 A/μs
1
V
72
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
MAX
UNIT
RθJC
Thermal Resistance Junction to Case (1)
PARAMETER
0.8
°C/W
RθJA
Thermal Resistance Junction to Ambient (1) (2)
50
°C/W
(1)
(2)
2
MIN
TYP
RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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CSD19502Q5B
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GATE
SLPS413 – DECEMBER 2013
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick)
Cu.
Source
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
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CSD19502Q5B
SLPS413 – DECEMBER 2013
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TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
200
180
180
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TEXT ADDED FOR SPACING
200
160
140
120
100
80
60
VGS = 10V
VGS = 8V
VGS = 6V
40
20
0
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDS - Drain-to-Source Voltage (V)
0.9
160
140
120
100
80
60
TC = 125°C
TC = 25°C
TC = −55°C
40
20
0
1
VDS = 5V
0
0.5
1
Figure 2. Saturation Characteristics
TEXT ADDED FOR SPACING
G001
ID = 19A
VDS = 40V
9
8
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
6
TEXT ADDED FOR SPACING
7
6
5
4
3
1000
100
10
2
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
0
5
10
15
20
25
30
35
Qg - Gate Charge (nC)
40
45
1
50
0
10
20
30
40
50
60
VDS - Drain-to-Source Voltage (V)
G001
70
80
G001
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
3.3
20
RDS(on) - On-State Resistance (mΩ)
ID = 250uA
VGS(th) - Threshold Voltage (V)
5.5
10000
Figure 4. Gate Charge
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
−75
−25
25
75
125
TC - Case Temperature (ºC)
Figure 6. Threshold Voltage vs. Temperature
4
5
Figure 3. Transfer Characteristics
10
0
1.5 2 2.5 3 3.5 4 4.5
VGS - Gate-to-Source Voltage (V)
G001
175
TC = 25°C, I D = 19A
TC = 125°C, I D = 19A
18
16
14
12
10
8
6
4
2
0
0
2
G001
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
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SLPS413 – DECEMBER 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
2
100
VGS = 6V
VGS = 10V
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
2.2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
−75
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
ID =19A
−25
25
75
125
TC - Case Temperature (ºC)
175
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 8. Normalized On-State Resistance vs. Temperature
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
10us
100us
1ms
10ms
DC
TC = 25ºC
TC = 125ºC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
G001
Figure 9. Typical Diode Forward Voltage
10000
1000
100
10
1
Single Pulse Width
Max RthetaJC = 0.8ºC/W
0.1
0.1
1
1
10
100
VDS - Drain-to-Source Voltage (V)
1000
10
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
IDS - Drain- to- Source Current (A)
120
100
80
60
40
20
0
−50
−25
0
25
50
75
100 125
TC - Case Temperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs. Temperature
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CSD19502Q5B
SLPS413 – DECEMBER 2013
www.ti.com
MECHANICAL DATA
Q5B Package Dimensions
K
c1
H
L
1
8
E1
b
3
D1
E
6
7
2
D2
7
2
ө
8
1
5
4
e
6
3
5
4
Top View
Side View
Bottom View
Front View
DIM
MILLIMETERS
MIN
NOM
MAX
A
0.80
1.00
1.05
b
0.36
0.41
0.46
c
0.15
0.20
0.25
c1
0.15
0.20
0.25
c2
0.20
0.25
0.30
D1
4.90
5.00
5.10
D2
4.12
4.22
4.32
d
0.20
0.25
0.30
E
4.90
5.00
5.10
E1
5.90
6.00
6.10
E2
3.48
3.58
3.68
e
0.360
0.460
0.560
L
0.46
0.56
0.66
θ
0°
–
–
K
6
1.27 TYP
H
1.40 TYP
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SLPS413 – DECEMBER 2013
Recommended PCB Pattern
(0.175)
4.440
5
(0.028)
0.710
(0.043)
1.100
C
L
4
(0.023)
0.590
1.270 (0.028)
SYM
C
L
(0.178)
4.520
1
8
0.560 (0.022)
(0.136)
3.456
0.710 (0.028)
(0.054)
(0.039)
0.984
1.372
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Recommended Stencil Pattern
(0.020)
0.508
x4
(0.011)
0.286
(0.014)
0.350
(0.022)
0.562 x 4
(0.029)
0.746 x 8
2.186 (0.086)
4.318 (0.170)
0.300
(0.012)
1.270 (0.050)
(0.030)
0.766
(0.051)
1.294
x8
(0.060)
1.525
1.270 (0.050)
(0.042)
1.072
(0.259)
6.586
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CSD19502Q5B
SLPS413 – DECEMBER 2013
www.ti.com
K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
2.00 ±0.05
+0.10
–0.00
12.00 ±0.30
Ø 1.50
1.75 ±0.10
Q5B Tape and Reel Information
5.50 ±0.05
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
R 0.30 TYP
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket
8
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD19502Q5B
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VSON
DNK
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-55 to 150
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD19502Q5B
Package Package Pins
Type Drawing
VSON
DNK
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD19502Q5B
VSON
DNK
8
2500
335.0
335.0
32.0
Pack Materials-Page 2
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