CSD13202Q2 www.ti.com SLPS313 – SEPTEMBER 2013 12V N-Channel NexFET™ Power MOSFETs Check for Samples: CSD13202Q2 FEATURES 1 • • • • • • • 2 PRODUCT SUMMARY Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 2-mm × 2-mm Plastic Package VDS Drain to Source Voltage 12 V Qg Gate Charge Total (4.5V) 5.1 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage nC 9.1 mΩ VGS = 4.5V 7.5 mΩ 0.8 V ORDERING INFORMATION Device Package Media CSD13202Q2 SON 2-mm × 2-mm Plastic Package 7-Inch Reel APPLICATIONS • • • • 0.76 VGS = 2.5V Optimized for Load Switch Applications Storage, Tablets, and Handheld Devices Optimized for Control FET Applications Point of Load Synchronous Buck Converters Qty Ship 3000 Tape and Reel ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage 12 V DESCRIPTION VGS Gate to Source Voltage ±8 V This 12V, 7.5mΩ NexFET™ power MOSFET has been designed to minimize losses in power conversion and load management applications. The SON 2 x 2 offers excellent thermal performance for the size of the package. ID Continuous Drain Current (Package Limit) 22 A 14.4 A Top View D 1 6 D 2 5 D G 3 S 4 S IDM Pulsed Drain Current, TA = 25°C(2) 76 A PD Power Dissipation(1) 2.7 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 20A, L = 0.1mH, RG = 25Ω 20 mJ (1) RθJA = 45°C/W on 1in² Cu (2 oz.) on .060" thick FR4 PCB. (2) Pulse duration 10μs, duty cycle ≤2% D D Continuous Drain Current(1) P0108-01 RDS(on) vs VGS GATE CHARGE 4.5 TC = 25°C, I D = 5A TC = 125°C, I D = 5A 16 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 18 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 VGS - Gate-to- Source Voltage (V) 7 8 G001 ID = 5A VDS =6V 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Qg - Gate Charge (nC) 4.5 5 5.5 G001 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated CSD13202Q2 SLPS313 – SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS TA = 25°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 9.6V IGSS Gate to Source Leakage Current VDS = 0V, VGS = 8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = 250μA RDS(on) gfs Drain to Source On Resistance Transconductance 12 0.58 V 1 μA 100 nA 0.80 1.10 V VGS = 2.5V, IDS = 5A 9.1 11.6 mΩ VGS = 3V, IDS = 5A 8.4 10.4 mΩ VGS = 4.5V, IDS = 5A 7.5 9.3 mΩ VDS = 6V, IDS = 5A 44 S Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance 767 997 pF 506 657 CRSS pF Reverse Transfer Capacitance 43 56 pF Rg Series Gate Resistance 0.7 1.4 Ω Qg Gate Charge Total (4.5V) 5.1 6.6 nC Qgd Gate Charge – Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 6V, f = 1MHz VDS = 6V, IDS = 5A VDS = 6V, VGS = 0V VDS = 6V, VGS = 4.5V, IDS = 5A RG = 2Ω 0.76 nC 0.98 nC 0.57 nC 5.7 nC 4.5 ns 28 ns 11.0 ns 13.6 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time IDS = 5A, VGS = 0V 0.75 VDD = 6V, IF = 5A, di/dt = 200A/μs 1 V 13 nC 28 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) MAX UNIT RθJC Thermal Resistance Junction to Case (1) PARAMETER 6.4 °C/W RθJA Thermal Resistance Junction to Ambient (1) (2) 60 °C/W (1) (2) 2 MIN TYP RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD13202Q2 CSD13202Q2 www.ti.com SLPS313 – SEPTEMBER 2013 GATE GATE Source Source N-Chan N-Chan Max RθJA = 60 when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Max RθJA = 210 when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0164-02 M0164-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance TEXT ADDED FOR SPACING 50 45 45 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) TEXT ADDED FOR SPACING 50 40 35 30 25 20 15 VGS = 4.5V VGS = 3V VGS =2.5V 10 5 0 0 0.1 0.2 0.3 0.4 0.5 VDS - Drain-to-Source Voltage (V) 0.6 VDS = 5V 40 35 30 25 20 15 TC = 125°C TC = 25°C TC = −55°C 10 5 0 0 G001 Figure 2. Saturation Characteristics 0.4 0.8 1.2 1.6 VGS - Gate-to-Source Voltage (V) 2 Product Folder Links: CSD13202Q2 G001 Figure 3. Transfer Characteristics Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated 2.4 3 CSD13202Q2 SLPS313 – SEPTEMBER 2013 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 10000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd ID = 5A VDS =6V 4 3.5 C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) 4.5 3 2.5 2 1.5 1 1000 100 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Qg - Gate Charge (nC) 4.5 5 10 5.5 0 2 G001 Figure 4. Gate Charge TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING RDS(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) G001 18 ID = 250uA 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 −75 −25 25 75 125 TC - Case Temperature (ºC) TC = 25°C, I D = 5A TC = 125°C, I D = 5A 16 14 12 10 8 6 4 2 0 175 0 1 G001 Figure 6. Threshold Voltage vs. Temperature TEXT ADDED FOR SPACING 8 G001 TEXT ADDED FOR SPACING VGS = 2.5V VGS = 4.5V ID =5A 1.3 1.2 1.1 1 0.9 0.8 0.7 −75 7 10 ISD − Source-to-Drain Current (A) 1.4 2 3 4 5 6 VGS - Gate-to- Source Voltage (V) Figure 7. On-State Resistance vs. Gate-to-Source Voltage 1.5 Normalized On-State Resistance 12 Figure 5. Capacitance 1.1 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 Figure 8. Normalized On-State Resistance vs. Temperature 4 4 6 8 10 VDS - Drain-to-Source Voltage (V) 1 G001 Figure 9. Typical Diode Forward Voltage Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD13202Q2 CSD13202Q2 www.ti.com SLPS313 – SEPTEMBER 2013 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1ms 10ms 100ms 1s DC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 0.1 Single Pulse Typical RthetaJA =165ºC/W(min Cu) 0.01 0.01 0.1 1 10 VDS - Drain-to-Source Voltage (V) 50 TC = 25ºC TC = 125ºC 10 1 0.1 0.01 0.1 1 TAV - Time in Avalanche (mS) G001 Figure 10. Maximum Safe Operating Area 10 G001 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING IDS - Drain- to- Source Current (A) 30.0 27.0 24.0 21.0 18.0 15.0 12.0 9.0 6.0 3.0 0.0 −50 −25 0 25 50 75 100 125 TA - AmbientTemperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD13202Q2 5 CSD13202Q2 SLPS313 – SEPTEMBER 2013 www.ti.com MECHANICAL DATA Q2 Package Dimensions D2 D K3 K1 K K2 4 1 2 3 4 5 6 3 2 1 K4 E E1 E2 5 E3 6 L Pin 1 Dot Top View Pin 1 ID e b D1 A A1 C Bottom View Front View M0165-01 DIM MILLIMETERS MIN NOM MAX MIN NOM MAX A 0.700 0.750 0.800 0.028 0.030 0.032 A1 0.000 0.050 0.000 b 0.250 0.350 0.010 0.300 C 0.203 TYP D 2.000 TYP D1 0.900 0.950 D2 0.300 TYP E 2.000 TYP E1 0.900 1.000 0.002 0.012 0.080 TYP 1.000 0.036 0.038 0.080 TYP 1.100 0.036 0.040 0.280 TYP 0.0112 TYP 0.470 TYP 0.0188 TYP e 0.650 BSC 0.026 TYP K 0.280 TYP 0.0112 TYP K1 0.350 TYP 0.014 TYP K2 0.200 TYP 0.008 TYP K3 0.200 TYP 0.008 TYP 0.470 TYP 0.200 0.25 0.040 0.012 TYP E3 L 0.014 0.008 TYP E2 K4 6 INCHES 0.044 0.0188 TYP 0.300 0.008 Submit Documentation Feedback 0.010 0.012 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD13202Q2 CSD13202Q2 www.ti.com SLPS313 – SEPTEMBER 2013 Recommended PCB Pattern For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Recommended Stencil Pattern Note: All dimensions are in mm, unless otherwise specified. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD13202Q2 7 CSD13202Q2 SLPS313 – SEPTEMBER 2013 www.ti.com Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ±0.20 3. Other material available 4. Typical SR of form tape Max 109 OHM/SQ 5. All dimensions are in mm, unless otherwise specified. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD13202Q2 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) CSD13202Q2 ACTIVE Package Type Package Pins Package Drawing Qty SON DQK 6 3000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. 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