SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345A – DECEMBER 2000 – REVISED JULY 2001 D D D D D SN54LV11A . . . J OR W PACKAGE SN74LV11A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1A 1B 2A 2B 2C 2Y GND 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y SN54LV11A . . . FK PACKAGE (TOP VIEW) 2A NC 2B NC 2C description These triple 3-input positive-AND gates are designed for 2-V to 5.5-V VCC operation. The ’LV11A devices perform the Boolean function Y A • B • C or Y A B C in positive logic. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y NC 3C NC 3B 2Y GND NC 3Y 3A + ) ) + 1 1B 1A NC VCC 1C D D These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. NC – No internal connection ORDERING INFORMATION –55°C to 125°C TOP-SIDE MARKING Tube SN74LV11AD Tape and reel SN74LV11ADR SOP – NS Tape and reel SN74LV11ANSR 74LV11A SSOP – DB Tape and reel SN74LV11ADBR LV11A TSSOP – PW Tape and reel SN74LV11APWR LV11A TVSOP – DGV Tape and reel SN74LV11ADGVR LV11A CDIP – J Tube SNJ54LV11AJ SNJ54LV11AJ CFP – W Tube SNJ54LV11AW SNJ54LV11AW LCCC – FK Tube SNJ54LV11AFK SNJ54LV11AFK SOIC – D –40°C 40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA LV11A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345A – DECEMBER 2000 – REVISED JULY 2001 FUNCTION TABLE (each gate) INPUTS A B C OUTPUT Y H H H H L X X L X L X L X X L L logic diagram, each gate (positive logic) A B C Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . –0.5 V to VCC + 0.5 V Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345A – DECEMBER 2000 – REVISED JULY 2001 recommended operating conditions (see Note 4) SN54LV11A VCC VIH MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V High level input voltage High-level VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 Input voltage 0 Output voltage 0 0 VCC –50 VCC × 0.3 5.5 0 VCC –50 V V V µA –2 –6 –6 –12 –12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 12 200 200 100 100 20 20 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Input transition rise or fall rate 0.5 –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC = 2 V VCC = 2.3 V to 2.7 V UNIT V 0.5 VCC × 0.3 VCC × 0.3 VI VO ∆t/∆v 5.5 VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low level output current Low-level 2 VCC × 0.7 VCC × 0.7 Low level input voltage Low-level IOL MAX 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V High level output current High-level MIN 1.5 VIL IOH SN74LV11A MIN mA µA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS IOH = –50 µA IOH = –2 mA 2 V to 5.5 V IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 MIN TYP SN74LV11A MAX MIN VCC–0.1 2 VCC–0.1 2 3V 2.48 2.48 4.5 V 3.8 2.3 V IOH = –6 mA IOH = –12 mA II ICC SN54LV11A VCC TYP MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0V 5 5 µA 3.3 V 1.9 1.9 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345A – DECEMBER 2000 – REVISED JULY 2001 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd TA = 25°C TYP MAX FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE A, B, or C Y CL = 15 pF 6.9* A, B, or C Y CL = 50 pF 9.9 MIN SN54LV11A SN74LV11A UNIT MIN MAX MIN MAX 13.8* 1* 16* 1 16 ns 17.5 1 21 1 21 ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN TYP MAX A, B, or C Y CL = 15 pF 5.2* A, B, or C Y CL = 50 pF 7.2 SN54LV11A SN74LV11A UNIT MIN MAX MIN MAX 8.8* 1* 10.5* 1 10.5 ns 12.3 1 14 1 14 ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN TYP MAX A, B, or C Y CL = 15 pF 3.9* A, B, or C Y CL = 50 pF 5.4 SN54LV11A SN74LV11A UNIT MIN MAX MIN MAX 5.9* 1* 7* 1 7 ns 7.9 1 9 1 9 ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV11A PARAMETER MIN MAX 0.2 0.8 V –0.8 V VOL(P) VOL(V) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL 0 VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3.2 High-level dynamic input voltage UNIT TYP V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 15.4 operating characteristics, TA = 25°C PARAMETER Cpd Power dissi dissipation ation ca capacitance acitance TEST CONDITIONS CL = 50 pF F, PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz 13.9 pF F SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345A – DECEMBER 2000 – REVISED JULY 2001 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPHL tPLH In-Phase Output 50% VCC tPHL Out-of-Phase Output 0V 50% VCC VOH 50% VCC VOL tPLH Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC Output Control 50% VCC 50% VCC 0V tPLZ tPZL 50% VCC tPZH 50% VCC ≈VCC VOL + 0.3 V VOL tPHZ VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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