TI SN74AUC1G80DBVR

SCES388H − MARCH 2002 − REVISED FEBRUARY 2004
D Available in the Texas Instruments
D
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 1.9 ns at 1.8 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D
CLK
GND
1
5
VCC
4
Q
2
3
YEA OR YZA PACKAGE
(BOTTOM VIEW)
GND
CLK
D
3 4
Q
2
1 5
VCC
description/ordering information
This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
NanoStar
WCSP (DSBGA) − YEA
Tape and reel
SN74AUC1G80YEAR
NanoFree
WCSP (DSBGA) − YZA (Pb-free)
Tape and reel
SN74AUC1G80YZAR
SOT (SOT-23) − DBV
Tape and reel
SN74AUC1G80DBVR
U80_
SOT (SC-70) − DCK
Tape and reel
SN74AUC1G80DCKR
UX_
_ _ _UX_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright  2004, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
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1
SCES388H − MARCH 2002 − REVISED FEBRUARY 2004
FUNCTION TABLE
INPUTS
OUTPUT
Q
CLK
D
↑
H
L
↑
L
H
L
X
Q0
logic diagram (positive logic)
CLK
CLK
Q
D
Q
D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES388H − MARCH 2002 − REVISED FEBRUARY 2004
recommended operating conditions (see Note 3)
VCC
VIH
VIL
VI
VO
Supply voltage
High-level input voltage
MIN
MAX
0.8
2.7
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
1.7
V
0
Input voltage
Output voltage
IOL
∆t/∆v
High-level output current
Low-level output current
V
0.7
0
3.6
V
0
VCC
−0.7
V
VCC = 0.8 V
VCC = 1.1 V
IOH
V
0.35 × VCC
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
Low-level input voltage
UNIT
−3
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
−5
VCC = 0.8 V
VCC = 1.1 V
0.7
mA
−8
−9
3
VCC = 1.4 V
VCC = 1.65 V
5
VCC = 2.3 V
9
mA
8
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100 µA
IOH = −0.7 mA
VOH
VOL
II
Ioff
ICC
Ci
D or CLK input
VCC
0.8 V to 2.7 V
MIN
MAX
0.55
IOH = −3 mA
IOH = −5 mA
1.1 V
0.8
1.4 V
1
IOH = −8 mA
IOH = −9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI or VO = 2.7 V
VI = VCC or GND,
VI = VCC or GND
IO = 0
UNIT
VCC−0.1
0.8 V
0.8 V
TYP†
V
0 to 2.7 V
±5
µA
0
±10
µA
10
µA
0.8 V to 2.7 V
2.5 V
2.5
pF
† All typical values are at TA = 25°C.
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SCES388H − MARCH 2002 − REVISED FEBRUARY 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 0.8 V
TYP
VCC = 1.2 V
± 0.1 V
MIN
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
200
VCC = 1.8 V
± 0.15 V
MIN
MAX
225
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
50
250
275
MHz
Pulse duration, CLK high or low
4.6
1.7
1.7
1.7
1.7
ns
tsu
Setup time before CLK↑, Data high or low
1.6
1.1
0.8
0.6
0.5
ns
th
Hold time, data after CLK↑
0
0
0.1
0.1
0.1
ns
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 0.8 V
TO
(OUTPUT)
TYP
MIN
50
200
5
1
fmax
tpd
CLK
VCC = 1.2 V
± 0.1 V
Q
VCC = 1.5 V
± 0.1 V
MAX
MIN
VCC = 1.8 V
± 0.15 V
MAX
MIN
225
3.9
0.8
TYP
VCC = 2.5 V
± 0.2 V
MAX
250
2.5
MIN
275
0.3
1
1.9
UNIT
MAX
MHz
0.3
1.3
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
MIN
fmax
tpd
TYP
VCC = 2.5 V
± 0.2 V
MAX
250
CLK
0.8
Q
MIN
275
1.5
2.4
UNIT
MAX
0.6
ns
1.8
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
Power dissipation
capacitance
TEST
CONDITIONS
f = 10 MHz
VCC = 0.8 V
TYP
18
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VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
18
• DALLAS, TEXAS 75265
18
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
18.5
20.5
pF
SCES388H − MARCH 2002 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
VCC/2
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
tPLH
tPHL
VCC
Output
Control
VCC/2
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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5
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
5
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-2/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
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