NCP5369 Integrated Driver and MOSFET The NCP5369 integrates a MOSFET driver, high−side MOSFET and low−side MOSFET into a 6 mm x 6 mm 40−pin QFN package. The driver and MOSFETs have been optimized for high−current DC−DC buck power conversion applications. The NCP5369 integrated solution greatly reduces package parasitics and board space compared to a discrete component solution. http://onsemi.com MARKING DIAGRAM Features • • • • • • • 1 Capable of Switching Frequencies Up to 1 MHz Capable of Output Currents Up to 35 A Internal Bootstrap Diode Zero Current Detection Undervoltage Lockout Internal Thermal Warning / Thermal Shutdown These are Pb−Free Devices 5V 5V NCP5369 AWLYYWWG 1 40 QFN40 MN SUFFIX CASE 485AZ A WL YY WW G 12−20 V = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Thermal Warning VCIN Output Disable Device BOOT ZCD_EN# ZCD Enable ORDERING INFORMATION VIN THWN VSWH Vout PWM PWM CGND PGND April, 2013 − Rev. 4 QFN40 2500/Tape & Reel (Pb−Free) NCP5369MNTWG QFN40 2500/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Figure 1. Application Schematic © Semiconductor Components Industries, LLC, 2013 Shipping† NCP5369MNR2G PHASE DISB# Package 1 Publication Order Number: NCP5369/D NCP5369 BOOT VCIN GH VIN 3.4 V 97k PWM PHASE 187k Logic VSWH ZCD_EN# Anti−Cross Conduction VCIN PGND DISB# UVLO THWN/THDN THWN GL BOOT NC VCIN ZCD_EN# 4 2 1 3 GH CGND 5 PHASE 6 THWN 14 37 CGND VSWH 15 36 GL PGND 16 35 VSWH PGND 17 34 VSWH PGND 18 33 VSWH PGND 19 32 VSWH PGND 20 31 VSWH PGND 28 VSWH 29 VSWH 30 VSWH FLAG43 PGND 27 VIN 7 DISB# 38 PGND 25 PGND 26 13 VIN NC PWM 39 CGND FLAG41 PGND 24 VIN 8 40 VIN FLAG42 PGND 23 12 PGND 22 11 VIN PGND 21 VIN 9 10 VIN Figure 2. Simplified Block Diagram Figure 3. Pin Connections (Top View) http://onsemi.com 2 NCP5369 Table 1. PIN FUNCTION DESCRIPTION Pin No. Pin Name 1 ZCD_EN# 2 VCIN 3, 8 NC 4 BOOT Bootstrap Voltage 5, 37, FLAG 41 CGND Control Signal Ground 6 GH 7 PHASE Description Enable Zero Current Detection Control Input Voltage No Connect High Side FET Gate Access Provides a return path for the high side driver of the internal IC. Place a high frequency ceramic capacitor of 0.1 uF to 1.0 uF from this pin to BOOT pin. 9−14, FLAG 42 VIN 15, 29−35, FLAG 43 VSWH Input Voltage Switch Node Output 16−28 PGND Power Ground 36 GL 38 THWN Low Side FET Gate Access Thermal Warning 39 DISB# Output Disable Pin 40 PWM PWM Drive Logic Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Pin Name / Rating Min Max Unit VCIN Control Input Voltage −0.3 7 V VIN Power Input Voltage −0.3 30 V −0.3 V wrt/VSWH 35 V wrt/PGND 40 V < 50 ns wrt/PGND 7 V wrt/VSWH V −5 V −10 V < 200 ns 35 V 40 V < 50 ns V BOOT Bootstrap Voltage VSWH Switch Node Output ZCD_EN# Zero Current Detection −0.3 6.5 V PWM PWM Drive Logic −0.3 6.5 V DISB# Output Disable −0.3 6.5 V THWN Thermal Warning −0.3 6.5 V TJ Junction Temperature −55 to 150 °C TS Storage Temperature −55 to 150 °C RqJPCB Thermal Resistance, High−Side FET 13 °C/W RqJPCB Thermal Resistance, Low−Side FET 5 °C/W Moisture Sensitivity Level 3 MSL Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. OPERATING RANGES Rating Control Input Voltage Input Voltage http://onsemi.com 3 Symbol Min Typ Max Unit VCIN VIN 4.5 5 5.5 V 4.5 12 25 V NCP5369 ELECTRICAL CHARACTERISTICS (Note 1) (VCIN = 5 V, VIN = 12 V, TA = −10°C to +100°C, unless otherwise noted) Parameter Symbol Condition VCIN Current (normal mode) − VCIN Current (shutdown mode) − Min Typ Max Unit DISB# = 5 V, PWM = OSC, FSW = 400 kHz 14 20 mA DISB# = GND 15 30 mA SUPPLY CURRENT UNDERVOLTAGE LOCKOUT UVLO Startup − 3.8 4.35 4.5 V UVLO Hysteresis − 150 200 250 mV 0.1 0.4 0.6 V VPWM_HI 3.6 − − V PWM Input Voltage Mid−State VPWM_MID 1.3 − 3.0 V PWM Input Voltage Low VPWM_LO − − 0.7 V BOOTSTRAP DIODE Forward Voltage − VCIN = 5 V, forward bias current = 2 mA PWM INPUT PWM Input Voltage High Tri−State Shutdown Holdoff Time tholdoff 250 ns PWM Input Resistance 63 kW PWM Input Bias Voltage 2.2 V OUTPUT DISABLE Output Disable Input Voltage High VDISB#_HI 2.0 − − V Output Disable Input Voltage Low VDISB#_LO − − 0.8 V − − 500 − mV − 20 40 ns Output Disable Hysteresis Output Disable Propagation Delay ZERO CROSS DETECT Zero Cross Detect High VZCD_EN#_HI 2.0 − − V Zero Cross Detect Low VZCD_EN#_LO − − 0.8 V Zero Cross Detect Threshold −6 mV ZCD Blanking Timer 250 ns Thermal Warning Temperature 150 °C Thermal Warning Hysteresis 15 °C Thermal Shutdown Temperature 180 °C Thermal Shutdown Hysteresis 25 °C THERMAL WARNING/SHUTDOWN 1. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. http://onsemi.com 4 NCP5369 APPLICATIONS INFORMATION Theory of Operation The NCP5369 prevents cross conduction by monitoring the status of the MOSFETs and applying the appropriate amount of “dead−time” or the time between the turn off of one MOSFET and the turn on of the other MOSFET. When the PWM input pin goes high, the gate of the low−side MOSFET (GL pin) will go low after a propagation delay (tpdlGL). The time it takes for the low−side MOSFET to turn off (tfGL) is dependent on the total charge on the low−side MOSFET gate. The NCP5369 monitors the gate voltage of both MOSFETs and the switchnode voltage to determine the conduction status of the MOSFETs. Once the low−side MOSFET is turned off an internal timer will delay (tpdhGH) the turn on of the high−side MOSFET. Likewise, when the PWM input pin goes low, the gate of the high−side MOSFET (GH pin) will go low after the propagation delay (tpdlGH). The time to turn off the high−side MOSFET (tfGH) is dependent on the total gate charge of the high−side MOSFET. A timer will be triggered once the high−side MOSFET has stopped conducting, to delay (tpdhGL) the turn on of the low−side MOSFET. The NCP5369 is an integrated driver and MOSFET module designed for use in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high−side and low−side MOSFETs. Low−Side Driver The low−side driver is designed to drive a ground−referenced low RDS(on) N−Channel MOSFET. The voltage rail for the low−side driver is internally connected to VCIN and PGND. High−Side Driver The high−side driver is designed to drive a floating low RDS(on) N−channel MOSFET. The gate voltage for the high side driver is developed by a bootstrap circuit referenced to Switch Node (VSWH) pin. The bootstrap circuit is comprised of the internal diode and an external bootstrap capacitor. When the NCP5369 is starting up, the VSWH pin is at ground, so the bootstrap capacitor will charge up to VCIN through the bootstrap diode See Figure 1. When the PWM input goes high, the high−side driver will begin to turn on the high−side MOSFET using the stored charge of the bootstrap capacitor. As the high−side MOSFET turns on, the VSWH pin will rise. When the high−side MOSFET is fully on, the switch node will be at 12 V, and the BST pin will be at 5 V plus the charge of the bootstrap capacitor (approaching 17 V). The bootstrap capacitor is recharged when the switch node goes low during the next cycle. Thermal Warning / Thermal Shutdown When the temperature of the driver reaches 150°C, the THWN pin will be pulled low indicating a thermal warning. At this point, the part continues to function normally. When the temperature drops below 135°C, the THWN will go high. If the driver temperature exceeds 180°C, the part will enter thermal shutdown and turn off both MOSFETs. Once the temperature falls below 155°C, the part will resume normal operation. The THWN pin has a maximum current capability of 30 mA. Zero Current Detect When ZCD_EN# is set high, the NCP5369 will operate in normal PWM mode. When ZCD_EN# is set low, zero current detect (ZCD) will be enabled. If PWM goes high, GH will go high after the non−overlap delay. If PWM goes low, GL will go high after the non−overlap delay, and stay high for the duration of the ZCD blanking timer. Once this timer has expired, VSWH will be monitored for zero current detection, and will pull GL low once detected. The threshold on VSWH to determine zero current undergoes an auto-calibration cycle every time DISB# is brought from low to high. This auto-calibration cycle typically takes 55 ms to complete. Power Supply Decoupling The NCP5369 can source and sink relatively large current to the gate pins of the MOSFETs. In order to maintain a constant and stable supply voltage (VCIN) a low ESR capacitor should be placed near the power and ground pins. A 1 mF to 4.7 mF multi layer ceramic capacitor (MLCC) is usually sufficient. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBST) and the internal diode. The bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. A minimum 50 V rating is recommended. A bootstrap capacitance greater than 100 nF and a minimum 50 V rating is recommended. A good quality ceramic capacitor should be used. Safety Timer and Overlap Protection Circuit It is very important that MOSFETs in a synchronous buck regulator do not both conduct at the same time. Excessive shoot−through or cross conduction can damage the MOSFETs, and even a small amount of cross conduction will cause a decrease in the power conversion efficiency. http://onsemi.com 5 NCP5369 ZCD_EN# PWM GH GL IL Figure 4. Zero Current Detection PWM GH GL tholdoff tholdoff Figure 5. Tri−State Operation http://onsemi.com 6 tholdoff NCP5369 PACKAGE DIMENSIONS QFN40 6x6, 0.5P MN SUFFIX CASE 485AZ−01 ISSUE O A B D ÉÉÉ ÉÉÉ ÉÉÉ PIN ONE LOCATION 2X L1 DETAIL A E ALTERNATE CONSTRUCTIONS EXPOSED Cu TOP VIEW 0.15 C (A3) DETAIL B 0.10 C DIM A A1 A3 b D D2 D3 E E2 E3 e G K L L1 MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION A 43X SIDE VIEW A1 0.08 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. POSITIONAL TOLERANCE APPLIES TO ALL THREE EXPOSED PADS. ÉÉÉ ÉÉÉ 0.15 C 2X L L SEATING PLANE C NOTE 4 0.10 C A B D3 D2 NOTE 5 G DETAIL A 40X L MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 6.00 BSC 2.30 2.50 1.40 1.60 6.00 BSC 4.30 4.50 1.90 2.10 0.50 BSC 2.20 BSC 0.20 −−− 0.30 0.50 −−− 0.15 SOLDERING FOOTPRINT 6.30 E3 4.56 E2 1.66 E3 1 40 K G 1 G e 40X e/2 BOTTOM VIEW b 0.10 C A B 0.05 C 40X 0.63 2.56 2.16 4.56 NOTE 3 6.30 2.16 PKG OUTLINE 0.50 PITCH 40X 0.30 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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