Integrated Driver and MOSFET

NCP5366
Integrated Driver and
MOSFET
The NCP5366 integrates a MOSFET driver, high-side MOSFET
and low-side MOSFET into a 6mm x 6mm 40-pin QFN package. The
driver and MOSFETs have been optimized for high-current DC-DC
buck power conversion applications. The NCP5366 integrated
solution greatly reduces package parasitics and board space compared
to a discrete component solution.
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MARKING
DIAGRAM
Features
•
•
•
•
•
•
•
•
1
Capable of Switching Frequencies up to 1 MHz
Capable of Output Currents up to 40 A
Integrated Bootstrap Diode
Output Disable Control turns off both MOSFETs
Anti Cross-Conduction Protection Circuitry
Undervoltage Lockout
Internal Thermal Shutdown for System Protection
These are Pb-free Devices
NCP5366
AWLYYWWG
1 40
QFN40
MN SUFFIX
CASE 485AZ
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
+12V
VCIN
ORDERING INFORMATION
VIN
Device
BST
NCP5366MNR2G
Output
Disable
DISB#
PWM
PWM
CGND
VSWH
Vout
PGND
Package
Shipping†
QFN40
2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2010
June, 2010 − Rev. 0
1
Publication Order Number:
NCP5366/D
NCP5366
BOOT
GH
VIN
VCIN
PWM
Logic
VSWH
Anti−Cross
Conduction
VCIN
PGND
DISB#
Fault
UVLO
Pre−OV
TSD
GL
Figure 2. Simplified Block Diagram
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2
NCP5366
PIN CONNECTIONS
PHASE
GH
CGND
BOOT
VCIN
NC
NC
9
8
7
6
5
4
3
2
1
13
NC
VIN
VIN
12
10
11
VIN
VIN
VIN
VIN
FLAG 42
CGND
FLAG 41
40
PWM
39
DISB#
38
NC
VIN
14
37
CGND
VSWH
15
36
GL
PGND
16
35
VSWH
PGND
17
34
VSWH
PGND
18
33
VSWH
PGND
19
32
VSWH
PGND
20
31
VSWH
VSWH
FLAG 43
23
24
25
26
27
28
29
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VSWH
VSWH
22
PGND
30
21
Figure 3. Pin Connections
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1, 2, 8, 38
NC
3
VCIN
No Connect
Control Input Voltage
4
BOOT
Bootstrap Voltage Pin
5, 37, Flag 41
CGND
Control Signal Ground
6
GH
7
PHASE
9−14, Flag 42
VIN
15, 29−35, Flag 43
VSWH
Switch Node Output
16−28
PGND
Power Ground
High Side FET Gate Access Pin
Provides a return path for the high side driver of the internal IC. Place a high frequency
ceramic capacitor of 0.1 mF from this pin to BOOT pin.
Input Voltage
36
GL
39
DISB#
Low Side FET Gate Access Pin
Output Disable Pin
40
PWM
PWM Drive Logic
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NCP5366
Table 2. ABSOLUTE MAXIMUM RATINGS
Pin Symbol
Pin Name
Min
Max
VCIN
Control Input Voltage
−0.3 V
15 V
VIN
Power Input Voltage
−0.3 V
30 V
−0.3 V wrt/VSWH
35 V wrt/PGND
40 V < 50 ns wrt/PGND
15 V wrt/VSWH
−5 V
−10 V < 200 ns
30 V
BOOT
Bootstrap Voltage
VSWH
Switch Node Output
PWM
PWM Drive Logic
−0.3 V
6.5 V
DISB#
Output Disable
−0.3 V
6.5 V
PGND
Ground
0V
0V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Resistance, High−Side FET
RqJPCB
13
°C/W
Thermal Resistance, Low−Side FET
RqJPCB
5.0
°C/W
Operating Junction Temperature
TJ
0 to 150
°C
Storage Temperature
TS
−55 to 150
°C
MSL
3
Moisture Sensitivity Level
1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
Table 4. OPERATING RANGES (Note 2)
Rating
Control Input Voltage
Input Voltage
Symbol
Min
Typ
Max
Unit
VCIN
4.5
12
13.2
V
VIN
4.5
12
25
V
2. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
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NCP5366
ELECTRICAL CHARACTERISTICS (Notes 3, 4) (VCIN = 12 V, VIN = 12 V, TA = −10°C to +100°C, unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
50
mA
0.5
1.7
mA
SUPPLY CURRENT
VCIN Current (Normal Mode)
−
DISB# = 5 V, PWM = OSC, Fsw = 400 kHz
VCIN Current (Shutdown Mode)
−
DISB# = GND
UNDERVOLTAGE LOCKOUT
UVLO Startup
−
3.8
4.35
4.5
V
UVLO Hysteresis
−
150
200
250
mV
0.1
0.4
0.6
V
BOOTSTRAP DIODE
Bootstrap Diode Forward Voltage
−
VCIN = 12 V, Forward Bias Current = 2 mA
PWM INPUT
VPWM_HI
3.3
PWM Input Voltage Mid−State
VPWM_MID
1.3
PWM Input Voltage Low
VPWM_LO
PWM Input Voltage High
Tri−State Shutdown Holdoff Time
V
2.7
0.7
−
200
V
V
ns
OUTPUT DISABLE
Output Disable Input Voltage High
VDISB_HI
Output Disable Input Voltage Low
VDISB_LO
Output Disable Hysteresis
2.0
V
1.0
−
500
Output Disable Propagation Delay
20
V
mV
40
ns
3. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25_C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
PWM
GH−VSWH
GL
Figure 4. Timing Diagram
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NCP5366
APPLICATION INFORMATION
Theory of Operation
MOSFETs, and even a small amount of cross−conduction
will cause a decrease in the power conversion efficiency.
The NCP5366 prevents cross conduction by monitoring
the status of the MOSFETs and applying the appropriate
amount of “dead−time” or the time between the turn off of
one MOSFET and the turn on of the other MOSFET.
When the PWM input pin goes high, the gate of the
low-side MOSFET (GL pin) will go low after a propagation
delay (tpdlGL). The time it takes for the low−side MOSFET
to turn off (tfGL) is dependent on the total charge on the
low−side MOSFET gate. The NCP5366 monitors the gate
voltage of both MOSFETs and the switchnode voltage to
determine the conduction status of the MOSFETs. Once the
low−side MOSFET is turned off an internal timer will delay
(tpdhGH) the turn on of the high−side MOSFET.
Likewise, when the PWM input pin goes low, the gate of
the high-side MOSFET (GH pin) will go low after the
propagation delay (tpdlGH). The time to turn off the
high−side MOSFET (tfGH) is dependent on the total gate
charge of the high−side MOSFET. A timer will be triggered
once the high−side MOSFET has stopped conducting, to
delay (tpdhGL) the turn on of the low−side MOSFET.
When the PWM input is between VPWM_LO and
VPWM_HI for longer than 200 ns, both the high-side and
low-side MOSFETs will be turned off. The PWM input will
need to exceed VPWM_HI to resume normal switching of the
MOSFETs.
The NCP5366 is an integrated driver and MOSFET
module designed for use in a synchronous buck converter
topology. A single PWM input signal is all that is required
to properly drive the high−side and low−side MOSFETs.
Undervoltage Lockout
GH and GL are held low until VCIN reaches 4.5 V during
startup. The PWM signals will control the gate status when
the VCIN threshold is exceeded.
Power-On Reset
Power-On Reset feature is used to protect against an
abnormal status during startup. When the initial soft-start
voltage is greater than 2.75 V, the switch node pin is
monitored. If VSWH is higher than 2.25 V, the low-side FET
is turned on to discharge the output capacitors. The fault
mode will latch and DISB# will be forced low until the part
is recycled. When the input voltage is higher than 4.5 V and
DISB# is high, the part will enter normal operation.
Bi-Directional DISB# Signal
Fault modes such as Power-On Reset, Overtemperature
and Undervoltage Lockout will assert the DISB# pin. This
will pull down the DRON of the controller as well, thus
shutting the controller down.
Low−Side Driver
The low−side driver is designed to drive a ground
referenced low RDS(on) N−Channel MOSFET. The voltage
rail for the low−side driver is internally connected to VCIN
and CGND.
Power Supply Decoupling
The NCP5366 can source and sink relatively large
currents to the gate pins of the MOSFETs. In order to
maintain a constant and stable supply voltage (VCIN) a low
ESR capacitor should be placed near the power and ground
pins. A 1 mF to 4.7 mF multi layer ceramic capacitor (MLCC)
is usually sufficient.
High−Side Driver
The high−side driver is designed to drive a floating low
RDS(on) N−channel MOSFET. The gate voltage for the
high-side driver is developed by a bootstrap circuit
referenced to Switch Node (VSWH) pin.
The bootstrap circuit is comprised of the internal
bootstrap diode, and an external bootstrap capacitor. When
the NCP5366 is starting up, the VSWH pin is at ground, so
the bootstrap capacitor will charge up to VCIN through the
bootstrap diode. When the PWM input goes high, the
high−side driver will begin to turn on the high−side
MOSFET using the stored charge of the bootstrap capacitor.
As the high−side MOSFET turns on, the VSWH pin will
rise. When the high−side MOSFET is fully on, the switch
node will be at 12 V, and the BST pin will be at 12 V plus the
charge of the bootstrap capacitor (approaching 24 V).
The bootstrap capacitor is recharged when the switch
node goes low during the next cycle.
Input Pins
The PWM input and the Output Disable pins of the
NCP5366 have internal protection for Electro Static
Discharge (ESD), but in normal operation they present a
relatively high input impedance. If the PWM controller does
not have internal pull−down resistors, they should be added
externally to ensure that the driver outputs do not go high
before the controller has reached its undervoltage lockout
threshold.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBST) and the internal diode. The bootstrap capacitor must
have a voltage rating that is able to withstand twice the
maximum supply voltage. A minimum 50 V rating is
recommended. A bootstrap capacitance greater than 100 nF
is recommended. A good quality ceramic capacitor should
be used.
Safety Timer and Overlap Protection Circuit
It is very important that MOSFETs in a synchronous buck
regulator do not both conduct at the same time. Excessive
shoot−through or cross−conduction can damage the
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NCP5366
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
MN SUFFIX
CASE 485AZ−01
ISSUE O
A B
D
ÉÉÉ
ÉÉÉ
ÉÉÉ
PIN ONE
LOCATION
2X
L1
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
EXPOSED Cu
TOP VIEW
0.15 C
(A3)
DETAIL B
0.10 C
DIM
A
A1
A3
b
D
D2
D3
E
E2
E3
e
G
K
L
L1
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
A
43X
SIDE VIEW A1
0.08 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. POSITIONAL TOLERANCE APPLIES TO ALL
THREE EXPOSED PADS.
ÉÉÉ
ÉÉÉ
0.15 C
2X
L
L
C
NOTE 4
SEATING
PLANE
0.10 C A B
D3
D2
NOTE 5
G
DETAIL A
40X
L
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.18
0.30
6.00 BSC
2.30
2.50
1.40
1.60
6.00 BSC
4.30
4.50
1.90
2.10
0.50 BSC
2.20 BSC
0.20
−−−
0.30
0.50
−−−
0.15
SOLDERING FOOTPRINT
6.30
E3
4.56
E2
1.66
E3
1
40
K
G
1
G
e
40X
e/2
BOTTOM VIEW
b
0.10 C A B
0.05 C
40X
0.63
2.56
2.16
4.56
NOTE 3
6.30
2.16
PKG
OUTLINE
0.50
PITCH
40X
0.30
DIMENSIONS: MILLIMETERS
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
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NCP5366/D