NCP5339 D

NCP5339
Integrated Driver &
MOSFETs
The NCP5339 integrates a MOSFET driver, high−side MOSFET
and low−side MOSFET into a 6 mm x 6 mm 40−pin QFN package.
The driver and MOSFETs have been optimized for high−current
DC−DC buck power conversion applications. The NCP5339
integrated solution greatly reduce package parasitics and board space
compared to a discrete component solution.
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MARKING
DIAGRAM
Features
•
•
•
•
•
•
•
•
3−State 5 V PWM Logic
Capable of Switching Frequencies up to 1 MHz
Zero Current Detection for Improving Light Load Efficiency
Internal Bootstrap Schottky Diode
Undervoltage Lockout of VCIN
Disable Pin Disables Both Driver Outputs
Internal Thermal Warning / Thermal Shutdown Functionality
These are Pb−free Devices
1
1 40
NCP5339
A
WL
YY
WW
G
Typical Applications
• Servers and Desktops
• Graphics Cards
• Telecom
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Vin
4.5 V to 16 V
5V
THWN
VIN
VCIN
Device
Package
Shipping†
NCP5339MNTXG
QFN−40
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Thermal
Warning
5V
NCP5339
AWLYYWWG
QFN40 6x6, 0.5P
CASE 485CM
BOOT
PHASE
ZCD Enable
Output
Disable
PWM
ZCD_EN#
DISB#
Vout
VSWH
PWM
CGND
PGND
Figure 1. Application Schematic
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 1
1
Publication Order Number:
NCP5339/D
NCP5339
BOOT
GH
VIN
VCIN
3.4 V
145 kW
PHASE
45 kW
PWM
129 kW
Logic
Anti−Cross−
Conduction
Circuitry
Clip
Connection
VSWH
45 kW
VCIN
VCIN
300 kW
ZCD_EN#
45 kW
PGND
VCIN UVLO
DISB#
Thermal
Shutdown
THWN
Temperature
Sense
CGND
Figure 2. Simplified Block Diagram
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2
GL
NCP5339
PHASE
GH
CGND
BOOT
NC
VCIN
ZCD_EN#
8
7
6
5
4
3
2
1
VIN
VIN
13
9
VIN
10
12
VIN
11
VIN
VIN
VIN
40
PWM
39
DISB#
38
THWN
14
37
CGND
VSWH
15
36
GL
PGND
16
35
VSWH
PGND
17
34
VSWH
PGND
18
33
VSWH
PGND
19
32
VSWH
PGND
20
31
VSWH
CGND
FLAG 41
VIN
FLAG 42
VSWH
FLAG 43
23
24
25
26
27
28
29
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VSWH
VSWH
22
30
21
(Top View)
Figure 3. Pin Connections
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
ZCD_EN#
Enable Zero Current Detection. When the voltage on this pin is low, the NCP5339 will enter zero
current detection mode. Otherwise, the NCP5339 will be in PWM mode. There is a 300 kW pull−
up resistor to VCIN.
2
VCIN
3
NC
4
BOOT
Bootstrap Voltage. This provides power to the GH driver. Place a high frequency ceramic capacitor of 0.1 mF to 1.0 mF from this pin to PHASE.
5, 37, FLAG 41
CGND
Control Signal Ground
6
GH
7
PHASE
8−14, FLAG 42
VIN
15, 29−35, FLAG 43
VSWH
Switch Node Output
16−28
PGND
Power Ground
36
GL
38
THWN
Thermal warning indicator. This is an open−drain output. When the temperature at the driver die
reaches TTHWN, this pin is pulled low. Driver operation is not disabled until the driver die temperature reaches TTHDN. Driver operation is resumed once the driver die temperature falls below
the TTHDN hysteresis level.
39
DISB#
Output Disable Pin. When the voltage on this pin is low, GH and GL is pulled low.
40
PWM
PWM Drive Logic. This is a 3−state input:
PWM = High ³ GH is high, GL is low.
PWM = Mid ³
GH is low, GL goes low after tholdoff.
PWM = Low ³ GH is low, GL is high (ZCD_EN# = High).
GH is low, GL is high for tblank and then goes low when zero current
is detected (ZCD_EN# = Low).
There are internal PWM resistors that bias this pin to 2.2 V (mid−state) if the pin is left floating.
Control Input Voltage. Provides power to the driver IC logic and power to the GL driver.
No Connect. There is no connection to any IC die.
High−Side FET Gate Access
Connection to the source of the high−side MOSFET. Place a high frequency ceramic capacitor
of 0.1 mF to 1.0 mF from this pin to BOOT pin.
Input Voltage
Low−Side FET Gate Access
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NCP5339
Table 2. ABSOLUTE MAXIMUM RATINGS (All Signals Referenced to CGND unless noted otherwise)
Pin Name
Min
Max
Unit
Control Input Voltage
−0.3
6.5
V
Power Input Voltage (Note 1)
−0.3
25 to PGND
V
−0.3 to VSWH
35
40 (< 50 ns)
6.5 to VSWH
V
Pin Symbol
VCIN
VIN
BOOT
Bootstrap Voltage
VSWH
Switch Node Output (Note 1)
−0.3 to PGND
−5 to PGND (< 10 ns)
25 to PGND
30 to PGND (< 10 ns)
V
GH
High−Side FET Gate Access
−0.3 to VSWH
6.5 to VSWH
V
GL
Low−Side FET Gate Access
−0.3
6.5
V
Zero Current Detection
−0.3
6.5
V
PWM
PWM Drive Logic
−0.3
6.5
V
DISB#
Output Disable
−0.3
6.5
V
THWN
Thermal Warning
ZCD_EN#
−0.3
6.5
V
Continuous Output
Current
Output Current, Fsw = 300 kHz, VIN = 12 V,
VOUT = 1.2 V (Note 2)
−
50
A
Peak Output
Current (Note 3)
Output Current, Fsw = 300 kHz, VIN = 12 V,
VOUT = 1.2 V (Note 2)
−
80
A
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. During switching of the MOSFETs, high transient voltages can appear on these pins. It is important to keep these transients within the
Maximum Ratings range.
2. Output current ratings are based on using a 3.0″ x 3.0″ PCB, 8 layers, board design, TA = 25°C, natural convection.
3. Peak output current is applied for 10 ms.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
Table 3. THERMAL CHARACTERISTICS
Symbol
Value
Unit
Thermal Resistance, Junction−to−Ambient (Note 4)
Parameter
qJA
24.6
°C/W
Thermal Characterization Parameter, Junction−to−Board (Note 4)
yJB
0.3
°C/W
Thermal Characterization Parameter, Junction−to−Top (Note 4)
yJC
0.5
°C/W
Operating Junction Temperature Range
TJ
−40 to 150
°C
Storage Temperature Range
TS
−55 to 150
°C
MSL
3
Moisture Sensitivity Level
4. JESD51−7 board (2s2p, 1 oz. Cu thickness), 0 LFM.
Table 4. OPERATING RANGES
Rating
Control Input Voltage
Input Voltage
Symbol
Min
Typ
Max
Unit
VCIN
4.5
5
5.5
V
VIN
4.5
12
16
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCP5339
Table 5. ELECTRICAL CHARACTERISTICS
(VCIN = 5 V, VIN = 12 V, TA = −40°C to +125°C, unless otherwise noted.)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
SUPPLY CURRENT
VCIN Current (normal mode)
−
DISB# = 5 V, PWM = switching
(0 V to 5 V), FSW = 400 kHz
−
18
30
mA
VCIN Current (shutdown mode)
−
DISB# = GND, ZCD_EN# = VCIN
−
1
−
mA
VCIN rising
3.8
4.35
4.5
V
UVLO rising threshold – UVLO falling
threshold
150
200
250
mV
Forward bias current = 2 mA
0.1
0.3
0.6
V
VPWM_HI
3.7
−
−
V
PWM Input Voltage Mid−State
VPWM_MID
1.3
−
3.0
V
PWM Input Voltage Low
VPWM_LO
−
−
0.7
V
UNDERVOLTAGE LOCKOUT (VCIN)
UVLO Rising
UVLO Hysteresis
VUVLO
HYSUVLO
BOOTSTRAP DIODE
Forward Voltage
−
PWM INPUT
PWM Input Voltage High
Tri−State Shutdown Holdoff Time
tholdoff
300
ns
PWM Input Resistance
−
68
kW
PWM Input Bias Voltage
−
2.2
V
OUTPUT DISABLE
Output Disable Input Voltage High
VDISB#_HI
2.0
−
−
V
Output Disable Input Voltage Low
VDISB#_LO
−
−
0.8
V
Output Disable Hysteresis
HYSDISB#
VDISB#_HI – VDISB#_LO
−
300
−
mV
Enable Delay Time (Note 5)
−
DISB# rising, PWM = 0 V,
GL rising to 10%
−
25
−
ms
Output Disable Propagation Delay
−
DISB# falling, PWM = 0 V, GL
falling to 90%
−
20
40
ns
ZERO CROSS DETECT
Zero Cross Detect High
VZCD_EN#_HI
2.0
−
−
V
Zero Cross Detect Low
VZCD_EN#_LO
−
−
0.8
V
−
−3
−
mV
−
350
−
ns
−
150
−
°C
−
15
−
°C
−
180
−
°C
−
25
−
°C
Zero Cross Detect Threshold
ZCD Blanking + Debounce Timer
−
ZCD_EN# = 0 V
tblank
THERMAL WARNING/SHUTDOWN
Thermal Warning Temperature (Note 5)
Thermal Warning Hysteresis (Note 5)
Thermal Shutdown Temperature (Note 5)
Thermal Shutdown Hysteresis (Note 5)
TTHWN
Temperature at driver IC
HYSTHWN
TTHSD
Temperature at driver IC
HYSTHSD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Guaranteed by design and/or characterization. This parameter is not tested in production.
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5
NCP5339
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
5
MODULE POWER LOSS (W)
MODULE EFFICIENCY (%)
TYPICAL CHARACTERISTICS
5
10
15
20
25
1
0
5
10
15
20
25
30
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 4. Module Efficiency vs. Current (Vin =
12 V, Vout = 1.2 V, Natural Air Convection,
Inductor = 0.15 mH, Output measured at VSW)
Figure 5. Module Power Loss vs. Current (Vin
= 12 V, Vout = 1.2 V, Natural Air Convection)
30
DRIVER SUPPLY CURRENT (mA)
VCIN CURRENT (mA)
2
30
45
40
35
30
25
20
15
10
5
0
100 200 300
400
500
600
700
800
28
26
500 kHz
24
22
20
18
300 kHz
16
14
12
10
900 1000
4.0
4.5
5.0
5.5
6.0
SWITCHING FREQUENCY (kHz)
DRIVER SUPPLY VOLTAGE (V)
Figure 6. Driver Supply Current vs. Frequency
(VCIN = 5 V, Ta = 255C)
Figure 7. Driver Supply Current vs. Driver
Supply Voltage (Ta = 255C)
4.5
4.0
High Rising
3.5
Rising
4.4
PWM THRESHOLDS (V)
VCIN UVLO THRESHOLDS (V)
3
0
0
50
4
4.3
Falling
4.2
4.1
High Falling
3.0
2.5
2.0
1.5
Low Rising
1.0
4.0
−50
−25
0
25
50
75
100
0.5
−50
125
Low Falling
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 8. VCIN UVLO vs. Temperature
(VCIN = 5 V, Ta = 255C)
Figure 9. PWM Thresholds vs. Temperature
(VCIN = 5 V, Ta = 255C)
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125
NCP5339
2.0
2.0
1.9
1.9
ZCD_EN# THRESHOLDS (V)
DISB# THRESHOLDS (V)
TYPICAL CHARACTERISTICS
1.8
1.7
1.6
Rising
1.5
1.4
Falling
1.3
1.2
1.1
1.0
−50
−25
0
25
50
75
100
1.8
1.7
1.6
1.4
Falling
1.3
1.2
1.1
1.0
−50
125
Rising
1.5
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 10. DISB# Threshold vs. Temperature
(VCIN = 5 V, Ta = 255C)
Figure 11. ZCD_EN# Threshold vs.
Temperature (VCIN = 5 V, Ta = 255C)
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125
NCP5339
APPLICATIONS INFORMATION
Theory of Operation
and CGND pins to minimize the parasitics in this loop. A
multi−layer ceramic capacitor greater than 1 mF should be
used.
The NCP5339 is an integrated driver and MOSFET
module designed for use in a synchronous buck converter
topology. It consists of a MOSFET driver die and two
MOSFET dies, one acting as the control MOSFET
(high−side FET) and the other acting as the synchronous
MOSFET (low−side FET). A single PWM input signal is all
that is required to properly drive the high−side and low−side
MOSFETs.
High−Side Driver
The high−side driver is designed to drive a floating
low−RDS(on) N−channel MOSFET, the control MOSFET in
a buck converter. The gate voltage for the high−side driver
is developed by a bootstrap circuit referenced to the VSWH
pin (switch node).
The bootstrap circuit is comprised of the internal Schottky
diode and an external capacitor. When the NCP5339 is
starting up, the VSWH pin is held at ground, allowing the
bootstrap capacitor to charge up to VCIN through the
bootstrap diode (See Figure 1). When the PWM input is
driven high, the high−side driver will turn on the high−side
MOSFET using the stored charge of the bootstrap capacitor.
As the high−side MOSFET turns on, the VSWH pin rises.
When the high−side MOSFET is fully turned on, the switch
node will settle to VIN and the BST pin will settle to VIN +
VCIN (excluding parasitic ringing).
VCIN Undervoltage Lockout (UVLO)
The VCIN pin is monitored by an Undervoltage Lockout
circuit. While VCIN is below UVLO Rising threshold
(4.35 V, typical), the outputs of the MOSFET driver, GH and
GL, are floating. The internal pull−down resistors connected
to GH and GL keep the MOSFETs in the off−state. When
VCIN is greater than UVLO Rising threshold, the driver can
be enabled by pulling DISB# high. There is a hysteresis of
200 mV (typical) on VCIN UVLO.
Enabling/Disabling the Driver (DISB#)
The DISB# pin is used to disable the GH and GL outputs
of the MOSFET driver. When DISB# is low, the driver is
disabled, pulling both gates of the MOSFETs low. This
prevents power transfer from VIN to the output. The driver
is enabled by pulling DISB# into a logic−high state (as long
as VCIN is greater than UVLO Rising threshold). When the
driver is enabled, the states of GH and GL are determined by
the signal on the PWM pin. See Table 6 for the
UVLO/DISB# logic table.
Every time DISB# changes from a low−state to a
high−state, the driver undergoes an auto−calibration cycle
for the zero current detect threshold. This auto−calibration
cycle typically takes 25 ms to complete. The driver outputs
will not respond to the PWM input signal until the
auto−calibration cycle is completed.
Bootstrap Circuit
The bootstrap circuit relies on an external charge−storage
capacitor (CBST) and an integrated diode to provide current
to the high−side driver. A multi−layer ceramic capacitor
with a value greater than 100 nF should be used as the
bootstrap capacitor.
Overlap Protection Circuit
It is important to avoid cross−conduction of the two
MOSFETs, which could result in a decrease in the power
conversion efficiency or damage to the device.
The NCP5339 prevents cross−conduction by monitoring
the status of the MOSFETs and applying the appropriate
amount of non−overlap time (the time between the turn−off
of one MOSFET and the turn−on of the other MOSFET).
See Figure 12.
When the PWM input is driven high, the gate of the
low−side MOSFET (GL) goes low after a propagation delay,
tpdlGL. The time it takes for the low−side MOSFET to turn
off is dependent on the total charge on the low−side
MOSFET gate. The NCP5339 monitors the pre−driver
voltage of both MOSFETs and VSWH to determine the
conduction status of the MOSFETs. Once the low−side
MOSFET is turned off, an internal timer will delay the
turn−on of the high−side MOSFET, tpdhGH.
Likewise, when the PWM input pin goes low, the gate of
the high−side MOSFET (GH) goes low after a propagation
delay, tpdlGH. The time to turn off the high−side MOSFET
is dependent on the total gate charge of the high−side
MOSFET. A timer is triggered once the high−side MOSFET
stops conducting, to delay the turn−on of the low−side
MOSFET, tpdhGL.
Table 6. UVLO/DISB# Logic Table
UVLO
DISB#
GH, GL Outputs
L
X
GH = Low, GL = Low
H
L
GH = Low, GL = Low
H
H
Normal PWM Operation
(See X)
H
Open
GH = Low, GL = Low
Low−Side Driver
The low−side driver is designed to drive a ground−
referenced low−RDS(on) N−Channel MOSFET, the
synchronous MOSFET in a buck converter. The voltage
supply for the low−side driver is internally connected to the
VCIN and CGND pins. The driver turns on the low−side
MOSFET with the charge stored in the VCIN capacitor. So,
it is important to place the VCIN capacitor close to the VCIN
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NCP5339
PWM
tpdlGL
tf GL
GL
90%
90%
1V
10%
tpdh GH
10%
tpdlGH tfGH
trGH
90%
90%
10%
GH−
VSWH
trGL
10%
1V
tpdhGL
Figure 12. MOSFET Gate Timing Diagram
• When transitioning from a PWM low state to mid−state,
PWM Mid−State
The NCP5339 can be placed into a high−impedance state,
where both high−side and low−side MOSFETs are in the
off−state. This state is commonly used in multi−phase
applications that allow phase shedding. A phase can be
turned off by placing the NCP5339 from that phase into
PWM mid−state. The phase can quickly be turned back on
by having PWM exit mid−state. When the voltage on PWM
is within the VPWM_MID voltage range, both GH and GL are
pulled low after a hold−off time (See Figure 13).
5V
PWM
VPWM _HI
GL goes from high to low after tholdoff. GH is already
low due to the prior PWM low state.
• When transitioning from a PWM high state to
mid−state, GH goes from high to low without delay.
After GH is pulled low, GL goes high for tholdoff.
There are internal resistors at the PWM input that biases
the voltage on PWM to be at mid−state when the voltage at
the pin is otherwise floating.
PWM mid−state
pulls GL low after
timer expires
VPWM _LO
0V
PWM mid−state
pulls GH low
without waiting for
a timer
5V
GH
0V
5V
A high−to−mid
PWM transition
pulls GL high for
timer duration
GL
0V
tholdoff
tholdoff
Figure 13. PWM Tri−State Behavior
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tholdoff
NCP5339
Zero Current Detect
When ZCD_EN# is set low, zero cross detect (ZCD) is
enabled, see Figure 14. The high−side driver responds to
PWM in the same manner as in normal PWM mode. When
PWM is high, GH goes high after the non−overlap delay.
When PWM is low, GL goes high after the non−overlap
delay, and stays high for the duration of the ZCD blanking
timer. Once this timer expires, VSWH is monitored for zero
cross detection, pulling GL low after VSWH is detected to
be at or above the ZCD threshold voltage.
The ZCD threshold undergoes an auto−calibration cycle
every time DISB# is brought from low to high. This
auto−calibration cycle typically takes 25 ms to complete.
During the auto−calibration cycle, GH and GL are pulled
low and do not respond to PWM signals.
When operating under light load conditions, the current
ripple through the inductor can cause a buck converter to
partially operate with negative current. This can have a
noticeable impact on converter efficiency as the negative
current discharges the output capacitors. The zero current
detect feature in the NCP5339 automatically turns off the
low−side MOSFET before the inductor current goes
negative. This causes the converter to operate under
discontinuous conduction mode and improves the efficiency
during light load conditions.
The ZCD_EN# pin is a logic input pin with an active
300 kW pull−up resistance to VCIN.
When ZCD_EN# is set high, the NCP5339 will operate in
normal PWM mode.
Inductor
Current
0A
LS FET stays
on until zero
current is
detected
ZCD off
(CCM)
5V
ZCD_EN#
ZCD on
(DCM)
0V
5V
PWM
0V
5V
GH
0V
5V
LS FET turns
off when tblank
expires
GL
0V
tblank
tblank
Figure 14. Zero Current Detect Behavior
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NCP5339
Prebias Startup
1. If on startup, ZCD_EN# is low and PWM is low or
mid, GL is low. Need a PWM transition
(mid−to−high−to−low, low−to−high−to−low or
mid−to−low) to get GL to go high.
2. If on startup, ZCD_EN# is high and PWM is mid,
GL is low. Need a PWM transition to low to get
GL to go high.
3. If on startup, ZCD_EN# is high and PWM is low,
GL is high. No prebias condition.
There are conditions that could allow a converter to start
up when there is a pre−existing voltage at the output.
Turning off a converter and then quickly turning it back on
is an example of this. There are controllers that, when a
prebias startup is recognized, will want to start the power
stage without discharging the output capacitors. To allow for
a prebias startup, the GL control of the NCP5339 has the
following behavior when it is first enabled:
5V
25 ms
auto−cal
DISB#
25 ms
auto−cal
0V
5V
ZCD_EN#
0V
5V
PWM
0V
GL stays low
GL stays low
5V
GL
0V
5V
GH
0V
PWM signals ignored
during auto−cal
PWM signals ignored
during auto−cal
25 ms
auto−cal
25 ms
auto−cal
5V
DISB#
0V
5V
ZCD_EN#
0V
5V
PWM
0V
GL stays low
5V
GL
GL goes high
0V
5V
GH
0V
PWM signals ignored
during auto−cal
PWM signals ignored
during auto−cal
Figure 15. Prebias Startup
(Top figure: ZCD_EN# = High, Bottom figure: ZCD_EN# = Low)
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NCP5339
Thermal Warning / Thermal Shutdown
drops below 135°C, the THWN pin is released. If the driver
temperature exceeds 180°C, the part enters thermal
shutdown and turns off both MOSFETs. Once the
temperature falls below 155°C, the part resumes normal
operation. The THWN pin has a maximum current
capability of 30 mA.
The THWN pin is an open−drain output. The temperature
sensor is on the die of the MOSFET driver. When the
temperature of the driver reaches 150°C, the THWN pin is
pulled low indicating a thermal warning. At this point, the
part continues to function normally. When the temperature
Driver IC
temperature
180°C
165°C
150°C
135°C
...
Thermal warning activated. THWN# pin pulled low.
Thermal
shutdown
activated. Driver
outputs are
disabled.
Figure 16. Thermal Warning/Thermal Shutdown Behavior
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NCP5339
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
CASE 485CM
ISSUE O
A B
D
PIN ONE
LOCATION
2X
ÉÉÉ
ÉÉÉ
ÉÉÉ
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
ÉÉ
ÉÉ
0.15 C
EXPOSED Cu
2X
TOP VIEW
0.15 C
(A3)
DETAIL B
0.10 C
DIM
A
A1
A3
b
D
D2
D3
E
E2
E3
E4
e
G
K
L
L1
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
A
43X
0.08 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. POSITIONAL TOLERANCE APPLIES TO ALL
THREE EXPOSED PADS.
L
L
SIDE VIEW A1
C
NOTE 4
SEATING
PLANE
0.10 C A B
D3
D2
NOTE 5
G
DETAIL A
40X
L
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.18
0.30
6.00 BSC
2.30
2.50
1.40
1.60
6.00 BSC
4.30
4.50
1.90
2.10
1.64
1.84
0.50 BSC
2.20 BSC
0.20
−−−
0.30
0.50
−−−
0.15
SOLDERING FOOTPRINT
E3
6.30
E2
4.56
E4
1.66
1
G
40
K
e
40X
e/2
G
BOTTOM VIEW
40X
0.63
2.56
1
b
0.10 C A B
0.05 C
2.16
NOTE 3
4.56
6.30
2.16
PKG
OUTLINE
40X
0.50
PITCH
0.30
DIMENSIONS: MILLIMETERS
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