IRF IRFR3303TRPBF

PD - 95070A
IRFR3303PbF
IRFU3303PbF
l
l
l
l
l
l
l
Ultra Low On-Resistance
Surface Mount (IRFR3303)
Straight Lead (IRFU3033)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
Lead-Free
HEXFET® Power MOSFET
D
VDSS = 30V
RDS(on) = 0.031Ω
G
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.
D-Pak
TO-252AA
I-Pak
TO-251AA
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
33…
21…
120
57
0.45
± 20
95
18
5.7
5.0
-55 to + 150
A
W
W/°C
V
mJ
A
mJ
V/ns
300 (1.6mm from case )
°C
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
www.irf.com
Junction-to-Case
Junction-to-Ambient (PCB mount)**
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
–––
2.2
50
110
°C/W
1
12/14/04
IRFR/U3303PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
30
–––
–––
2.0
9.3
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.032
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
11
99
16
28
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
750
400
140
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.031
Ω
VGS = 10V, ID = 18A „
4.0
V
VDS = VGS, ID = 250µA
–––
S
VDS = 25V, ID = 18A
25
VDS = 30V, VGS = 0V
µA
250
VDS = 24V, VGS = 0V, TJ = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
29
ID = 18A
7.3
nC VDS = 24V
13
VGS = 10V, See Fig. 6 and 13 „
–––
VDD = 15V
–––
ID = 18A
ns
–––
RG = 13Ω
–––
RD = 0.8Ω, See Fig. 10 „
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact†
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 33…
showing the
A
G
integral reverse
––– ––– 120
p-n junction diode.
S
––– ––– 1.3
V
TJ = 25°C, IS = 18A, VGS = 0V „
––– 53
80
ns
TJ = 25°C, IF = 18A
––– 94 140
nC
di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
‚ Starting TJ = 25°C, L = 590µH
… Caculated continuous current based on maximum allowable junction
RG = 25Ω, IAS = 18A. (See Figure 12)
temperature; Package limitation current = 20A.
ƒ ISD ≤ 18A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS, † This is applied for I-PAK, LS of D-PAK is measured between
TJ ≤ 150°C
lead and center of die contact
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
IRFR/U3303PbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
100
10
1
4.5V
0.1
1
10
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
2.0
TJ = 150 ° C
TJ = 25 ° C
1
V DS = 15V
25V
20µs PULSE WIDTH
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
10
100
Fig 2. Typical Output Characteristics
100
4
1
20µs PULSE WIDTH
TJ = 150 °C
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
0.1
4.5V
1
0.1
VDS , Drain-to-Source Voltage (V)
10
10
20µs PULSE WIDTH
TJ = 25 °C
0.01
0.1
I D , Drain-to-Source Current (A)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
10
ID = 30A
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
IRFR/U3303PbF
1400
VGS , Gate-to-Source Voltage (V)
1200
C, Capacitance (pF)
20
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
1000
Ciss
800
Coss
600
400
Crss
200
0
1
10
ID = 18A
VDS = 24V
VDS = 15V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
VDS , Drain-to-Source Voltage (V)
10
15
20
25
30
QG , Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
TJ = 25 ° C
100
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
5
TJ = 150 ° C
10
1
0.1
0.0
V GS = 0 V
1.0
2.0
3.0
4.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
5.0
10us
100
100us
10
1ms
1
TC = 25 °C
TJ = 150 °C
Single Pulse
1
10ms
10
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
100
IRFR/U3303PbF
35
LIMITED BY PACKAGE
VGS
30
ID , Drain Current (A)
RD
V DS
D.U.T.
RG
25
+
-VDD
10V
20
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
15
Fig 10a. Switching Time Test Circuit
10
VDS
5
0
90%
25
50
75
100
125
150
TC , Case Temperature ( °C)
10%
VGS
td(on)
Fig 9. Maximum Drain Current Vs.
Case Temperature
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.01
0.00001
0.02
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
0.1
L
VDS
D.U.T.
RG
+
V
- DD
IAS
10 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
EAS , Single Pulse Avalanche Energy (mJ)
IRFR/U3303PbF
200
TOP
BOTTOM
ID
8.0A
11A
18A
150
100
50
0
25
50
75
100
125
Starting TJ , Junction Temperature ( °C)
tp
VDD
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
VDS
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
10 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
150
IRFR/U3303PbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
ISD
*
IRFR/U3303PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRF R120
WIT H ASS EMBLY
LOT CODE 1234
ASS EMBLED ON WW 16, 1999
IN T HE AS SEMBLY LINE "A"
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
Note: "P" in as s embly line pos ition
indicates "Lead-Free"
IRFU120
12
916A
34
AS S EMBLY
LOT CODE
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
OR
PART NUMBER
INTERNATIONAL
RECTIF IER
LOGO
IRFU120
12
AS S EMBLY
LOT CODE
34
DAT E CODE
P = DESIGNATES LEAD-F REE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 16
A = AS SEMBLY S ITE CODE
IRFR/U3303PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120
WIT H AS S EMBLY
LOT CODE 5678
AS S E MBLE D ON WW 19, 1999
IN T HE AS S EMBLY LINE "A"
PART NUMBER
INTE RNAT IONAL
RECT IF IER
LOGO
IRFU120
919A
56
78
AS S EMBLY
LOT CODE
Note: "P" in ass embly line
pos ition indicates "Lead-Free"
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
OR
PART NUMBE R
INT ERNAT IONAL
RECTIF IER
LOGO
IRFU120
56
AS SEMBLY
LOT CODE
78
DATE CODE
P = DES IGNAT ES LEAD-F REE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WE EK 19
A = ASS EMBLY SIT E CODE
IRFR/U3303PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/