ANPEC APW7153BKAI-TRG

APW7153/A/B
3A 5V 2MHz Synchronous Buck Converter
Features
General Description
•
High Efficiency up to 95%
- PFM/PWM Mode Operation
APW7153/A/B is a 3A synchronous buck converter with
integrated 110mΩ power MOSFETs. The APW7153/A/B
•
•
•
Adjustable Output Voltage from 0.8V to VIN
Integrated 110mΩ High/Low Side MOSFET
is designed with a current-mode control scheme; it can
convert wide input voltage of 2.6V to 5.5V to the output
Programmable Switching Frequency: 300kHz to
2MHz
voltage adjustable from 0.8V to 5.5V to provide excellent
output voltage regulation.
•
•
•
•
•
•
•
•
•
•
•
•
Low Dropout Operation: 100% Duty Cycle
Stable with Low ESR Capacitors
The APW7153/A/B is equipped with an PFM/PWM mode
operation. At light load, the IC operates in the PFM mode
Power-On-Reset Detection on VDD and PVDD
Integrate Soft-Start and Soft-Off
to reduce the switching losses. At heavy load, the IC works
in PWM. At PWM mode, the switching frequency is set by
Over-Temperature Protection
Over-Voltage Protection
the external resistor.
The APW7153/A/B is also equipped with Power-on-reset,
Under-Voltage Protection
High/Low Side Current-Limit
soft-start, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature and current-limit) into a
Power Good Indicator (APW7153A/B)
Enable/Shutdown Function
single package.
This device, available TDFN3x3-10 and SOP-8P provides
Small TDFN3x3-10 and SOP-8P Packages
Lead Free and Green Devices Available
a very compact system solution external components and
PCB area.
(RoHS Compliant)
Simplified Application Circuit
VIN
Applications
•
•
•
LCD Minitor/TV
Set-Top Box
VDD
PVDD
DSL, Switch HUB
•
•
VOUT
APW7153/A/B
Notebook Computer
Portable Instrument
Pin Configuration
APW7153
SHDN/RT 1
GND 2
LX 3
PGND 4
9
Expose
Pad
APW7153
8 COMP SHDN/RT 1
GND 2
7 FB
LX 3
6 VDD
LX 4
5 PVDD
PGND 5
SOP-8P
(Top View)
9
11
Expose
Pad
APW7153A
10 COMP
9 FB
8 VDD
7 PVDD
6 PVDD
11
Expose
Pad
APW7153B
10 COMP SHDN/RT 1
GND 2
9 FB
LX 3
8 POK
LX 4
7 VDD
PGND 5
6 PVDD
TDFN3X3-10
(Top View)
TDFN3X3-10
(Top View)
The pin 2 and 4 must be connected to the pin 9 (Exposed Pad)
EN/RT 1
GND 2
LX 3
LX 4
PGND 5
11
Expose
Pad
10 COMP
9 FB
8 POK
7 VDD
6 PVDD
TDFN3X3-10
(Top View)
11 The pin 2 and 5 must be connected to the pin 11 (Exposed Pad)
S
ANPEC reserves the right to make changes to improve reliability or manufacturability
without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
1
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APW7153/A/B
Ordering and Marking Information
Package Code
QB : TDFN3x3-10 KA : SOP-8P
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7153/A/B
Assembly Material
Handling Code
Temperature Range
Package Code
APW7153/A/B QB:
APW
7153
XXXXX
APW7153 KA:
APW7153
XXXXX
APW
7153A
XXXXX
APW
7153B
XXXXX
XXXXX - Date Code
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VVDD, VPVDD
VLX
(Note 1)
Parameter
Rating
Unit
-0.3 ~ 6
V
>20ns pulse width
-1 ~VPVDD+0.3
V
<20ns pulse width
-3 ~VPVDD+3
V
-0.3 ~ 6
V
Input Supply Voltage
LX to GND Voltage
SHDN/RT, FB, COMP, POK to GND Voltage
PGND
PGND to GND Voltage
PD
Power Dissipation
TJ
Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
-0.3 ~ +0.3
V
Internally Limited
W
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Junction-to-Ambient Resistance in Free Air
Typical Value
Unit
(Note 2)
TDFN3x3-10
SOP-8P
50
80
o
TDFN3x3-10
SOP-8P
10
20
o
Junction-to-Case Resistance in Free Air (Note 3)
C/W
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TDFN3x3-10 and SOP-8P is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TDFN3x3-10 and SOP-8P
packages.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
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APW7153/A/B
Recommended Operating Conditions (Note 4)
Symbol
Range
Unit
VVDD
Control and Driver Supply Voltage
2.6~ 5.5
V
VPVDD
Input Supply Voltage
1. 5~5.5
V
VOUT
Converter Output Voltage
0.8~5.5
V
IOUT
Converter Output Current
0~3
TA
TJ
Parameter
Ambient Temperature
Junction Temperature
A
-40 ~ 85
o
-40 ~ 125
o
C
C
Note 4: Refer to the typical application circuit.
Electrical Characteristics
Unless otherwise specified, these specifications apply over VVDD=VPVDD=3.3V, TA= -40 ~ 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
APW7153/A/B
Test Conditions
Min.
Typ.
Unit
Max.
SUPPLY CURRENT
VFB=1V
-
460
-
µA
IVDD_SDH VDD Shutdown Supply Current
SHDN/RT=VDD
-
-
1
µA
IVDD_SDL VDD Shutdown Supply Current
SHDN/RT=GND
-
-
10
µA
2.3
2.4
2.5
V
VDD Debounce Time
-
100
-
µs
VDD POR Hysteresis
0.1
0.2
0.3
V
PVDD POR Voltage Threshold
1.5
1.6
1.7
V
PVDD POR Debounce
-
10
-
µs
PVDD POR Hysteresis
-
50
-
mV
Regulated on FB APW7153/B
pin
APW7153A
-
0.8
-
-
0.5
-
TJ=25°C, IOUT=10mA, VDD=5V
-0.5
-
+0.5
%
IOUT=10mA~3A, VDD=2.6~5V
-0.8
-
+0.8
%
0.3
-
2
MHz
0.8
1
1.2
MHz
Maximum Converter’s Duty
-
100
-
%
Minimum on Time
-
90
-
ns
IVDD
VDD Supply Current
POWER-ON-RESET (POR)
VDD POR Voltage Threshold
VIN Rising
REFERENCE VOLTAGE
VREF
Reference Voltage
Output Voltage Accuracy
V
OSCILLATOR AND DUTY CYCLE
FOSC
Oscillator Frequency
Oscillator Frequency
RT=332kΩ
POWER MOSFET
High Side P-MOSFET Resistance
ILX=0.5A, TA=25°C
-
110
160
mΩ
Low Side N-MOSFET Resistance
ILX=0.5A, TA=25°C
-
110
160
mΩ
-
-
10
µA
High/Low Side MOSFET Leakage
Current
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
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APW7153/A/B
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VVDD=VPVDD=3.3V, TA= -40 ~ 85 oC. Typical values are at TA=25oC.
Symbol
Parameter
APW7153/A/B
Test Conditions
Unit
Min.
Typ.
Max.
-
550
-
CURRENT-MODE PWM CONVERTER
Gm
Error Amplifier Transconductance
Error Amplifier DC Gain
TD
COMP=NC
µA/V
-
80
-
dB
Current Sense Transresistance
-
500
-
mΩ
Dead Time (Note 5)
-
20
-
ns
4.0
4.5
5.0
A
-
160
-
°C
PROTECTIONS
ILIM
TOTP
High Side MOSFET Current-Limit
Over-Temperature Trip Point
Peak Current
(Note 5)
Over-Temperature Hysteresis
-
50
-
°C
Over-Voltage Protection Threshold
119
125
131
%VOUT
Under-Voltage Protection Threshold
44
50
56
%
0.7
-
1.6
A
1
1.5
2
ms
-
VVDD-0.9
VVDD -0.4
V
85
87.5
90
%VOUT
POK Low Hysteresis
(POK Goes High)
-
5
-
%VOUT
POK in from Higher
(POK Goes High)
110
112.5
115
%VOUT
-
5
-
%VOUT
Power Good Pull Low Resistance
-
100
-
Ω
Power Good Debounce
-
0.5
-
ms
Low Side MOSFET Current-Limit
From Drain to Source
SOFT-START, ENABLE AND INPUT CURRENTS
Soft-Start Time
VSHDN
SHDN Shutdown Threshold
VSHDN > SHDN shutdown Threshold,
IC shutdown
POK in from Lower
(POK Goes High)
POK Threshold
POK High Hysteresis
(POK Goes Low)
Note 5: Guarantee by design.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
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APW7153/A/B
Typical Operating Characteristics
Refer to the application circuit in the section “Typical Application Circuits”, VIN=5V, TA=25oC, unless otherwise specified.
Efficiency vs. Output Current
100
1.8
95
1.6
90
1.4
85
1.2
Efficiency (%)
RT=330k for 1MHz
1
0.8
0.6
RT=1.3M for 300kHz
75
70
65
60
0.2
55
0
0
200
400
600
0.1
1
10
RT Resistance, RRT (kΩ)
Output Current, IOUT (A)
Efficiency vs. Output Current
Reference Voltage vs. Supply Voltage
100
820
95
815
85
80
75
70
65
VIN=5V
VOUT=3.3V
RT=330k
60
55
50
0.01
0.1
1
Output Current, IOUT (A)
810
805
800
795
790
785
780
10
No Switch Quiescent Current
vs. Supply Voltage
2
2.5
3
3.5
4
4.5
Supply Voltage, V VDD (V)
5
5.5
Peak Current-Limit vs. Supply Voltage
6
450
Peak Current Limit, ILIM (A)
No Switch Quiescent Current, IVDD (µA)
VIN=5V
VOUT=1.8V
RT=330k
50
0.01
800 1000 1200 1400
90
Efficiency (%)
80
0.4
Reference Voltage, VREF (mV)
Oscillator Frequency, FOSC (MHz)
Oscillator Frequency vs. RT Resistance
2
400
350
300
250
5
4
3
2
1
0
200
2
2.5
3
3.5
4
4.5
5
5.5
2.5
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
3
3.5
4
4.5
5
5.5
Supply Voltage, VVDD (V)
Supply Voltage, V VDD (V)
5
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APW7153/A/B
Operating Waveforms
Start-up with No Load
Start-up with 3A Load
EN, 2V/div
EN, 2V/div
VOUT, 1V/div, DC
VOUT, 1V/div, DC
POK, 5V/div
POK, 5V/div
IIN, 1A/div
IIN, 200mA/div
0.5ms/div
0.5ms/div
Load Transient Response
Normal Operating
VOUT, 50mV/div, AC
3A
IOUT, 1A/div
VLX, 2V/div
Slew rate = 3A/20µs
10mA
VOUT, 100mV/div, AC
IOUT, 1A/div
VOUT =1.8V
500ns/div
100µs/div
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
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APW7153/A/B
Pin Description
PIN
TDFN3x3-10
SOP-8P
FUNCTION
NAME
APW7153 APW7153A APW7153B APW7153
Shutdown/Enable and Oscillator Input. Connecting a resistor to
SHDN/RT GND sets the switching Frequency. Pull the pin to VDD to shut
down the device. Do leave the pin floating.
1
-
1
1
-
1
-
-
EN/RT
Shutdown/Enable and Oscillator Input. Connecting a resistor to
VDD sets the switching Frequency. Pull the pin to GND to shut
down the device. Do leave the pin floating.
2
2
2
2
GND
Signal Ground. Ground of MOSFET Gate Drivers and Control
Circuitry.
3, 4
3, 4
3, 4
3
LX
Power Switching Output. LX is the Junction of the high-side and
low-side Power MOSFETs to supply power to the output LC filter.
5
5
5
4
PGND
Power Ground. The Source of the N-channel power MOSFET.
Connect this pin to the system ground with lowest impedance.
6, 7
6
6
5
PVDD
Power Input. PVDD supplies the step-down converter switches.
Connecting a ceramic bypass capacitor from PVDD to PGND to
eliminate switching noise and voltage ripple on the input to the IC.
8
7
7
6
VDD
Control circuitry supply Input. VDD supplies the control circuitry,
gate drivers. Connecting a ceramic bypass capacitor from VDD to
GND to eliminate switching noise and voltage ripple on the input
to the IC.
-
8
8
-
POK
Power Good Output. This pin is open-drain logic output that is
pulled to ground when the output voltage is not within ±12.5% of
regulation point.
9
9
9
7
FB
Output Feedback Input. The APW7153/A senses the feedback
voltage via FB and regulates the voltage at 0.8V. Connecting FB
with a resistor-divider from the converter’s output sets the output
voltage.
10
10
10
8
COMP
Output of the error amplifier. Connect a series RC network from
COMP to GND to compensate the regulation control loop. In
some cases, an additional capacitor from COMP to GND is
required.
11
11
11
9
Exposed
Pad
Connect the exposed pad to the system ground plan with large
copper area for dissipating heat into the ambient air.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
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APW7153/A/B
Block Diagram
APW7153
VDD
PVDD
Current Sense
Amplifier
LOC
OverTemperature
Protection
Power-OnReset
Current
-Limit
Zero Crossing
Amplifier
POR
1V
0.4
OTP
OVP
Fault
Logics
UVP
Inhibit
Soft-Start
COMP
Slope
Compensation
VREF
0.8V
LX
Gate
Driver
Gat
e
Current
Compartor
Error
Amplifier
Gm
FB
Gate
Control
PGND
LOC
Current Sense
Amplifier
Oscillator
Shutdown
GND
SHDN/RT
APW7153A
VDD
7
PVDD
6
Current Sense
Amplifier
LOC
OverTemperature
Protection
Power-OnReset
Current
-Limit
Zero Crossing
Comparator
POR
0.625V
OTP
OVP
Fault
Logics
0.25V
4 LX
UVP
Inhibit
0.5625V
0.4375V
Soft-Start
Current
Compartor
Error
Amplifier
Gm
FB 9
VREF
0.5V
Gate
Control
Slope
Compensation
COMP 10
Oscillator
Shutdown
Gate
Driver
Gat
e
5 PGND
LOC
Current Sense
Amplifier
2 GND
1
8
POK
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
3 LX
EN/RT
8
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APW7153/A/B
Block Diagram
APW7153B
VDD
7
PVDD
6
Current Sense
Amplifier
LOC
OverTemperature
Protection
Power-OnReset
Current
-Limit
Zero Crossing
Comparator
POR
1V
OTP
OVP
Fault
Logics
0.4V
4 LX
UVP
Inhibit
0.9V
FB 9
Soft-Start
Current
Compartor
Error
Amplifier
Gm
0.7V
Gate
Control
VREF
0.8V
Slope
Compensation
COMP 10
Oscillator
Shutdown
1
POK
SHDN/RT
9
Gate
Driver
Gat
e
5 PGND
LOC
Current Sense
Amplifier
2
8
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
3 LX
GND
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APW7153/A/B
Typical Application Circuit
L1
2.2µH
VIN
5V
CIN
22µF
PVDD
R4
2R2
CFF
22pF
VDD
R3
1M
VOUT
1.8V/3A
LX
C2
1µF
R1
25k
COUT
22µFx2
FB
APW7153
RT
332k
Cc
100pF
Rc
COMP
SHDN/RT
ON
R2
20k
30k
GND
OFF
PGND
VIN
5V
6
CIN
22µF
R3
1.8M
R5
100k
L1
2.2µH
PVDD
LX
VOUT
1.8V/3A
3,4
R4
2R2
CFF
22pF
7 VDD
C2
1µF
FB
1
OFF
POK
COMP 10
GND
VIN
5V
6
CIN
22µF
R3
1M
R5
100k
Rc
30k
PGND
L1
2.2µH
PVDD
LX
CFF
22pF
FB
1
POK
COMP 10
SHDN/RT
GND
OFF
5
R1
25k
COUT
22µFx2
9
APW7153B
ON
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
VOUT
1.8V/3A
3,4
7 VDD
C2
1µF
8
R2
15k
2
R4
2R2
RT
332k
Cc
100pF
EN/RT
ON
5
COUT
22µFx2
9
APW7153A
8
R1
39k
2
Rc
Cc
100pF
R2
20k
30k
PGND
10
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APW7153/A/B
Function Description
power MOSFETs, allowing the devices to cool. The thermal sensor allows the converters to start a start-up pro-
VDD and PVDD Power-On-Reset (POR)
The APW7153/A/B keeps monitoring the voltage on VDD
cess and to regulate the output voltage again after the
junction temperature cools by 50oC. The OTP is designed
and PVDD pins to prevent wrong logic operations which
may occur when VDD or PVDD voltage is not high enough
with a 50oC hysteresis to lower the average TJ during
continuous thermal overload conditions, increasing life-
for internal control circuitry to operate. The VDD POR rising threshold is 2.4V (typical) with 0.2V hysteresis and
time of the APW7153/A/B.
PVDD POR rising threshold is 1.7V with 0.05V hysteresis.
During start-up, the VDD and PVDD voltage must exceed
Current-Limit Protection
the enable voltage threshold. Then, the IC starts a startup process and ramps up the output voltage to the volt-
The APW7153/A/B monitors the output current, flows
through the high-side and low-side power MOSFETs, and
age target.
limits the current peak at current-limit level to prevent the
IC from damaging during overload, short-circuit, and overvoltage conditions. Typical high side power MOSFET current-limit is 4.5A, and low side MOSFET current-limit is
1.6A maximum.
Output Under-Voltage Protection (UVP)
In the operational process, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the required regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
Soft-Start
The APW7153/A/B has a built-in soft-start to control the
rise rate of the output voltage and limit the input current
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC shuts down con-
surge during start-up. During soft-start, an internal volt-
verter’s output.
The under-voltage threshold is 50% of the nominal out-
age ramp connected to one of the positive inputs of the
error amplifier, rises up from 0V to 0.95V to replace the
put voltage. The under-voltage comparator has a built-in
3µs noise filter to prevent the chips from wrong UVP shut-
reference voltage, VREF until the voltage ramp reaches the
reference voltage. During soft-start without output over-
down being caused by noise. APW7153/A/B will be latched
after under-voltage protection.
voltage, the APW7153/A/B converter’s sinking capability
is disabled until the output voltage reaches the voltage
Over-Voltage Protection (OVP)
target.
The over-voltage function monitors the output voltage by
Soft-Off
FB pin. When the FB voltage increases over 125% of the
reference voltage due to the high-side MOSFET failure or
At the moment of shutdown controlled by SHDN/RT
signal, under-voltage event or over-temperature
protection, the APW7153/A/B initiates a soft-stop process
for other reasons, the over-voltage protection comparator will force the low-side MOSFET gate driver to be high.
to discharge the output voltage in the output capacitors.
Certainly, the load current also discharges the output
This action actively pulls down the output voltage and
eventually attempts to blow the internal bonding wires.
voltage. During soft-stop, the internal voltage ramp (VRAMP)
falls down rises from 0.95V to 0V to replace the reference
As soon as the output voltage is within regulation, the
OVP comparator is disengaged. The chip will restore its
normal operation.
voltage. Therefore, the output voltage falls down slowly at
the light load. After the soft-stop interval elapses, the soft-
Over-Temperature Protection (OTP)
stop process ends and the IC turns on the low-side power
MOSFET.
The over-temperature circuit limits the junction temperature of the APW7153/A/B. When the junction temperature
exceeds TJ=+160oC, a thermal sensor turns off the both
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
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APW7153/A/B
Function Description (Cont.)
Switching Frequency and Shutdown/Enable
The SHDN/RT pin is a multi-function pin that is used to
control the switching frequency and Shutdown/Enable
function of APW7153/A/B. The switching frequency is set
by the external resistor that is connected between SHDN/
RT and GND. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing capacitor within the oscillator.
The SHDN/RT pin also provides Shutdown/Enable
function. Pulling the pin to VDD or GND, APW7153/A/B
initiates a soft-stop process and shutdown the IC.
Power Good Indicator (APW7153A/B)
POK is actively held low in shutdown and soft-start status.
In the soft-start process, the POK is an open-drain. When
the soft-start is finished, the POK is released. In normal
operation, the POK window is from 87.5% to 112.5% of
the converter reference voltage. When the output voltage
has to stay within this window, POK signal will become
high after 0.5ms internal delay. When the output voltage
outruns 85% or 115% of the target voltage, POK signal
will be pulled low immediately. In order to prevent false
POK drop, capacitors need to parallel at the output to
confine the voltage deviation with severe load step
transient.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
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APW7153/A/B
Application Information
Input Capacitor Selection
shown in “Typical Application Circuits”. A suggestion of
maximum value of R2 is 300kΩ to keep the minimum
Because buck converters have a pulsating input current,
a low ESR input capacitor is required. This results in the
current that provides enough noise rejection ability through
the resistor divider. The output voltage can be calculated
best input voltage filtering, minimizing the interference
with other circuits caused by high input voltage spikes.
as below:
R1 

VOUT = VREF ⋅  1 +

R2 

Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For
good input voltage filtering, usually a 22µF input capacitor is sufficient. It can be increased without any limit for
VOUT
better input voltage filtering. Ceramic capacitors show
better performance because of the low ESR value, and
R1≤1MΩ
FB
they are less sensitive against voltage transients and
spikes compared to tantalum capacitors. Place the input
R2 ≤ 300KΩ
APW7153
GND
capacitor as close as possible to the input and GND pin
of the device for better performance.
Output Capacitor Selection
Inductor Selection
The current-mode control scheme of the APW7153 allows the use of tiny ceramic capacitors. The higher ca-
For high efficiencies, the inductor should have a low dc
resistance to minimize conduction losses. Especially at
pacitor value provides the good load transients response.
Ceramic capacitors with low ESR values have the lowest
high-switching frequencies the core material has a higher
impact on efficiency. When using small chip inductors,
output voltage ripple and are recommended. If required,
the efficiency is reduced mainly due to higher inductor
core losses. This needs to be considered when select-
tantalum capacitors may be used as well. The output
ripple is the sum of the voltages across the ESR and the
ing the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor
ideal output capacitor.
value, the smaller the inductor ripple current and the lower
the conduction losses of the converter. Conversely, larger
∆VOUT
inductor values cause a slower load transient response.
A reasonable starting point for setting ripple current, ∆IL,


 
1
 ⋅  ESR +

8 ⋅ FSW ⋅ COUT





When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
is 40% of maximum output current. The recommended
inductor value can be calculated as below:

V
VOUT 1 − OUT
VIN

L≥
FSW ⋅ ∆IL

V
VOUT ⋅ 1 − OUT
VIN

≅
FSW ⋅ L
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.




VIN
IIN
IP-FET
IL(MAX) = IOUT(MAX) + 1/2 x ∆IL
IL
To avoid saturation of the inductor, the inductor should be
rated at least for the maximum output current of the con-
CIN
verter plus the inductor ripple current.
P-FET
VOUT
LX
N-FET
Output Voltage Setting
IOUT
ESR
COUT
In the adjustable version, the output voltage is set by a
resistive divider. The external resistive divider is connected to the output, allowing remote voltage sensing as
Copyright  ANPEC Electronics Corp.
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APW7153/A/B
Application Information (Cont.)
Output Capacitor Selection (Cont.)
Via To GND
GND
IPEAK
∆IL
LX
L1
IOUT
Via To VOUT
Rc
1
10
2
9
3
8
4
7
5
6
CFF
R1
FB
C2
ILIM
Cc
R4
RT
R2
IL
Via To GND
IP-FET
C2
C1
PGND
VOUT
VIN
Figure 1. APW7153/A/B Layout Suggestion
Recommended Minimum Footprint
Layout Considerations
Layout
For all switching power supplies, the layout is an important step in the design; especially at high peak currents
Package outline
and switching frequencies. If the layout is not carefully
done, the regulator might show noise problems and duty
0.06
cycle jitter.
Unit: Inch
0.04
1. The input capacitor should be placed close to the PVDD
and GND. Connect the capacitor and PVDD/GND with
short and wide trace without any via holes for good input
voltage filtering. The distance between PVDD/GND to
0.1
capacitor less than 2mm respectively is recommended.
2. To minimize copper trace connections that can inject
0.011
1
10
2
9
3
8
4
7
5
6
0.011
0.06
noise into the system, the inductor should be placed as
close as possible to the LX pin to minimize the noise
0.029
The via diameter = 0.012
Hole size = 0.008
TDFN3x3-10
coupling into other circuits.
3. The output capacitor should be place closed to VOUT
0.024
8
7
6
5
0.072
and GND.
4. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX) on the PCB. Therefore
place the feedback divider and the feedback compensa-
0.138
GND pin of the IC using a dedicated ground trace.
5. A star ground connection or ground plane minimizes
0.118
0.212
tion network close to the IC to avoid switching noise.
Connect the ground of feedback divider directly to the
ground shifts and noise is recommended.
1
2
0.050
3
4
Unit : Inch
SOP-8P
Copyright  ANPEC Electronics Corp.
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APW7153/A/B
Package Information
TDFN3x3-10
A
b
E
D
Pin 1
A1
D2
A3
L K
E2
Pin 1
Corner
e
S
Y
M
B
O
L
TDFN3x3-10
MILLIMETERS
MIN.
INCHES
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
0.30
0.007
0.012
0.122
A3
b
0.20 REF
0.18
0.008 REF
D
2.90
3.10
0.114
D2
2.20
2.70
0.087
0.106
0.122
0.069
E
2.90
3.10
0.114
E2
1.40
1.75
0.055
0.50
0.012
e
0.50 BSC
L
0.30
K
0.20
0.020 BSC
0.020
0.008
Note : 1. Followed from JEDEC MO-229 VEED-5.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
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APW7153/A/B
Package Information
SOP-8P
-T- SEATING PLANE < 4 mils
D
SEE VIEW A
h X 45o
E
THERMAL
PAD
E1
E2
D1
c
A1
0.25
A2
A
b
e
GAUGE PLANE
SEATING PLANE
θ
L
VIEW A
S
Y
M
B
O
L
A
SOP-8P
INCHES
MILLIMETERS
MAX.
MIN.
MIN.
MAX.
1.60
A1
0.00
0.063
0.15
0.000
0.006
0.049
A2
1.25
b
0.31
0.51
0.012
0.020
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
D1
2.50
3.50
0.098
0.138
E
5.80
6.20
0.228
0.244
0.157
0.118
E1
3.80
4.00
0.150
E2
2.00
3.00
0.079
e
1.27 BSC
0.050 BSC
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0o C
8o C
θ
0oC
8o C
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
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APW7153/A/B
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TDFN3x3-10
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
4.0±0.10
8.0±0.10
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
Application
SOP-8P
4.0±0.10
8.0±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TDFN3x3-10
Tape & Reel
3000
SOP-8P
Tape & Reel
2500
Copyright  ANPEC Electronics Corp.
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APW7153/A/B
Taping Direction Information
TDFN3x3-10
USER DIRECTION OF FEED
SOP-8P
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
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APW7153/A/B
Classification Profile
Supplier Tp≧Tc
User Tp≦Tc
TC
TC -5oC
User tp
Supplier tp
Tp
Temperature
Max. Ramp
Max. Ramp
TL
Tsmax
tp
Up Rate = 3oC/s
Down Rate = 6oC/s
TC -5oC
t
Preheat Area
Tsmin
tS
25
Time 25oC to Peak
Time
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright  ANPEC Electronics Corp.
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APW7153/A/B
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
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