APW8820 System Power PWM Controller for Notebook Computers Features General Description • Built in 2 PWM Controller into single chip • High Input Battery Voltage Range from 5.5V to 28V • Fixed 1.0MHz Switching Frequency for Individual The APW8820 offers a compact power supply solution to provide 2 voltages required by notebook application. The 2 PWM controllers use current-mode scheme with phase shift 180 degrees control scheme allow to use MLCC Channel • output capacitors. The higher fixed 1MHz switching frequency allows to use thin and small filtered components. Built in Programmable Inductor DCR Sense For Inductor Current Sense Function • The APW8820 provides good transient response and accurate DC output voltage in either PSM or PWM Mode. Built in Current Mode Control with fully Support MLCC Output Capacitor • • In Pulse Skipping Modulation Mode (PSM), the APW8820 provides high efficiency over light to heavy loads with load- Built in 180 degrees Phase Shift Function Built in PWM/PSM/Ultra Sonic PFM (25kHz) Control ing modulated switching frequencies. The unique ultrasonic mode maintains the switching frequency above Schemes • Built in Internal 5V/175mA and 3.3V/50mA Linear 25kHz, which eliminates noise in audio applications. The APW8820 built in individual enable control input on 2 chan- Regulators • 0.5V Reference Voltage • Built in Digital Soft-start nels for flexible power sequence adjustment. The powergood outputs (SYSPOK) indicate the operating mode of • Latch Off Mode for Both Channels the PWMx. • Over-Temperature Protection The APW8820 has been equipped with excellent protec- • Built in SYSPOK Report function for 2 PWM tion functions: Power-on-RESET (POR), over-current protection (OCP), over-voltage protection OVP, under-volt- Channels • Available in TQFN4x4-24 and QFN3x3-20 Package • Halogen and Lead Free Available (RoHS Compliant) age protection (UVP) and over-temperature protection (OTP) to prevent the device operate under abnormal condition or adjacent pin shortage. Applications • The APW8820 is available in TQFN4x4-24 and QFN3x320 package. NB Simplified Application Circuit V IN /5.5V~28V 3.3V PWM3 Controller Phase Shift 5V PWM5 Controller APW 8820 3.3V/50mA 5V/175mA LDO3 LDO5 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 1 www.anpec.com.tw APW8820 Ordering and Marking Information Package Code QB: TQFN4x4-24 QA: QFN3x3-20 Operating Ambient Temperature Range I : -40 to 85oC APW8820 Assembly Material Handling Code Handling Code TR : Tape & Reel Temperature Range Package Code APW8820 QB: APW8820 XXXXX Assembly Material G : Halogen and Lead Free Device APW 8820 XXXXX APW8820 QA: XXXXX - Date Code XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration 16 LDO5 COMP5/SD 3 (Exposed Pad) 13 LDO3 COMP3/SD 4 GND 12 VIN FB3 5 11 LGATE3 9 10 PHASE3 UGATE3 BOOT3 ENLDO CSN3 GND QFN3x3-20 Top View TQFN4x4-24 Top View Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 LGATE5 14 CSP3 CSN3 10 11 12 BOOT3 9 UGATE3 8 PHASE3 7 15 2 8 13 LGATE3 1 FB5 7 6 CSP5 6 CSP3 14 VIN BOOT5 FB3 5 17 15 LDO3 GND UGATE5 COMP3/SD 4 18 16 LDO5 (Exposed Pad) PHASE5 COMP5/SD 3 19 17 NC FB5 2 20 18 LGATE5 CSN5 22 21 20 19 SYSPOK BOOT5 UGATE5 PHASE5 BYP SYSPOK CSN5 24 23 CSP5 1 2 www.anpec.com.tw APW8820 Absolute Maximum Ratings (Note 1) Symbol Rating Unit Input Bias Supply Voltage (VIN to GND) -0.3 ~ 30 V VLDOx LDOx Supply Voltage (LDOx to GND) -0.3 ~ 7 V VBOOTx VBOOTx Supply Voltage VIN Parameter VBOOTx to VPHASEx -0.3 ~ 7 V -0.3 ~ 37 V <20ns pulse width -5 ~ VBOOTx+5 V >20ns pulse width -0.3 ~ VBOOTx+0.3 V <20ns pulse width -5 ~ 9 V >20ns pulse width -0.3 ~ 7 V <20ns pulse width -10 ~ 37 V >20ns pulse width -0.3 ~ VIN +0.3 V -0.3 ~ 7 V VBOOTx to GND UGATEx to PHASEx Voltage LGATEx to GND Voltage PHASEx to GND Voltage Input/Output to GND Voltage (FBx, CSNx, CSPx, COMPx, BYP, SYSPOK, ENLDO) PD Power Dissipation TJ Maximum Junction Temperature TSTG TSDR Internally Limit Storage Temperature Maximum Lead Soldering Temperature (10 Seconds) W 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Thermal Characteristics Symbol Parameter Typical Value θJA Junction-to-Ambient Resistance in free air (Note 2) θJC Case-to-Ambient Resistance in free air (Note 2) TQFN4x4-24 41 QFN3x3-20 50 TQFN4x4-24 9 QFN3x3-20 12 Unit o C/W o C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol Range Unit Input Bias Supply Voltage (VIN to GND) 5.5 ~ 28 V VOUT5 5V PWM Converter Output Voltage 0.5 ~ 5.5 V VOUT3 3.3V PWM Converter Output Voltage 0.5 ~ 5.5 V 4.7 ~ µF 4.7 ~ µF VIN CIN CLDO5 TA TJ Parameter Input Power Capacitor LDO5 Output Capacitor Ambient Temperature Junction Temperature -40 ~ 85 o -40 ~ 125 o C C Note 3: Refer to the typical application circuit. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 3 www.anpec.com.tw APW8820 Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=19V and TA= 25oC. Symbol Parameter Test Conditions APW8820 Min Typ Max 5.5 - 28 Unit SUPPLY CURRENT VIN Input Voltage Range IVIN VIN Supply Current UGATEx and LGATEx open - 200 400 µA VIN Shutdown Input Current COMPx=GND, ENLDO=GND - 30 50 µA V POWER-ON-RESET (POR) THRESHOLDS VIN Rising VIN Voltage 4.1 4.2 4.3 V VIN POR Hysteresis 0.05 0.1 0.15 V Rising LDO5 Voltage 4.1 4.2 4.3 V LDO5 POR Hysteresis 0.05 0.1 0.15 V - 0.5 - V Over temperature range -1.5 - +1.5 % IOUT = 0.3A ~ 8A, VIN=6V~28V -0.2 - +0.2 % -50 - 50 nA REFERENCE VOLTAGE (FB5, FB3) VFBx Regulated Voltage Output Voltage Accuracy (Note 4) IFBx VIN=5.5V~28V FBx Input Current LDO5 AND LDO3 LDO5 Voltage VIN=5.5V ~ 28V, BYP=GND 4.90 5.00 5.10 V LDO5 Current Limit VIN=5.5V ~ 28V, BYP=GND 175 - 330 mA BYP Threshold Voltage VBYP Rising 4.53 4.68 4.83 V - 1.5 2.5 Ω VIN>4.5V, ILOAD=0mA 3.235 3.300 3.365 V VIN<4.0V, ILOAD=0mA 3.220 3.300 3.380 V - 30 - mV VIN=5.5V ~ 28V, TA= 25oC 0.9 1.0 1.1 MHz VIN=5.5V ~ 28V, TA= -40~85 oC -15 - 15 % VIN=5.5V ~ 28V 20 25 - kHz - 25 - ns LDO5 to BYP Switch ON Resistor LDO3 Voltage LDO3 Load Regulation ILOAD=0 ~ 50mA OSCILLATOR FOSC FOSC_MI Switching Frequency at PWM Mode (PWM5 & PWM3) Switching Frequency at Ultra-sonic Mode Dead-time (Note 4) PWM GATE DRIVER UGATEx Source Current VBOOTx = 5V, VUGATEx-PHASEx=2.5V - 0.5 - A UGATEx Sink Current VBOOTx = 5V, VUGATEx-PHASEx=2.5V - 0.5 - A LGATEx Source Current VPVCC=5V, VLGATEx=2.5V - 0.5 - A LGATEx Sink Current VPVCC=5V, VLGATEx=2.5V - 0.5 - A Duty Cycle 0 - 100 % Minimum on-time - 100 - ns Zero Crossing Voltage Threshold -5 - +5 mV Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 4 www.anpec.com.tw APW8820 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VIN=19V and TA= 25oC. Symbol Parameter Test Conditions APW8820 Min Typ Max Unit CURRENT SENSE ICSPx CSPx Pin Input Current VCSPx = 5V -100 - +100 nΑ ICSNx CSNx Pin Input Current VCSNx = 5V -100 - +100 nΑ BOOTSTRAP SWITCH VF Forward Voltage VLDO5 – VBOOTx-GND, IF = 10mA - 0.5 0.8 V IR Reverse Leakage VBOOTx-GND = 30V, VPHASEx = 25V, VLDO5 = 5V - - 1 µA Error Amplifier Transconductance (Note 4) VIN=5.5V ~ 28V - 640 - µA/V Open-Loop Gain (Note 4) RL = 10KΩ, CL =10pF - 80 - dB Open-Loop Bandwidth (Note 4) RL = 10KΩ, CL = 10pF - 20 - MHz FB Input Leakage Current VFB = 0.8V - 0.1 1 µA CURRENT MODE PWM CONTROL gm COMP High Voltage - 3 - V COMP Low Voltage - 0.5 - V COMP Source Current VCOMP = 2V - 100 - µA COMP Sink Current VCOMP = 2V - 100 - µA Shutdown Threshold - - 0.4 V Enable Threshold 2.4 - - V COMPx Threshold - - 0.45 V - 1 - ms 87 90 93 % ENABLE CONTROL ENLDO Input Voltage PWM Shutdown Threshold INTERNAL SOFT-START TSS Soft-start Interval SYSPOK CONTROL SYSPOK Threshold RSYSPOK FB5 and FB3 Rising FB5 or FB3 Falling - 5 - % SYSPOK Propagation Delay FB5/FB3 Falling & Rising - 10 - µs SYSPOK Low Voltage ISINK=4mA - 0.1 0.2 V SYSPOK Leakage Current VSYSPOK=5V - - 1 µA PWM5 Fault Detected IPWMPOK=5mA (sink) 90 120 150 Ω PWM3 Fault Detected IPWMPOK=5mA (sink) 45 60 75 Ω OVP Rising Threshold 115 120 125 % UVP Falling Threshold 65 70 75 % OCSETx Current Source 9 10 11 µA Over-Temperature Protection Rising Threshold - 160 - PROTECTION for PWMx IOCSETx o C Note 4: Grauantee by design, not production test. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 5 www.anpec.com.tw APW8820 Typical Operating Characteristics Shutdown Input Current vs. Supply Voltage LDO5 Output Voltage vs. Supply Voltage Shutdown Input Voltage, ISD (uA) 40 5.02 LDO5 Output Voltage, VLDO5 (V) 35 30 25 20 15 10 5 5.00 4.98 4.96 4.94 4.92 4.90 0 0 5 10 15 20 25 0 5 Supply Voltage, VIN (V) 20 25 LDO5 Output Voltage vs. Load Current 5.1 LDO5 Output Voltage, VLDO5 (V) 3.32 LDO3 Output Voltage, VLDO3 (V) 15 Supply Voltage, VIN (V) LDO3 Output Voltage vs. Load Current 3.31 3.30 3.29 3.28 3.27 3.26 3.25 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 0 10 20 30 40 50 60 70 80 0 LDO3 Load Current, ILDO3 (mA) PWM5 Output Voltage, VOUT5 (V) 3.31 VIN=19V 3.29 VIN=7V 3.28 100 150 200 PWM5 Output Voltage vs. Load Current 5.03 3.30 50 LDO5 Load Current, ILDO5 (mA) PWM3 Output Voltage vs. Load Current 3.32 PWM3 Output Voltage, VOUT3 (V) 10 3.27 3.26 5.02 VIN=7V 5.01 5.00 VIN=19V 4.99 4.98 4.97 4.96 0 2 4 6 8 10 0 12 PWM3 Load Current, IOUT3 (A) Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 1 2 3 4 5 6 7 8 PWM5 Load Current, IOUT5 (A) 6 www.anpec.com.tw APW8820 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. Enable PWM3 Enable PWM5 VCOMP3/SD , 0.5V/Div VCOMP5/SD , 0.5V/Div 1 1 VOUT5 , 2V/Div VOUT3 , 2V/Div 2 2 VSYSPOK VSYSPOK 3 3 IIN , 0.5A/Div IIN , 0.5A/Div 4 4 TIME: 0.5ms/Div TIME: 0.5ms/Div Load Transient Response of PWM 5 Load Transient Response of PWM 5 4A 4A 1A 1A I OUT5 , 2A/Div I OUT5 , 2A/Div 1 1 2 2 VOUT5 , 0.2V/Div , AC VOUT5 , 0.2V/Div , AC VIN=7V VIN =19V TIME: 20µs/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 TIME: 20µs/Div 7 www.anpec.com.tw APW8820 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. Load Transient Response of PWM 3 Load Transient Response of PWM 3 4A 4A 1A 1A IOUT3 , 2A/Div IOUT3 , 2A/Div 1 1 2 2 V OUT3 , 0.1V/Div , AC V OUT3 , 0.1 V/Div , AC VIN=19V VIN=7V TIME: 20µs/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 TIME: 20µs/Div 8 www.anpec.com.tw APW8820 Pin Description PIN TQFN4x4-24 QFN3x3-20 Function NAME 1 1 CSP5 Positive Input of current sensing Amplifier for PWM5. This pin combined with CSN5 senses the inductor current through an RC network. 2 2 FB5 Feedback Input of PWM5. The converter senses feedback voltage via FB5 and regulates the FB5 voltage at 0.5V. Connecting FB5 with a resistor-divider from the output sets the output voltage of the converter. 3 This is a multiplexed pin. During the soft-start and normal converter operation, this pin represents the output of the error amplifier. It is used to compensate the regulation control loop in combination with the FB5 pin. Pulling COMP5/SD low (VDISABLE=0.4V) will COMP5/SD shut down the PWM5. Once the pull-down device is released, the COMP5/SD pin will start to rise. After the COMP5/SD pin exceeds the VDISABLE trip point, the PWM5 will begin a new initialization and soft-start cycle. 4 4 This is a multiplexed pin. During the soft-start and normal converter operation, this pin represents the output of the error amplifier. It is used to compensate the regulation control loop in combination with the FB3 pin. Pulling COMP3/SD low (VDISABLE=0.4V) will COMP3/SD shut down the PWM3. Once the pull-down device is released, the COMP3/SD pin will start to rise. After the COMP3/SD pin exceeds the VDISABLE trip point, the PWM3 will begin a new initialization and soft-start cycle. 5 5 FB3 Feedback Input of PWM3. The converter senses feedback voltage via FB3 and regulates the FB3 voltage at 0.5V. Connecting FB3 with a resistor-divider from the output sets the output voltage of the converter. 6 6 CSP3 Positive Input of current sensing Amplifier for PWM3. This pin combined with CSN3 senses the inductor current through an RC network. 7 7 CSN3 Positive Input of current sensing Amplifier for PWM3. This pin combined with CSN3 senses the inductor current through an RC network. 8 - GND Signal and Power Ground. Connected this pin to exposed pad. 9 - ENLDO Enable pin of LDO5/3. Forcing this pin above 2.4V enables the LDO5/3, or pulling this pin below 0.4V to shut it down. Do not leave this pin floating. 10 8 PHASE3 This pin is the return path for the high-side gate driver of PWM3. Connecting this pin to the high-side MOSFET source and connecting a capacitor to BOOT3 for the bootstrap voltage. 11 9 UGATE3 High-side Gate Driver Output of PWM3. This pin is connected to high-side MOSFET. 12 10 BOOT3 This pin provides the bootstrap voltage to the high-side gate driver of PWM3 for driving the N-channel MOSFET. An external capacitor connected from PHASE3 to BOOT3 is required for the high-side gate driver. 13 11 LGATE3 Low-side Gate Driver Output of PWM3. This pin is the gate driver for low-side MOSFET. 14 12 VIN Power Supply Input. Connect a nominal 5V to 28V power supply voltage to this pin. A power-on-reset function monitors the input voltage at this pin. It is recommended that a decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling. 15 13 LDO3 Internal 3.3V LDO Output. 16 14 LDO5 Power Supply of Internal Gate Drivers. When VBYP below 4.68V, the LDO5 internally connect to internal LDO. When VBYP exceeds 4.68V, an internal switch connects LDO5 to BYP. 17 - NC 18 15 LGATE5 Low-side Gate Driver Output of PWM5. This pin is the gate driver for low-side MOSFET. 19 16 BOOT5 This pin provides the bootstrap voltage to the high-side gate driver of PWM5 for driving the N-channel MOSFET. An external capacitor connected from PHASE5 to BOOT5 is required for the high-side gate driver. 20 17 UGATE5 High-side Gate Driver Output of PWM5. This pin is connected to high-side MOSFET. 3 No Internal Connection. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 9 www.anpec.com.tw APW8820 Pin Description (Cont.) PIN TQFN4x4-24 QFN3x3-20 21 18 Function NAME PHASE5 This pin is the return path for the high-side gate driver of PWM5. Connecting this pin to the high-side MOSFET source and connecting a capacitor to BOOT5 for the bootstrap voltage. 22 19 SYSPOK PWM5 and PWM3 Power Good Output Indicator. This pin used to indicate the status of the PWM5 and PWM3. If an fault even detected on FB5, this pin represents a 100Ω resistance. If an fault even detected on FB3, this pin represents a 45Ω resistance. Once the VFB5 and VFB3 exceed 90% of reference voltage and operate normally, this pin represents high impedance. 23 - BYP Bypass this pin to LDO5. Once VBYP exceeds 4.68V, an internal switch connects BYP to LDO5. Connecting this pin to output of PWM5. 24 20 CSN5 Negative Input of current sensing amplifier for PWM5. This pin combined with CSP5 senses the inductor current through an RC network. Exposed Pad Exposed Pad GND Signal and Power Ground. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 10 www.anpec.com.tw APW8820 Block Diagram VIN BYP LDO5 VIN POR SYSPOK PWM5POK 4.68V (typ.) LDO3 3.3V PWM3POK LDO ENLDO CSN3 + + CSP3 Slope Compe n-sation Slope Compe n-sation + CSP5 LDO5 BOOT3 Q3 UGATE3 BOOT5 Gate Driver Phase Shift Logic Control 3 LDO5 Q4 LDO5 Gate Driver PHASE3 LGATE3 CSN5 + Gate Driver Error Amplifier GND gm FB3 PWM Comparator ICMP 3 Logic Control 5 PWM Comparator 1MHz Oscillator ICMP 5 Soft0.5V Start Error Amplifier Q1 UGATE5 PHASE5 LDO5 Gate Driver LGATE5 Q2 GND gm FB5 0.5V SoftStart COMP3/SD COMP5/SD 0.5V 0.5V X 1.25 X 0.7 Under-Voltage Comparator Under-Voltage Comparator Over-Voltage Comparator Over-Voltage Comparator Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 X 0.7 11 0.5V X 1.25 0.5V www.anpec.com.tw APW8820 Typical Application Circuit V IN V IN VIN C2 4.7μF C8 Q3 0.1μF APM4810 VOUT3 3.3V/11A CFF3 (option) C5 C6 R3 56k 22μF 22μF R4 10k BOOT3 L2 Q4 APM4810 1μH R10 C10 10nF BOOT5 UGATE3 UGATE5 PHASE3 PHASE5 LGATE3 LGATE5 R8 18k 10k R12/10k VIN CSP3 CSN3 FB3 C12/1nF CSP5 CSN5 FB5 COMP3/SD 5V 175mA C15 4.7μF C1 4.7μF Q1 APM4810 L1 Q2 APM4810 1μH C9 R9 R7 18k C11/1nF V OUT5 5V/7A 10k C3 C4 22μF 22μF R1 82k CFF5 (option) R2 9.1k 10nF R11/10k COMP5/SD C14/NC SDPWM3 C7 0.1μF C13/NC BYP LDO5 3.3V SYSPOK V OUT5 LDO3 50mA SDPWM5 SYSPOK ON C16 1μF ENLDO OFF GND Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 12 www.anpec.com.tw APW8820 Function Description PSM/PWM The APW8820 integrate 2 PWM controllers and two LDO with 175mA source capability. At light loads, the inductor current may reach zero or reverse on each pulse. The bottom MOSFET is turned off by the current reversal comparator, the switch voltage will PWMx Control Loop The APW8820 is a constant frequency, synchronous rec- ring. This is discontinuous mode operation, and is normal behavior for the switching regulator. At very light loads, tifier and current-mode switching controllers. In normal operation, the high side power MOSFET is turned on each the APW8820 will automatically skip pulses in pulse skipping mode operation to maintain output regulation. cycle. The peak inductor current at which ICMPx turn off the high side MOSFET is controlled by the voltage on the COMPx node, which is the output of the error amplifier (EAMPx). An external resistive divider connected between Ultrasonic Mode The APW8820 integrated ultrasonic mode. The ultrasonic VOUTx and ground allows the EAMPx to receive an output feedback voltage VFBx at FBx pin. When the load current mode activates an unique PFM mode with a minimum switching frequency of 25kHz. The minimum frequency increases, it causes a slightly decrease in VFBx relative to the reference voltage (0.5V typical), which in turn causes 25kHz of ultrasonic mode eliminates audio-frequency interference in light load condition. It will transit to unique the COMPx voltage to increase until the average inductor current matches the new load current. PFM mode when output loading makes the frequency exceed ultrasonic frequency. When the controller detects Power-On-Reset that no switching has occurred within about 40ms (typical), an ultrasonic pulse will be occurred. The ultrasonic con- A Power-On-Reset (POR) function is designed to prevent troller turns on the lowside MOSFET firstly to reduce the output voltage. After the COMPx voltage exceed 0.45V, the wrong logic controls. The POR function continually monitors the supply voltage on the VIN pin. When the VIN volt- controller turns off lowside MOSFETs and turns high-side MOSFETs on. When the inductor current rise in which age starts to establish, the internal LDO5 and LDO3 voltage start to rise. COMPx exceed 0.45V, the controller turns on the lowside MOSFET again until the inductor current is below Soft-Start The APW8820 has a built-in digital soft-start to control the the zero-crossing threshold. The behavior is the same as PFM mode. output voltage rise and limit the current surge at the startup. During soft-start, an internal ramp connected to the Enable/Shutdown one of the positive inputs of the gm amplifier rises up to replace the reference voltage (0.5V) until the ramp volt- The APW8820 integrate individual control input pin for both converters. Pulling COMPx/SD low (VDISABLE=0.4V) will age reaches the reference voltage. The soft-start interval is about 1ms typical, independent of the converter¡¦s in- shut down the represent controller. When the pull-down device is released, the COMPx/SD pin will start to rise. put and output voltages. When the COMPx/SD pin rises above the VDISABLE trip point, the APW8820 will begin a new initialization and soft-start Soft-Stop The APW8820 integrated a soft-stop circuitry in the event cycle. of PWM under-voltage or shutdown. The soft-stop function discharges the PWM output voltages (VOUTx) from Power Good Indicator The SYSPOK is used to indicate the status of the PWM5 CSNx to the GND through an internal 20Ω switch. The reference remains active to provide an accurate thresh- and PWM3. If an Fault even detected on FB5, this pin represents a 100Ω resistance. If an fault even detected old and over-voltage protection. on FB3, this pin represents a 60Ω resistance. The fault even includes FBx over-voltage, FBx undervoltage, inductor over-current sense at CSP5/3 and CSN5/ 3. When the VFB5 and VFB3 exceed 90% of reference voltage and operate normally, this pin represents high impedance. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 13 www.anpec.com.tw APW8820 Function Description (Cont.) Adaptive Shoot-Through Protection The equations of the sensing network are: The gate driver incorporates adaptive shoot-through proVL (s) = IL (s) × (sL + DCR) tection to high-side and low-side MOSFETs from conducting simultaneously and shorting the input supply. VC (s) = VL (s) × This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to 1 I (s) × (sL + DCR ) = L 1 + sRSCS 1 + sRSCS Take R SC S = rise. During turn-off the low-side MOSFET, the internal LGATE voltage is monitored until it below 1.5V threshold, at which time the UGATE is released to rise after a constant delay. L DCR If the above is true, the voltage across the capacitor CS is equal to voltage drop across the inductor DCR, and the During turn-off the high-side MOSFET, the UGATE voltage is also monitored until it above 1.5V threshold, at voltage VC is proportional to the inductor current IL. which time the LGATE is released to rise after a constant delay. VC = DCR x IL Where Over-Temperature Protection (OTP) IL is the inductor current DCR is the inductor resistance When the junction temperature exceed the threshold temperature 160oC (typical), the device enter the over temperature protection (OTP). When the OTP occurs, the APW8820 shut off 2 channels of regulators’circuitry with Inductor Current Sense and Over-Circuit Protection a latch. The APW8820 will initiate a soft-start process until re-cycle power supply or both the control input The over-current function protects the switching converter against over-current or short-circuit conditions. The con- (COMPx/SD). troller senses the inductor current by detecting the drain to-source voltage which is the product of the inductor’s Over-Temperature Protection (OTP) current and the on-resistance of the low-side MOSFET during it’s on-state. A resistor (ROCSETx ), connected from Below shows the circuit of sensing inductor current. Connecting a series resistor (RS) and a capacitor (CS) net- the LGATEx to the GND, programs the over-current trip level. Before the IC initiates soft-start process, an inter- work in parallel with the inductor and measuring the voltage (VC) across the capacitor can sense the inductor nal current source, IOCSETx (5mA typical), flowing through the ROCSETx develops a voltage (VROCSETx) across the ROCSETx. current. + VL IL The device holds VROCSETx and stops the current source, IOCSETx. The APW8820 initial soft-start process after over- DCR current setting completed. Once the voltage across the low-side MOSFET exceeds the VROCSET, the IC shuts off VOUT PHASE RS the converter. Both the output of the PWMx converter are latched. The threshold of the valley inductor current-limit CS + VC - is therefore given by: CSP CSN Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 ILIMIT = 14 IOCSETx × ROCSETx DCR www.anpec.com.tw APW8820 Function Description (Cont.) Under Voltage Protection In the operational process, if short-circuit occurs, the outVIN put voltage will drop quickly. When load current increased, the output voltage will falls out of the required regulation range. The under-voltage circuitry continually monitors the setting output voltage after soft-start is completed. If a Power-On Reset IOCSETx (10uA typical) load step is strong enough to pull the output voltage lower than the under-voltage threshold, the PWM controller starts Sample and Hold a soft-stop process to shut down the output gradually. If any channel triggers under-voltage, both under-voltage protection circuits active and latched off when the softstop process is completed. The under-voltage threshold VROCSETx To LGATEx is 70% of the nominal output voltage. The APW8820 will initiate a soft-start process until re-cycle power supply or VIN both the control input (COMPx/SD). UGATEx Lx PHASEx DCR Output Over-Voltage Protection VOUTx The over-voltage protection circuitry monitors the FB5 and LGATEx IOCSETx FB3 voltage to prevent the output from over-voltage. Once the feedback voltage, FB5 and FB3, exceed 120% of ref- + VC - ROCSETx erence voltage, the APW8820 turns on the low-side To Logic Control MOSFET until the output voltage falls below 5% of normal. When the output voltage falls below 5% of normal, all the gm channels converter are shut off. The UGATEx and LGATEx are pulled low. The APW8820 will initiate a soft-start pro- VROCSETx cess until re-cycle power supply or both the control input (COMPx/SD). For the over-current is never occurred in the normal operating load range; the variation of all parameters in the above equation should be considered: The minimum IOCSET (9µA) and minimum R OCSETx should be used in the above equation. The overshoot and transient peak current also should be considered. Due to the OCP sense the integrated VC, the OCP threshold equal to output current (IOUTx) rather than peak or valley inductor current. The APW8820 will initiate a soft-start process until recycle power supply or both the control input (COMPx/SD). Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 15 www.anpec.com.tw APW8820 Application Information • The input capacitor should be near the drain of the Layout Consideration upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at 1000kHz, the resulting the output capacitor GND and the lower MOSFET GND. • The drain of the MOSFETs (VIN and PHASE nodes) current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. should be a large plane for heat sinking. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full VIN load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and BOOTx LDO5 parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. UGATEx In general, using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combined using L O A D PHASEx LDO5 ground plane construction or single point grounding. Below illustrates the layout, with bold lines indicating high LGATEx current paths; these traces must be short and wide. Components along the bold lines should be placed lose GND together. Below is a checklist for your layout: • The gate driver trace should be as short as possible. CBOOTx which connected between BOOTx and PHASEx should closed to IC. Keep the switching nodes (UGATEx, LGATEx, and PHASEx) as short as possible. • Keep the sensitive small nodes (FBx, CSPx, CSNx, COMPx) away from the switching nodes (UGATEx, LGATEx, and PHASEx). • Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. • Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 16 www.anpec.com.tw APW8820 Package Information QFN3x3-20 A E b D Pin 1 A1 A3 D2 NX aaa c L K E2 Pin 1 Corner e S Y M B O L QFN3x3-20 MILLIMETERS MIN. INCHES MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.15 0.25 0.006 0.010 D 2.90 3.10 0.114 0.122 0.071 D2 1.50 1.80 0.059 E 2.90 3.10 0.114 0.122 E2 1.50 1.80 0.059 0.071 0.50 0.012 e 0.40 BSC L 0.30 K 0.20 aaa 0.016 BSC 0.020 0.008 0.08 0.003 Note : 1. Followed from JEDEC MO-220 WEEE Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 17 www.anpec.com.tw APW8820 Package Information QFN4x4-24 A E b D Pin 1 A1 A3 NX D2 L K E2 Pin 1 Corner aaa c e TQFN4x4-24 S Y M B O L MIN. MAX. MIN. A 0.70 0.80 0.028 0.032 A1 0.00 0.05 0.000 0.002 MILLIMETERS A3 INCHES 0.20 REF MAX. 0.008 REF b 0.18 0.30 0.008 D 3.90 4.10 0.154 0.161 0.110 0.161 D2 2.50 2.80 0.098 E 3.90 4.10 0.154 E2 2.50 2.80 0.098 e 0.50 BSC L 0.35 K 0.20 aaa 0.012 0.110 0.020 BSC 0.014 0.45 0.018 0.008 0.003 0.08 Note : 1. Doll owed from JEDFC MO-220 WGGD-6 Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 18 www.anpec.com.tw APW8820 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application QFN3X3-20 A H T1 C d D W E1 F 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 TQFN4x4-24 8.0±0.10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30±0.20 (mm) Devices Per Unit Package Type QFN3x3-20 TQFN4x4-24 Unit Tape & Reel Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 Quantity 3000 3000 19 www.anpec.com.tw APW8820 Taping Direction Information QFN3x3-20 USER DIRECTION OF FEED TQFN4x4-24 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 20 www.anpec.com.tw APW8820 Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 21 www.anpec.com.tw APW8820 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 22 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8820 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2012 23 www.anpec.com.tw