APW7145 3A, 12V, Synchronous-Rectified Buck Converter Features General Description • Wide Input Voltage from 4.3V to 14V The APW7145 is a 3A synchronous-rectified Buck con- • Output Current up to 3A • Adjustable Output Voltage from 0.8V to VIN verter with integrated 55mΩ power MOSFETs. The APW7145, designed with a current-mode control scheme, can convert wide input voltage of 4.3V to 14V to the output voltage adjustable from 0.8V to VIN to provide excellent - ±2% System Accuracy • 55mΩ Integrated Power MOSFETs • High Efficiency up to 95% output voltage regulation. For high efficiency over all load current range, the - Automatic Skip/PWM Mode Operation • APW7145 is equipped with an automatic Skip/PWM mode operation. At light load, the IC operates in the Skip mode, Current-Mode Operation - Easy Feedback Compensation which keeps a constant minimum inductor peak current, to reduce switching losses. At heavy load, the IC works in - Stable with Low ESR Output Capacitors - Fast Load/Line Transient Response PWM mode, which inductor peak current is programmed by the COMP voltage, to provide high efficiency and excel- • Power-On-Reset Monitoring • Fixed 500kHz Switching Frequency in PWM Mode • Built-In Digital Soft-Start and Soft-Stop • Current-Limit Protection with Frequency Foldback • 123% Over-Voltage Protection • Hiccup-Mode 50% Under-Voltage Protection • Over-Temperature Protection • <3µA Quiescent Current in Shutdown Mode • This device, available SOP-8P and DFN4x4-8 packages, provides a very compact system solution with minimal SOP-8P and Compact 4mmx4mm DFN-8 external components and PCB area. lent output voltage regulation. The APW7145 is also equipped with power-on-reset, softstart, soft-stop, and whole protections (under-voltage, over-voltage, over-temperature, and current-limit) into a single package. In shutdown mode, the supply current drops below 3µA. (DFN4x4-8) Packages • Lead Free and Green Devices Available 100 (RoHS Compliant) 90 80 Applications 70 60 VIN=5V, VOUT=3.3V, L1=2.2µH • OLPC, UMPC 50 • Notebook Computer 40 VIN=12V, VOUT=3.3V, L1=4.7µH • Handheld Portable Device 30 VIN=5V, VOUT=1.2V, L1=2.2µH • VIN=12V, VOUT=5V, L1=6.8µH 20 Step-Down Converters Requiring High Efficiency 10 and 3A Output Current 0 0.001 VIN=12V, VOUT=2V, L1=3.3µH 0.01 0.1 1 10 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 1 www.anpec.com.tw APW7145 Pin Configuration APW7145 NC VIN AGND FB 1 2 3 4 APW7145 8 7 6 5 9 LX PGND LX EN COMP NC VIN AGND FB 1 2 3 4 SOP-8P (Top View) 8 7 6 5 PGND LX EN COMP DFN4x4-8 (Top View) The Pin 7 must be connected to the Exposed Pad Ordering and Marking Information Package Code KA : SOP-8P QA: DFN4x4-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7145 Assembly Material Handling Code Temperature Range Package Code APW7145 KA : APW7145 XXXXX XXXXX - Date Code APW7145 QA : APW7145 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol (Note 1) Parameter VIN VIN Supply Voltage (VIN to AGND) VLX LX to GND Voltage PGND to AGND Voltage EN to AGND Voltage FB, COMP to AGND Voltage PD Power Dissipation TSDR Unit V > 100ns -1 ~ VIN+1 < 100ns - 5 ~ VIN+5 Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds V -0.3 ~ +0.3 V -0.3 ~ VIN+0.3 V -0.3 ~ 6 V Internally Limited Maximum Junction Temperature TSTG Rating -0.3 ~ 15 W 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 2 www.anpec.com.tw APW7145 Thermal Characteristics Symbol θJA θJC Parameter Typical Value Junction-to-Ambient Thermal Resistance in Free Air Unit (Note 2) SOP-8P DFN4x4-8 50 65 o SOP-8P DFN4x4-8 20 30 o C/W Junction-to-Case Resistance in Free Air (Note 3) C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P and DFN4x4-8 packages. Recommended Operating Conditions (Note 4) Symbol VIN Parameter Range Unit VIN Supply Voltage 4.3 ~ 14 V VOUT Converter Output Voltage 0.8 ~ VIN V IOUT Converter Output Current 0~3 A CIN Converter Input Capacitor (MLCC) COUT LOUT TA TJ 8 ~ 50 µF Converter Output Capacitor 20 ~ 1000 µF Effective Series Resistance 0 ~ 60 mΩ Converter Output Inductor 1 ~ 22 µH Resistance of the Feedback Resistor connected from FB to GND 1 ~ 20 kΩ Ambient Temperature Junction Temperature -40 ~ 85 o -40 ~ 125 o C C Note 4: Refer to the Typical Application Circuits. Electrical Characteristics Refer to the “Typical Application Circuits”. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APW7145 Test Conditions Unit Min. Typ. Max. VFB = VREF +50mV, VEN=3V, LX=NC - 0.5 1.5 mA VEN = 0V - - 3 µA 3.9 4.1 4.3 V - 0.5 - V - 0.8 - V TJ = 25 C, IOUT=10mA, VIN=12V -1.0 - +1.0 IOUT=10mA~3A, VIN=4.75~14V -2.0 - +2.0 SUPPLY CURRENT IVIN IVIN_SD VIN Supply Current VIN Shutdown Supply Current POWER-ON-RESET (POR) VOLTAGE THRESHOLD VIN POR Voltage Threshold VIN rising VIN POR Hysteresis REFERENCE VOLTAGE VREF Reference Voltage Regulated on FB pin o Output Voltage Accuracy % Line Regulation VIN = 4.75V to 14V - +0.02 - %/V Load Regulation IOUT = 0.5A ~ 3A - -0.04 - %/A Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 3 www.anpec.com.tw APW7145 Electrical Characteristics (Cont.) Refer to the “Typical Application Circuits”. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APW7145 Test Conditions Unit Min. Typ. Max. 450 500 550 kHz - 80 - kHz OSCILLATOR AND DUTY CYCLE FOSC TON_MIN Oscillator Frequency TJ = -40 ~ 125oC, VIN = 4.75 ~ 14V Foldback Frequency VOUT = 0V Maximum Converter’s Duty - 99 - % Minimum Pulse Width of LX - 150 - ns CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance VFB=VREF±50mV - 200 - µA/V Error Amplifier DC Gain COMP = NC - 80 - dB - 0.1 - V/A Between VIN and Exposed Pad, VIN = 5V, TJ=25°C - 70 100 Between VIN and Exposed Pad, VIN = 12V, TJ=25°C - 55 80 Between GND and Exposed Pad, VIN = 5V, TJ=25°C - 55 100 Between GND and Exposed Pad, VIN = 12V, TJ=25°C - 45 80 Current-Sense to COMP Voltage Transresistance High-Side Switch Resistance Low-Side Switch Resistance mΩ mΩ PROTECTIONS High-Side Switch Current-limit Peak Current 5 6.5 8 A VTH_UV FB Under-Voltage Threshold VFB falling 45 50 55 % VTH_OV FB Over-Voltage Threshold VFB rising 118 123 128 % ILIM TOTP FB Under-Voltage Debounce - 1 - µs Over-Temperature Trip Point - 150 - o Over-Temperature Hysteresis TD Dead-Time VLX = -0.7V C - 40 - o - 20 - ns 1.5 2 2.5 ms 0.5 V C SOFT-START, SOFT-STOP, ENABLE, AND INPUT CURRENTS TSS Soft-Start / Soft-Stop Interval EN Low Logic Level VEN falling - - EN High Logic Level VEN rising 2.1 - - V High-side Switch Leakage Current VEN = 0V, VLX = 0V - - 2 µA -100 - +100 nA -100 - +100 nA IFB FB Pin Input Current IEN EN Pin Input Current Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 VEN = 0V ~ VIN 4 www.anpec.com.tw APW7145 Typical Operating Characteristics (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Output Current vs. Output Voltage 3.4 90 3.38 80 3.36 Output Voltage, VOUT (V) Efficiency (%) Output Current vs. Efficiency 100 70 60 VIN=5V, VOUT=3.3V, L1=2.2µH 50 VIN=12V, VOUT=5V, L1=6.8µH 40 VIN=12V, VOUT=3.3V, L1=4.7µH 30 VIN=5V, VOUT=1.2V, L1=2.2µH 20 10 VIN=12V, VOUT=2V, L1=3.3µH 0 0.001 3.34 3.32 3.3 3.28 3.26 3.24 3.22 3.2 0.01 0.1 1 10 0 1 Output Current, IOUT (A) Current Limit Level (Peak Current) 3.4 IOUT=500mA Output Voltage, VOUT (V) 3.38 Current Limit Level, ILIM (A) 3 Output Voltage vs. Supply Voltage vs. Junction Temperature 7 2 Output Current, IOUT (A) 7.5 7 6.5 6 3.36 3.34 3.32 3.3 3.28 3.26 3.24 3.22 5.5 3.2 -40 -20 0 20 40 60 80 100 120 140 4 6 Junction Temperature, TJ (oC) 10 12 14 Reference Voltage vs. Junction Temperature VIN Input Current vs. Supply Voltage 2.0 0.816 Reference Voltage, VREF (V) VFB=0.85V VIN Input Current, IVIN (mA) 8 Supply Voltage, VIN (V) 1.5 1.0 0.5 0.812 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -50 0.0 0 2 4 6 8 10 12 14 Supply Voltage, VIN (V) Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 -25 0 25 50 75 100 125 150 o Junction Temperature, TJ ( C) 5 www.anpec.com.tw APW7145 Typical Operating Characteristics (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Oscillator Frequency vs. Junction Temperature Oscillator Frequency, FOSC (kHz) 550 540 530 520 510 500 490 480 470 460 450 -50 -25 0 25 50 75 100 125 150 o Junction Temperature, TJ ( C) Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 6 www.anpec.com.tw APW7145 Operating Waveforms (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Power On Power Off IOUT=3A IOUT=3A VIN VIN 1 1 VOUT VOUT 2 2 IL1 IL1 3 3 CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 1ms/div CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 10ms/div Shutdown Enable IOUT=3A 1 IOUT=3A VEN VEN 1 VOUT VOUT 2 2 IL1 IL1 3 3 CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1, 2A/div Time : 100µs/div CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 2A/div Time : 1ms/div Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 7 www.anpec.com.tw APW7145 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Short Current Short Circuit IOUT =3~7A VOUT is shorted to GND by a short wire VLx 1 VLX 1 VOUT VOUT 2 2 IL1 IL1 3 3 CH1 : VLX , 10V/div CH2 : VOUT , 2V/div CH3 : IL1 , 5A/div Time : 20µs/div CH1 : VLX , 5V/div CH2 : VOUT , 200mV/div CH3 : IL1 , 5A/div Time : 5ms/div Load Transient Response Load Transient Response 1 IOUT= 50mA-> 3A ->50mA IOUT rising/falling time=10µs VOUT IOUT= 0.5A-> 3A ->0.5A IOUT rising/falling time=10µs 1 VOUT IL1 IL1 2 2 CH1 : VOUT , 200mV/div CH1 : VOUT , 100mV/div CH2 : IL1 , 2A/div CH2 : IL1 , 2A/div Time : 100µs/div Time : 100µs/div Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 8 www.anpec.com.tw APW7145 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH) Switching Waveform Switching Waveform VLX IOUT=0.2A VLX IOUT=3A 1 1 IL1 IL1 2 2 CH1 : VLX , 5V/div CH2 : IL1 , 2A/div Time : 1µs/div CH1 : VLX , 5V/div CH2 : IL1 , 2A/div Time : 1µs/div Line Transient VIN= 5~12V Over-Voltage Protection VIN VIN rising/falling time=20µs VIN VOUT 1 1 VOUT 2 2 VLX 3 IL1 4 IL1 3 IOUT=-1A CH1 : VIN , 5V/div CH2 : VOUT , 50mV/div (Voffset=3.3V) CH3 : IL1 , 2A/div Time : 100µs/div Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : VLX , 5V/div CH4 : IL1 , 5A/div Time : 20µs/div 9 www.anpec.com.tw APW7145 Pin Description PIN FUNCTION NO. NAME 1 NC No Connection. 2 VIN Power Input. VIN supplies the power (4.3V to 14V) to the control circuitry, gate drivers and step-down converter switches. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and both of AGND and PGND to eliminate switching noise and voltage ripple on the input to the IC. 3 AGND Ground of MOSFET Gate Drivers and Control Circuitry. 4 FB Output Feedback Input. The APW7145 senses the feedback voltage via FB and regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’s output sets the output voltage from 0.8V to VIN. 5 COMP Output of the error amplifier. Connecting a series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required. 6 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Connecting this pin to VIN if it is not used. 7 LX Power Switching Output. LX is the junction of the high-side and low-side power MOSFETs to supply power to the output LC filter. 8 PGND Power Ground of the APW7145, which is the source of the N-channel power MOSFET. Connect this pin to the system ground with lowest impedance. LX Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to the output. The Exposed Pad provides current with lower impedance than the Pin 7. Connecting the pad to output LC filter via a top-layer thermal pad on PCBs. The PCB will be a heat sink of the IC. 9 (Exposed Pad) Block Diagram VIN Current Sense Amplifier Power-OnReset Zero-Crossing Comparator POR OVP 123%VREF 50%VREF UVP UG Soft-Start / Soft-Stop and Fault Logic Gate Driver Soft-Start / Soft-Stop FB Inhibit LX Gate Control Gm VREF VIN Current Limit Error Amplifier VIN LG Current Compartor COMP Gate Driver PGND Slope Compensation EN Enable/ Shutdown Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 OverTemperature Protection FB 10 Oscillator 500kHz AGND www.anpec.com.tw APW7145 Typical Application Circuit 1. 4.3~14V Single Power Input Step-down Converter (with a Ceramic Output Capacitor) VIN C1 2 VIN L1 3A Enable 6 LX EN U1 LX APW7145 Shutdown PGND 5 VOUT 7 8 C2 COMP R3 (± 5%) C3 (±30%) 9 FB AGND 3 R1 ± 1% 4 R2 ±1% C4 (± 30%, Optional) a. Cost-effective Feedback Compensation (C4 is no connection) V IN(V) V OUT(V) 12 5 12 L1(µF) C2(µF) C2 ESR(mΩ) R1(kΩ) R2(kΩ) R3(kΩ) C3(pF) 6.8 22 5 63.0 12 33.0 820 5 6.8 44 3 63.0 12 68.0 820 12 3.3 4.7 22 5 46.9 15 27.0 1000 12 3.3 4.7 44 3 46.9 15 56.0 1000 12 2 3.3 22 5 30.0 20 18.0 1800 12 2 3.3 44 3 30.0 20 33.0 1800 12 1.8 3.3 22 5 18.8 15 15.0 1800 12 1.8 3.3 44 3 18.8 15 30.0 1800 5 3.3 2.2 22 5 46.9 15 27.0 470 5 3.3 2.2 44 3 46.9 15 56.0 470 5 1.8 2.2 22 5 25.0 20 15.0 820 5 1.8 2.2 44 3 25.0 20 30.0 820 5 1.5 2.2 22 5 21.9 25 12.0 1000 5 1.5 2.2 44 3 21.9 25 24.0 1000 5 1.2 2.2 22 5 7.5 15 10.0 1200 5 1.2 2.2 44 3 7.5 15 20.0 1200 Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 11 www.anpec.com.tw APW7145 Typical Application Circuit (Cont.) b. Fast-Transient-Response Feedback Compensation (C4 is connected) VIN(V) VOUT(V) L1(µH) C2(µF) C2 ESR(mΩ) R1(kΩ) R2(kΩ) R3(kΩ) C3(pF) C4(pF) 12 5 6.8 22 5 63.0 12 43 680.0 27 12 5 6.8 44 3 63.0 12 82 680.0 27 12 3.3 4.7 22 5 46.9 15 27 1000.0 27 12 3.3 4.7 44 3 46.9 15 56 1000.0 27 12 2 3.3 22 5 30.0 20 18 1800.0 27 12 2 3.3 44 3 30.0 20 33 1800.0 27 12 1.8 3.3 22 5 18.8 15 15 1800.0 33 12 1.8 3.3 44 3 18.8 15 30 1800.0 33 5 3.3 2.2 22 5 46.9 15 27 470.0 27 5 3.3 2.2 44 3 46.9 15 56 470.0 27 5 1.8 2.2 22 5 25.0 20 15 820.0 56 5 1.8 2.2 44 3 25.0 20 30 820.0 56 5 1.5 2.2 22 5 22 25 12 1000 56 5 1.5 2.2 44 3 22 25 24 1000 56 5 1.2 2.2 22 5 7.5 15 10 1200 180 5 1.2 2.2 44 3 7.5 15 20 1200 270 2. +12V Single Power Input Step-down Converter (with an Electrolytic Output Capacitor) C1 2.2µF 2 VIN C5 470µF VIN 12V L1 4.7µH /3A Enable 6 LX EN U1 LX APW7145 Shutdown PGND 5 Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 8 R1 46.9K 1% COMP R3 100K C3 1000pF 9 7 FB AGND 3 4 VOUT 3.3V/3A C2 470µF (ESR=30mΩ) R2 15K 1% 12 www.anpec.com.tw APW7145 Function Description VIN Power-On-Reset (POR) The under-voltage threshold is 50% of the nominal output voltage. The undervoltage comparator has a built-in The APW7145 keeps monitoring the voltage on the VIN 2µs noise filter to prevent the chips from wrong UVP shutdown caused by noise. The under-voltage protection pin to prevent wrong logic operations which may occur when VIN voltage is not high enough for the internal con- works in a hiccup mode without latched shutdown. The IC will initiate a new soft-start process at the end of the trol circuitry to operate. The VIN POR has a rising threshold of 4.1V (typical) with 0.5V of hysteresis. preceding delay. During start-up, the VIN voltage must exceed the enable voltage threshold. Then, the IC starts a start-up process Over-Voltage Protection (OVP) and ramps up the output voltage to the voltage target. The over-voltage function monitors the output voltage by FB pin. When the FB voltage increase over 123% of the reference voltage due to the high-side MOSFET failure, Digital Soft-Start The APW7145 has a built-in digital soft-start to control the rise rate of the output voltage and limit the input current or for other reasons, the over-voltage protection comparator will force the low-side MOSFET gate driver high. This surge during start-up. During soft-start, an internal voltage ramp (VRAMP), connected to one of the positive inputs of action actively pulls down the output voltage and eventually attempts to blow the internal bonding wires. As soon the error amplifier, rises up from 0V to 0.95V to replace the reference voltage (0.8V) until the voltage ramp reaches as the output voltage is within regulation, the OVP comparator is disengaged. The chip will restore its normal the reference voltage. During soft-start without output over-voltage, the APW7145 operation. This OVP scheme only clamps the voltage overshoot and does not invert the output voltage when other- converter’s sinking capability is disabled until the output voltage reaches the voltage target. wise activated with a continuously high output from lowside MOSFET driver - a common problem for OVP Digital Soft-Stop schemes with a latch. At the moment of shutdown controlled by EN signal, un- Over-Temperature Protection (OTP) der-voltage event, or over-temperature protection, the APW7145 initiates a digital soft-stop process to discharge The over-temperature circuit limits the junction tempera- the output voltage in the output capacitors. Certainly, the load current also discharges the output voltage. ture of the APW7145. When the junction temperature exceeds TJ = +150oC, a thermal sensor turns off the both power MOSFETs, allowing the devices to cool. The thermal sensor allows the converters to start a start-up pro- During soft-stop, the internal voltage ramp (VRAMP) falls down from 0.95V to 0V to replace the reference voltage. cess and regulate the output voltage again after the junction temperature cools by 40 oC. The OTP is designed Therefore, the output voltage falls down slowly at light load. After the soft-stop interval elapses, the soft-stop process ends and the the IC turns on the low-side power MOSFET. with a 40 oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing life- Output Under-Voltage Protection (UVP) time of the APW7145. In the operational process, if a short-circuit occurs, the Enable/Shutdown output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the re- Driving EN to the ground initiates a soft-stop process and then places the APW7145 in shutdown. When in shutdown, after the soft-stop process is completed, the quired regulation range. The under-voltage continually monitors the FB voltage after soft-start is completed. If a internal power MOSFETs turns off, all internal circuitry shuts down and the quiescent supply current reduces to load step is strong enough to pull the output voltage lower than the under-voltage threshold, the IC shuts down less than 3mA. converter’s output. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 13 www.anpec.com.tw APW7145 Function Description (Cont.) Current-Limit Protection The APW7145 monitors the output current, flowing through the high-side power MOSFET, and limits the current peak at current-limit level to prevent loads and the IC from damages during overload or short-circuit conditions. Frequency Foldback The foldback frequency is controlled by the FB voltage. When the output is shortened to the ground, the frequency of the oscillator will be reduced to 80kHz. This lower frequency allows the inductor current to safely discharge, thereby preventing current runaway. The oscillator’s frequency will gradually increase to its designed rate when the feedback voltage on FB again approaches 0.8V. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 14 www.anpec.com.tw APW7145 Application Information T=1/FOSC Setting Output Voltage The regulated output voltage is determined by: VOUT VLX R1 = 0.8 ⋅ (1 + ) R2 DT (V) I IOUT IL Suggested R2 is in the range from 1K to 20kΩ. For portable applications, a 10K resistor is suggested for R2. To prevent stray pickup, please locate resistors R1 and R2 IOUT IQ1 close to APW7145. I ICOUT Input Capacitor Selection Use small ceramic capacitors for high frequency VOUT decoupling and bulk capacitors to supply the surge current needed each time the P-channel power MOSFET (Q1) VOUT turns on. Place the small ceramic capacitors physically close to the VIN and between the VIN and the GND. Figure 1. Converter Waveforms The important parameters for the bulk input capacitor are Output Capacitor Selection the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are the function of the switching frequency and the ripple current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor volt- current (∆I). The output ripple is the sum of the voltages, having phase shift, across the ESR, and the ideal output age rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations: a conservative guideline. The RMS current (IRMS) of the bulk input capacitor is calculated as the following equation: IRMS = IOUT ⋅ D ⋅ (1- D) (A) where D is the duty cycle of the power MOSFET. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tanta- D= VOUT VIN ........... (1) ∆I = VOUT ·(1 - D) FOSC ·L ........... (2) VESR = ∆I. ⋅ ESR lum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. ........... (3) The peak-to-peak voltage of the ideal output capacitor is calculated as the following equation: ∆VCOUT = VIN VIN IQ1 CIN ........... (4) For the applications using bulk capacitors, the ∆VCOUT is Q1 IL LX Q2 ∆I (V) 8 ⋅ FOSC ⋅ COUT much smaller than the VESR and can be ignored. Therefore, the AC peak-to-peak output voltage (∆VOUT ) is shown as IOUT VOUT L ICOUT below: ESR ∆VOUT = ∆ I ⋅ ESR COUT Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 15 (V) ........... (5) www.anpec.com.tw APW7145 Application Information (Cont.) VOUT ·(VIN - VOUT ) ≤ 1.2 500000 ·L ·VIN Output Capacitor Selection (Cont.) For the applications using ceramic capacitors, the VESR is much smaller than the ∆V COUT and can be ignored. L≥ Therefore, the AC peak-to-peak output voltage (∆VOUT ) is close to ∆VCOUT. VOUT ·(VIN - VOUT ) 600000 ·VIN ........... (6) (H) where VIN = VIN(MAX) The load transient requirements are the function of the slew rate (di/dt) and disengaged\the magnitude of the Layout Consideration transient load current. These requirements are generally met with a mix of capacitors and careful layout. High fre- In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In quency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk general, interconnecting impedance should be minimized by using short and wide printed circuit traces. Signal and filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating require- power grounds are to be kept separating and finally combined using ground plane construction or single point ments rather than actual capacitance requirements. High frequency decoupling capacitors should be placed grounding. Figure 2 illustrates the layout, with bold lines indicating high current paths. Components along the bold as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit lines should be placed close together. Below is a checklist for your layout: board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic 1. Firstly, to initial the layout by placing the power components. Orient the power circuitry to achieve a clean power flow path. If possible, make all the con- capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equiva- nections on one side of the PCB with wide and copper filled areas. lent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. + VIN - Inductor Value Calculation 1 2 NC VIN The operating frequency and inductor selection are inter6 related in that higher operating frequencies permit the use of a smaller inductor for the same amount of inductor EN 5 COMP C3 FB AGND 3 Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple + 7 C 2 Load VOUT PGND R3 equation (2) shows that the inductance value has a direct effect on ripple current. L1 9 U1 APW7145 Compensation Network ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The C1 LX LX - 8 R1 4 R2 C4(Optional) Feedback Divider Figure 2. Current Path Diagram and greater core losses. A reasonable starting point for setting ripple current is ∆I ≤ 0.4 ⋅ IOUT(MAX). Please be no- 2. In Figure 2, the loops with same color bold lines con- ticed that the maximum ripple current occurs at the maximum input voltage. The minimum inductance of the in- duct high slew rate current. These interconnecting impedances should be minimized by using wide and short ductor is calculated by using the following equation: printed circuit traces. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 16 www.anpec.com.tw APW7145 Application Information (Cont.) Layout Consideration (Cont.) 3. Keep the sensitive small signal nodes (FB and COMP) away from switching nodes (LX or others) on the PCB. Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid switching noise. Connect the ground of feedback divider directly to the AGND pin of the IC using a dedicated ground trace. 4. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. Use a wide power ground plane to connect the C1 and C2 to provide a low impedance path between the components for large and high slew rate current. VIN VOUT Ground C2 C1 1 2 3 4 7 VLX L1 8 5 6 APW7145 SOP-8P For dissipating heat VIN Ground VOUT Ground C2 C1 1 2 3 4 7 VLX L1 8 6 5 APW7145 DFN4x4 For dissipating heat Ground Figure 3. Recommended Layout Diagram Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 17 www.anpec.com.tw APW7145 Package Information SOP-8P -T- SEATING PLANE < 4 mils D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE θ L VIEW A S Y M B O L A SOP-8P INCHES MILLIMETERS MAX. MIN. MIN. MAX. 1.60 0.063 0.000 0.15 0.006 A1 0.00 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 D1 2.50 3.50 0.098 0.138 0.244 0.049 E 5.80 6.20 0.228 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0o C 8o C θ 0oC 8o C Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 18 www.anpec.com.tw APW7145 Package Information DFN4x4-8 A Pin 1 b E D D2 A1 A3 L K E2 Pin 1 Corner e S Y M B O L DFN4x4-8 INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.25 0.35 0.010 0.014 D 3.90 4.10 0.154 0.161 D2 3.10 3.30 0.122 0.130 E 3.90 4.10 0.154 0.161 E2 2.40 2.60 0.094 0.102 0.60 0.016 e 0.80 BSC L 0.40 K 0.20 0.031 BSC 0.024 0.008 Note : 1. Followed from JEDEC MO-229 VGGB. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 19 www.anpec.com.tw APW7145 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-8P Application DFN4x4-8 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 4.0±0.10 8.0±0.10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type SOP-8P DFN4x4-8 Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 Unit Tape & Reel Tape & Reel Quantity 2500 3000 20 www.anpec.com.tw APW7145 Taping Direction Information SOP-8P USER DIRECTION OF FEED DFN4x4-8 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 21 www.anpec.com.tw APW7145 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 22 www.anpec.com.tw APW7145 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.7 - Mar., 2011 23 www.anpec.com.tw