APW8716 Preliminary High Input Voltage 12A PWM Converter With Adj. Soft Start Features General Description • Adjustable Output Voltage from +0.8V to +12V The APW8716 is a 12A, synchronous, step-down con- - 0.8V Reference Voltage verter with integrated 9.7mΩ N-channel High-Side MOSFET and 5.2mΩ Low-Side MOSFET. The APW8716 - +1% Accuracy over Temperature • steps down high voltage to generate low-voltage chipset or RAM supplies in notebook computers. Operates from An Input Battery Voltage Range of +2.7V to +28V • Power-On-Reset Monitoring on VCC pin • Excellent line and load transient responses • PFM mode for increased light load efficiency • Programmable PWM Frequency from 300kHz to The APW8716 provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. In Pulse Frequency Mode (PFM), the APW8716 provides very high efficiency over light to heavy loads with loadingmodulated switching frequencies. In PWM Mode, the converter works nearly at constant frequency for low-noise 1000kHz • Integrated 9.7mΩ at VCC=5V N-Channel MOSFET requirements. The APW8716 is equipped with accurate current-limit, out- For High Side • put under-voltage, and output over-voltage protections, perfect for various applications. A Power-On-Reset func- Integrated 5.2mΩ at VCC=5V N-Channel MOSFET For Low Side • Integrated Bootstrap Forward P-CH MOSFET • External Adjustable Soft-Start and Soft-Stop • Selectable Forced PWM or automatic PFM/PWM tion monitors the voltage on VCC to prevent wrong operation during power-on. The APW8716 has external adjustable soft-start and built-in an integrated output discharge method for soft stop. A soft-start ramps up the mode • output voltage with programmable timing to reduce the start-up current. A soft-stop function actively discharges Power Good Monitoring • 70% Under-Voltage Protection • 125% Over-Voltage Protection • Current-Limit Protection • Over-Temperature Protection • TQFN-30 5mmx5mm package • Lead Free and Green Device Available (RoHS the output capacitors. The APW8716 is available in TQFN5x5-30 (Power PAK). - Using Sense Low-Side MOSFET’s RDS(ON) Applications Compliant) • • Notebook • Table PC • Hand-Held Portable • AIO PC • Set-top boxes • LCD TV Mother Board ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 1 www.anpec.com.tw APW8716 Preliminary Simplified Application Circuit VCC EN RPOK VIN POK VIN H/L L1 PFM VOUT LX CSS SS COUT APW8716 Ordering and Marking Information Package Code QB: TQFN5x5-30 Operating Ambient Temperature Range I : -40 to 85 °C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device G : Halogen and Lead Free Device APW8716 Assembly Material Handling Code Temperature Range Package Code APW8716 QB : XXXXX - Date Code APW8716 XXXXX LX LX LX BOOT PGND VCC SS Pin Configuration AGND Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). 30 29 28 27 26 25 24 23 POK 1 22 LX EN 2 21 LX PFM 3 AGND 20 LX AGND 4 19 PGND LX FB 5 18 PGND 17 PGND TON 6 16 PGND VIN PGND PGND 12 13 14 VIN 9 10 11 VIN VIN 8 PGND 15 PGND VIN NC 7 TQFN5x5-30 (TOP VIEW) =Exposed and Thermal Pad Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 2 www.anpec.com.tw APW8716 Preliminary Absolute Maximum Ratings (Note 1) Symbol VV CC VIN VTON VBOOT-GND Parameter VCC Supply Voltage (VCC to AGND) -0.3 ~ 7 V -0.3 ~ 30 V TON Supply Voltage (TON to AGND) -0.3 ~ 30 V BOOT Supply Voltage (BOOT to AGND) -0.3 ~ 37 V -0.3 ~ 7 V -0.3 ~ +0.3 V -0.3 ~ 7 V -5 ~ 32 -0.3 ~ 30 V BOOT Supply Voltage (BOOT to LX) VGND AGND to PGND All Other Pins (POK, EN, FB, SS and PFM to AGND) LX Voltage (LX to GND) VLX TSTG TSDR Unit VIN Supply Voltage (VIN to AGND) VBOOT TJ Rating <20ns pulse width >20ns pulse width Junction Temperature Storage Temperature Maximum Lead Soldering Temperature(10 Seconds) 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Typical Value Junction-to-Ambient Resistance in free air (Note 2) Unit o 25 C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol VVCC VIN Parameter VCC Supply Voltage Converter Input Voltage Range Unit 4.5 ~ 5.5 V 2.7 ~ 28 V VOUT Converter Output Voltage 0.8 ~ 13.2 V IOUT Converter Output Current 0 ~ 12 A FSW Frequency Adjustable Range 100 ~ 1000 kHz CIN PWM1/2 Converter Input Capacitor (MLCC) 10 ~ µF VCC Output Capacitor (MLCC) 1.0 ~ µF C VCC TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o C C Note 3: Refer to the application circuit for further information. Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 3 www.anpec.com.tw APW8716 Preliminary Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=12V,VEN=5V and TA= -40 to 85 oC. Typical values are at TA=25oC. Sym bol P arame ter APW 8716 Tes t Condition Unit Min Typ Ma x - 0.8 - V -1.0 - +1.0 % 0 .02 - µA VO UT AND VFB VOLTAGE VREF Reference Voltage Regula tio n Accuracy IFB T STOP o o T A = - 40 C ~ 8 5 C FB Inp ut Bi as Curre nt FB=5V Outpu t Discha rge Time EN go low to output remain be low 0.1V - 5*Tss - - SUPP LY CURRE NT I VCC_N OR MAL VCC Q uiescent Supply Current EN=5 V, FB=0.835V, VCC=5 V - 0.7 1 mΑ I VCC _SHDN VCC S hutdown Cu rrent EN=G ND, VCC=5V - - 100 µA ON-TIME TIMER AND INTERNAL S OFT START TON Nominal on time VIN=12V, VOUT=1V, RTON=1 00kΩ 20 0 250 300 ns TOFF(MIN) Minimum off time VFB=0.75 V, VL X=-0.1V - 250 - ns Inte rnal Soft Star t Current Vss=0V ，Css=0.001u F to 0 .1u F 8 10 12 µA High Sid e MOSFET On Resistance VIN=12 V，V CC=5V - 9.7 1 4.6 mΩ Low Side MOSFET On Resistance VIN=12 V，V CC=5V - 5.2 7.8 mΩ VVCC – VBOOT-GN D, I F = 10mA - 0.5 0.7 V - - 0.5 µA 4.25 4 .35 4 .4 5 V - 100 - mV 2 .5 - VCC V 0 - 0.5 V ISS GATE DRIV ER BOOTSTRAP SWITCH VF IR BOOTSTRAP Vol tage Reverse Leakage VBOOT-GND = 3 0V, V LX = 25V, VVCC = 5 V VCC POR THRESHOLD VVC C_THF Rising VCC POR Threshol d Voltage VCC P OR Hyste resis CONTROL INP UTS EN Hi gh-Le vel Inpu t Voltage EN Low-Level Input Vo lta ge - 0.1 - µA PFM Hig h-Level Input Voltage 2 .5 - VCC V PFM L ow- Level In put Voltage 0 - 0.5 V - 0.1 - µA EN Leakag e PFM L eakage Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 E N=5V P FM=5V 4 www.anpec.com.tw APW8716 Preliminary Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=12V,VEN=5V and TA= -40 to 85 oC. Typical values are at TA=25oC. Symbol Parameter Test Condition APW8716 Unit Min Typ Max POK in from Lower (POK Goes High) 87 90 93 % POK out from Normal (POK Goes Low) 120 125 130 % - 0.1 - µA mA POWER-OK INDICATOR V POK IPOK POK Threshold POK Leakage Current V POK=5V POK Sink Current V POK=0.5V 1.25 7.5 - POK Out Debounce Time2 When run away 90% - 20 - µs POK Enable Delay Time From EN High to POK High - Tss - ms CURRENT SENSE I OCP OCP Threshold Valley Current of IL 18 - - A Zero Crossing Comparator Offset V GND-LX Voltage, PFM=0V -5 0 5 mV 65 70 75 % - 16 - µs PROTECTION VUV UVP Threshold UVP Debounce Interval VOVR TOTR UVP Enable Delay EN high to UVP workable OVP Rising Threshold1 OVP Occur - Tss - ms 120 125 130 % OVP Propagation Delay V FB Rising, Over Voltage=10mV - 3 - µs OTP Rising Threshold - 145 - o C OTP Hysteresis - 45 - o C Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 5 www.anpec.com.tw APW8716 Preliminary Pin Description PIN FUNCTION NO. NAME 1 POK 2 EN 3 PFM 4, 29 AGND 5 FB 6 TON 7 NC No connect. 8~11 VIN Battery Voltage Input Pin. VIN powers linear regulators and is also used for the constant on-time PWM on-time one-shot circuits. 12~19, 26 PGND 20~25 LX Junction Point of The High-Side MOSFET Source, Output Filter Inductor and The Low-Side MOSFET Drain for PWM. Connect this pin to the Source of the high-side MOSFET. LX serves as the lower supply rail for the UGATE high-side gate driver. LX is the current-sense input for the PWM. 27 BOOT Supply Input for The UGATE Gate Driver and an internal level-shift circuit. Connect to an external capacitor to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. 28 VCC Supply Voltage Input Pin for Control Circuitry, Connect +5V from the VCC pin to the GND pin. Decoupling at least 1µF of a MLCC capacitor from the VCC pin to the AGND pin. 30 SS Power-Good Output Pin of PWM. POK is an open-drain output used to indicate the status of the PWM output voltage. Connect the POK in to +5V through a pull-high resistor. PWM Enable. PWM is enabled when EN=1. When EN=0, PWM is in shutdown. PFM Selection Input. When the PFM is above high logic level, the Device is in force PWM mode. When the PFM is below low logic level, the device is in automatic PFM/PWM Mode. Signal Ground for The IC. Output Voltage Feedback Pin. This pin is connected to the resistive divider that set the desired output voltage. The POK, UVP, and OVP circuits detect this signal to report output voltage status. This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor R TON from TON pin to VIN pin. Power Ground of The LGATE Low-Side MOSFET Drivers. Soft Start Output. Connect a capacitor to GND to set the soft start interval. Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 6 www.anpec.com.tw APW8716 Preliminary Block Diagram POK LX TON PFM AGND 125% VREF Mean Value Circuit Delay Current Limit Reference 90% VREF OV UV 70% VREF FB VIN Fault Latch Logic VCC BOOT PWM Signal Controller 125% VREF Thermal Shutdown On-Time Generator LDO ZC Error Comparator PFM UG Gate Driver LX VCC LX VREF EN POR VLX LG Soft-Start Gate Driver PGND VCC SS Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 7 www.anpec.com.tw APW8716 Preliminary Typical Application Circuit When Vin=19V, Dual Power Input : 19V VIN EN CIN 10uF /25V X 4 (MLCC) Mode Selection PFM 91K TON 5V VCC VOUT L1 0.47uH APW8716 1.5V, 12A LX CVCC 1uF CBOOT 0.1uF RPOK RTOP 8.5k 100k BOOT COUT2 22uFx4 POK FB RGND 10k SS 0.01uF AGND Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 PGND 8 www.anpec.com.tw APW8716 Preliminary Typical Application Circuit When Vin=5V, Single Power Input : 5V VIN EN CIN 10uF /12V X 4 (MLCC) PFM 91K Mode Selection TON VCC VOUT L1 1.0uH 1.5V, 12A LX CVCC 1uF CBOOT 0.1uF APW8716 RPOK RTOP 8.5k 100k BOOT COUT2 22uFx4 POK FB RGND 10k SS 0.01uF AGND Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 PGND 9 www.anpec.com.tw APW8716 Preliminary Function Description Constant-On-Time PWM Controller with Input Feed- Where FSW is the nominal switching frequency of the Forward converter in PWM mode. The load current at handoff from PFM to PWM mode is The constant on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This ar- given by: chitecture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resistor, 1 VIN - VOUT × × TON-PFM 2 L V -V V 1 = IN OUT × × OUT 2L FSW VIN ILOAD (PFM to PWM) = so the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time controlled by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input Forced-PWM Mode voltage and directly proportional to output voltage. In PWM operation, the high-side switch on-time is determined by The Forced-PW M mode disables the zero-crossing comparator, which truncates the low-side switch on-time at the inductor current zero crossing. This causes the a switching frequency control circuit in the on-time generator block. low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. This in turn causes The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulat- the inductor current to reverse at light loads while UG maintains a duty factor of VOUT/VIN. The benefit of Forced- ing it at a constant frequency in PWM mode. The design improves the frequency variation and is more outstand- PWM mode is to keep the switching frequency fairly constant. The Forced-PWM mode is most useful for re- ing than a conventional constant on-time controller, which has large switching frequency variation over input voltage, ducing audio frequency noise, improving load-transient response, and providing sink-current capability for dy- output current and temperature. Both in PFM and PWM, the on-time generator, which senses input voltage on VIN pin, provides very fast on-time response to input line namic output voltage adjustment. When V PFM is above the PFM high threshold (2.5V, minimum), the converter is in forced-PWM mode. When transients. Another one-shot sets a minimum off-time (typical: VPFM is below the PFM low threshold (0.5V, maximum), the chip is in automatic PFM/PWM Mode. 250ns). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time oneshot has timed out. Power-On-Reset A Power-On-Reset (POR) function is designed to prevent Over-Current Protection of the PWM Converter In PFM mode, an automatic switchover to pulse-frequency wrong logic controls when the VCC voltage is low. The POR function continually monitors the bias supply volt- modulation (PFM) takes place at light loads. This switchover is affected by a comparator that truncates the age on the VCC pin if at least one of the enable pins is set high. When the rising VCC voltage reaches the rising low-side switch on-time at the inductor current zero crossing. This mechanism causes the threshold between POR voltage threshold (4.35V, typical), the POR signal goes high and the chip initiates soft-start operations. PFM and PWM operation to coincide with the boundary between continuous and discontinuous inductor-current Should this voltage drop lower than 4.25V (typical), the POR disables the chip. operation (also known as the critical conduction point). The on-time of PFM is given by: EN Pin Control W hen V EN is above the EN high threshold (2.5V, TON -PFM = 1 FSW × minimum), the converter is enabled. When VEN is below the EN low threshold (0.5V, maximum), the chip is in the VOUT VIN shutdown and only low leakage current is taken from VCC. Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 10 www.anpec.com.tw APW8716 Preliminary Function Description (Cont.) Soft-Start Under-Voltage Protection (UVP) The APW8716 provides the programmed soft-start func- In the process of operation, if a short circuit occurs, the tion to limit the inrush current. The soft-start time can be programmed by the external capacitor between SS and output voltage will drop quickly. When load current is bigger than current limit threshold value, the output voltage GND. Typical charge current is 10uA, and the soft-start time can be calculated by the following formula: will fall out of the required regulation range. The undervoltage protection circuit continually monitors the FB voltage after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the under TSS (µs) = 330 × CSS (nF) voltage threshold, the under voltage threshold is 70% of the nominal output voltage, the internal UVP delay counter The APW8716 integrates soft-start circuits to ramp up the output voltage of the converter to the programmed regu- starts to count. After 16ms de-bounce time, the device turns off both high side and low-side MOSEFET with lation set point at a predictable slew rate. The slew rate of output voltage is internally controlled to limit the latched. Toggling enable pin to low, or recycling VIN, will clear the latch and bring the chip back to operation. inrush current through the output capacitors during softstart process. When the EN pin is pulled above the rising EN threshold voltage, the device initiates a soft-start process to ramp up the output voltage. Over-Voltage Protection (OVP) The over voltage function monitors the output voltage by FB pin. Should the FB voltage increase over 125% of the During soft-start stage before the PGOOD pin is ready, the under voltage protection is prohibited. The over volt- reference voltage due to the high-side MOSFET failure or for other reasons, the over voltage protection comparator age and current limit protection functions are enabled. If the output capacitor has residue voltage before startup, designed with a 3µs noise filter will force the low-side both low-side and high-side MOSFETs are in off-state until the soft start voltage equal the VFB voltage. This will MOSFET gate driver fully turn on and latch high. This action actively pulls down the output voltage. ensure the output voltage starts from its existing voltage level. This OVP scheme only clamps the voltage overshoot, and does not invert the output voltage when otherwise In the event of under-voltage, over-voltage, over-temperature or shutdown, the chip enables the soft-stop function. activated with a continuously high output from low-side MOSFET driver. It’s a common problem for OVP schemes The soft-stop function discharges the output voltages by low side turns MOSFET on linearly. with a latch. Once an over-voltage fault condition is set, it can only be reset by toggling EN or VIN power-on-reset signal. Power Good Indicator POK is actively held low in shutdown and soft-start status. Current Limit In the soft-start process, the POK is an open-drain. When the soft-start is finished, the POK is released. In normal The current limit circuit employs a "valley" current-sensing algorithm (See Figure 1). The APW8716 uses the low-side MOSFET’s RDS(ON) of the synchronous rectifier operation, the POK window is from 90% to 125% of the converter reference voltage. When the output voltage has as a current-sensing element. If the magnitude of the current-sense signal at LX pin is above the current-limit to stay within this window, POK signal will become high. When the output voltage outruns 90% or 125% of the threshold 18A(minimum), the PWM is not allowed to initiate a new cycle. The actual peak current is greater than target voltage, POK signal will be pulled low immediately. In order to prevent false POK drop, capacitors need to the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit char- parallel at the output to confine the voltage deviation with severe load step transient. Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 acteristic and maximum load capability are a function of the sense resistance, inductor value, and input voltage. 11 www.anpec.com.tw APW8716 Preliminary Function Description (Cont.) Programming the On-Time Control and PWM Switch- Current Limit( Cont.) ing Frequency INDUCTOR CURRENT IPEAK IOUT The APW8716 does not use a clock signal to produce PWM. The device uses the constant on-time control architecture to produce pseudo-fixed frequency with input voltage feed-forward. The on-time pulse width is propor- ΔI tional to output voltage VOUT and inverse proportional to input voltage VIN. In PWM, the on-time calculation is writ- ILIMIT ten as below equation. 0 Time TON = Figure 1. Current Limit algorithm 26.3 × 10-12 × RTON(Ω) VIN(V) Where: RTON is the resistor connected from TON pin to VIN pin. The PWM controller uses the low-side MOSFETs on-re- Furthermore, The approximate PWM switching frequency is written as: sistance R DS(ON) to monitor the current for protection against shorted outputs. The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user should determine the maximum RDS(ON) in manufacture’s TON = datasheet. The PCB layout guidelines should ensure that noise and DC errors do not corrupt the current-sense signals at LX. Place the hottest power MOSEFTs as close to the IC as D ，FSW = FSW VOUT VIN TON Where: FSW is the PWM switching frequency. possible for best thermal coupling. When combined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance. Over-Temperature Protection (OTP) When the junction temperature increases above the rising threshold temperature TOTR, the IC will enter the over temperature protection state that suspends the PWM, which forces the UG and LG gate drivers output low. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 45oC. The OTP designed with a 45oC hysteresis lowers the average TJ during continuous thermal overload conditions, which increases lifetime of the APW8716. Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 12 www.anpec.com.tw APW8716 Preliminary Application Information Output Inductor Selection A good starting point is to choose the ripple current to be The output voltage is adjustable from 0.8V to 12V with a approximately 30% of the maximum output current. Once the inductance value has been chosen, selecting an in- resistor-divider connected with FB, GND, and converterˇ¦s output. Using 1% or better resistors for the resistor-di- ductor that is capable of carrying the required peak current without going into saturation.In some types of vider is recommended. The output voltage is determined by: VOUT = 0.8 × (1 + inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage. Besides, the inductor needs to have low DCR to reduce the loss of efficiency. R TOP ) R GND Where 0.8 is the reference voltage, RTOP is the resistor connected from converter¡¦s output to FB, and RGND is the Output Capacitor Selection resistor connected from FB to GND. Suggested RGND is in the range from 1k to 20kΩ. To prevent stray pickup, locate are factors that have to be taken into consideration when selecting an output capacitor. Higher capacitor value and resistors RTOP and RGND close to APW8716. lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR Output voltage ripple and the transient voltage deviation capacitors is recommended for switching regulator applications. In addition to high frequency noise related Output Inductor Selection The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage to MOSFET turn-on and turnoff, the output voltage ripple includes the capacitance voltage drop ∆VCOUT and ESR is fixed, it can be written as: D= voltage drop ∆V ESR caused by the AC peak-to-peak inductor’s current. These two voltages can be represented VOUT VIN by: ∆COUT = The inductor value (L) determines the inductor ripple current, IRIPPLE, and affects the load transient response. Higher inductor value reduces the inductor’s ripple cur- ∆VESR = IRIPPLE × RESR rent and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: IRIPPLE = IRIPPLE 8 × COUT × FSW These two components constitute a large portion of the total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired VIN - VOUT VOUT × FSW × L VIN ESR value. If the output of the converter has to support another load with high pulsating current, more capacitors Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s ripple current and the regu- decoupling capacitor (1µF) in parallel for bypassing the noise is also recommended, and the voltage rating of the lator load transient response time. A smaller inductor will give the regulator a faster load output capacitors are also must be considered. To support a load transient that is faster than the switch- transient response at the expense of higher ripple current. Increasing the switching frequency (FSW ) also reduces ing frequency, more capacitors are needed for reducing the voltage excursion during load step change. Another the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipa- aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the tion of the converter. The maximum ripple current occurs at the maximum input voltage. rated RMS current specified on the capacitors in order to prevent the capacitor from over-heating. Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 13 www.anpec.com.tw APW8716 Preliminary Application Information (Cont.) Input Capacitor Selection Layout Consideration The input capacitor is chosen based on the voltage rating In any high switching frequency converter, a correct layout is important to ensure proper operation of the and the RMS current rating. For reliable operation, selecting the capacitor voltage rating to be at least 1.3 times regulator. W ith power devices switching at higher frequency, the resulting current transient will cause volt- higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, age spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current. turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. For low-duty notebook applications, ceramic capacitor is recommended. The capacitors must be connected be- During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impedance PCB layout. diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In Thermal Consideration Because the APW8716 build-in high-side and low-side MOSFET, the heat dissipated may exceed the maximum general, using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. Besides, signal and power grounds are to be kept separate and finally combined using ground junction temperature of the part in applications. If the junction temperature reaches approximately 150 oC, both plane construction or single point grounding. The best tie-point between the signal ground and the power ground power switches will be turned off and the LX node will become high impedance. To avoid the APW8716 from exceeding the maximum junction temperature, the user is at the negative side of the output capacitor on each channel, where there is less noise. Noisy traces beneath will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dis- the IC are not recommended. Below is a checklist for your layout: - Keep the switching nodes (BOOT and LX) away from sipated exceeds the maximum junction temperature of the part. The main power dissipated by the part is sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these approximated: nodes as short as possible and there should be no other weak signal traces in parallel with theses traces 2 PUPPER = IOUT (1 + TC)(RDS(ON) )D + 0.5(IOUT )(VIN )(tSW )FSW on any layer. - The large layout plane between the drain of the MOSFETs 2 PLOWER = IOUT (1 + TC)(RDS(ON) )(1- D) IOUT is the load current (VIN and LX nodes) can get better heat sinking. - The current sense resistor should be close to OCSET TC is the temperature dependency of RDS(ON) FSW is the switching frequency pin to avoid parasitic capacitor effect and noise coupling. - Decoupling capacitors, the resistor-divider, and boot tSW is the switching interval capacitor should be close to their pins. - The output bulk capacitors should be close to the loads. D is the duty cycle Note that both internal MOSFETs have conduction losses The input capacitor’s ground should be close to the grounds of the output capacitors. while the upper MOSFET include an additional transition loss. The switching internal, t SW , is the function of the - Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces reverse transfer capacitance CRSS. The (1+TC) term factors in the temperature dependency of the RDS(ON) and can can’t be close to the switching signal traces (BOOT and LX). be extracted from the "RDS(ON) vs. Temperature" curve of the power MOSFET. In APW8716 case, the RDS(ON) is about 30mW from specification table. Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 14 www.anpec.com.tw APW8716 Preliminary Application Information (Cont.) Recommended Minimum Footprint TQFN5x5-30 Unit:mm 5mm ThermalVia diameter 0.3mm X 16 0.5* 0.4 0.25 1.39 1.9 AGND 0.4 3.7 0.5 LX 5mm 2.22 0.25 0.25 1.07 0.4 VIN * Just Recommend Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 15 www.anpec.com.tw APW8716 Preliminary Package Information TQFN5x5-30 D b E A Pin 1 A1 K1 D1 D2 A3 NX E1 aaa C E2 K1 Pin 1 Corner e KL D3 S Y M B O L A A1 A3 b D D1 D2 D3 E E1 E2 e L K K1 aaa Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 TQFN5x5-30 MILLIMETERS INCHES MIN. MAX. MIN. MAX. 0.80 0.70 0.028 0.031 0.000 0.002 0.05 0.00 0.20 REF 0.20 0.30 4.90 5.10 2.12 2.32 0.97 1.17 3.56 3.76 4.90 5.10 1.29 1.49 1.80 2.00 0.50 BSC 0.35 0.45 0.20 0.37 REF 0.008 REF 0.008 0.012 0.193 0.201 0.083 0.091 0.038 0.046 0.140 0.148 0.193 0.201 0.051 0.059 0.071 0.079 0.08 0.003 16 0.020 BSC 0.014 0.018 0.008 0.015 REF www.anpec.com.tw APW8716 Preliminary Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN5x5 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.50±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 2.00±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 5.35±0.20 5.35±0.20 1.00±0.20 4.00±0.10 8.00±0.10 (mm) Devices Per Unit Package Type Unit Quantity TQFN5x5 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 17 www.anpec.com.tw APW8716 Preliminary Taping Direction Information TQFN5x5 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 18 www.anpec.com.tw APW8716 Preliminary Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 19 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8716 Preliminary Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. P.3 - Nov., 2015 20 www.anpec.com.tw